Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <stdint.h> |
| 30 | #include <debug.h> |
| 31 | #include <reg.h> |
| 32 | #include <mmc.h> |
| 33 | #include <clock.h> |
| 34 | #include <platform/clock.h> |
| 35 | #include <platform/iomap.h> |
| 36 | |
| 37 | void hsusb_clock_init(void) |
| 38 | { |
| 39 | int ret; |
| 40 | struct clk *iclk, *cclk; |
| 41 | |
| 42 | ret = clk_get_set_enable("usb_iface_clk", 0, 1); |
| 43 | if(ret) |
| 44 | { |
| 45 | dprintf(CRITICAL, "failed to set usb_iface_clk ret = %d\n", ret); |
| 46 | ASSERT(0); |
| 47 | } |
| 48 | |
| 49 | ret = clk_get_set_enable("usb_core_clk", 75000000, 1); |
| 50 | if(ret) |
| 51 | { |
| 52 | dprintf(CRITICAL, "failed to set usb_core_clk ret = %d\n", ret); |
| 53 | ASSERT(0); |
| 54 | } |
| 55 | |
| 56 | /* Wait for the clocks to be stable since we are disabling soon after. */ |
| 57 | mdelay(1); |
| 58 | |
| 59 | iclk = clk_get("usb_iface_clk"); |
| 60 | cclk = clk_get("usb_core_clk"); |
| 61 | |
| 62 | clk_disable(iclk); |
| 63 | clk_disable(cclk); |
| 64 | |
| 65 | /* Wait for the clock disable to complete. */ |
| 66 | mdelay(1); |
| 67 | |
| 68 | /* Start the block reset for usb */ |
| 69 | writel(1, USB_HS_BCR); |
| 70 | |
| 71 | /* Wait for reset to complete. */ |
| 72 | mdelay(1); |
| 73 | |
| 74 | /* Take usb block out of reset */ |
| 75 | writel(0, USB_HS_BCR); |
| 76 | |
| 77 | /* Wait for the block to be brought out of reset. */ |
| 78 | mdelay(1); |
| 79 | |
| 80 | ret = clk_enable(iclk); |
| 81 | |
| 82 | if(ret) |
| 83 | { |
| 84 | dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret); |
| 85 | ASSERT(0); |
| 86 | } |
| 87 | |
| 88 | ret = clk_enable(cclk); |
| 89 | |
| 90 | if(ret) |
| 91 | { |
| 92 | dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret); |
| 93 | ASSERT(0); |
| 94 | } |
| 95 | |
Tanya Finkel | 90abab7 | 2014-07-30 09:55:23 +0300 | [diff] [blame] | 96 | ret = clk_get_set_enable("usb_phy_cfg_ahb2phy_clk", 0, 1); |
| 97 | if(ret) |
| 98 | { |
| 99 | dprintf(CRITICAL, "failed to enable usb_phy_cfg_ahb2phy_clk = %d\n", ret); |
| 100 | ASSERT(0); |
| 101 | } |
Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 102 | } |
| 103 | |
| 104 | void clock_init_mmc(uint32_t interface) |
| 105 | { |
| 106 | char clk_name[64]; |
| 107 | int ret; |
| 108 | |
| 109 | snprintf(clk_name, sizeof(clk_name), "sdc%u_iface_clk", interface); |
| 110 | |
| 111 | /* enable interface clock */ |
| 112 | ret = clk_get_set_enable(clk_name, 0, 1); |
| 113 | if(ret) |
| 114 | { |
| 115 | dprintf(CRITICAL, "failed to set sdc%u_iface_clk ret = %d\n", interface, ret); |
| 116 | ASSERT(0); |
| 117 | } |
| 118 | } |
| 119 | |
| 120 | /* Configure MMC clock */ |
| 121 | void clock_config_mmc(uint32_t interface, uint32_t freq) |
| 122 | { |
| 123 | int ret; |
| 124 | uint32_t reg; |
| 125 | char clk_name[64]; |
| 126 | |
| 127 | snprintf(clk_name, sizeof(clk_name), "sdc%u_core_clk", interface); |
| 128 | |
| 129 | if(freq == MMC_CLK_400KHZ) |
| 130 | { |
| 131 | ret = clk_get_set_enable(clk_name, 400000, 1); |
| 132 | } |
| 133 | else if(freq == MMC_CLK_50MHZ) |
| 134 | { |
| 135 | ret = clk_get_set_enable(clk_name, 50000000, 1); |
| 136 | } |
| 137 | else if(freq == MMC_CLK_96MHZ) |
| 138 | { |
| 139 | ret = clk_get_set_enable(clk_name, 100000000, 1); |
| 140 | } |
| 141 | else if(freq == MMC_CLK_192MHZ) |
| 142 | { |
| 143 | ret = clk_get_set_enable(clk_name, 192000000, 1); |
| 144 | } |
Channagoud Kadabi | e804d64 | 2014-08-20 17:43:57 -0700 | [diff] [blame] | 145 | else if(freq == MMC_CLK_200MHZ) |
| 146 | { |
| 147 | ret = clk_get_set_enable(clk_name, 200000000, 1); |
| 148 | } |
Channagoud Kadabi | 6b3a998 | 2014-06-05 12:59:46 -0700 | [diff] [blame] | 149 | else if(freq == MMC_CLK_400MHZ) |
| 150 | { |
| 151 | ret = clk_get_set_enable(clk_name, 384000000, 1); |
| 152 | } |
Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 153 | else |
| 154 | { |
| 155 | dprintf(CRITICAL, "sdc frequency (%u) is not supported\n", freq); |
| 156 | ASSERT(0); |
| 157 | } |
| 158 | |
| 159 | |
| 160 | if(ret) |
| 161 | { |
| 162 | dprintf(CRITICAL, "failed to set sdc%u_core_clk ret = %d\n", interface, ret); |
| 163 | ASSERT(0); |
| 164 | } |
| 165 | } |
| 166 | |
| 167 | /* Configure UART clock based on the UART block id*/ |
| 168 | void clock_config_uart_dm(uint8_t id) |
| 169 | { |
| 170 | int ret; |
| 171 | char iclk[64]; |
| 172 | char cclk[64]; |
| 173 | |
| 174 | snprintf(iclk, sizeof(iclk), "uart%u_iface_clk", id); |
| 175 | snprintf(cclk, sizeof(cclk), "uart%u_core_clk", id); |
| 176 | |
| 177 | ret = clk_get_set_enable(iclk, 0, 1); |
| 178 | if(ret) |
| 179 | { |
| 180 | dprintf(CRITICAL, "failed to set uart%u_iface_clk ret = %d\n", id, ret); |
| 181 | ASSERT(0); |
| 182 | } |
| 183 | |
| 184 | ret = clk_get_set_enable(cclk, 7372800, 1); |
| 185 | if(ret) |
| 186 | { |
| 187 | dprintf(CRITICAL, "failed to set uart%u_core_clk ret = %d\n", id, ret); |
| 188 | ASSERT(0); |
| 189 | } |
| 190 | } |
| 191 | |
| 192 | /* Function to asynchronously reset CE (Crypto Engine). |
| 193 | * Function assumes that all the CE clocks are off. |
| 194 | */ |
| 195 | static void ce_async_reset(uint8_t instance) |
| 196 | { |
| 197 | } |
| 198 | |
| 199 | void clock_ce_enable(uint8_t instance) |
| 200 | { |
| 201 | } |
| 202 | |
| 203 | void clock_ce_disable(uint8_t instance) |
| 204 | { |
| 205 | } |
| 206 | |
| 207 | void clock_config_ce(uint8_t instance) |
| 208 | { |
| 209 | /* Need to enable the clock before disabling since the clk_disable() |
| 210 | * has a check to default to nop when the clk_enable() is not called |
| 211 | * on that particular clock. |
| 212 | */ |
| 213 | clock_ce_enable(instance); |
| 214 | |
| 215 | clock_ce_disable(instance); |
| 216 | |
| 217 | ce_async_reset(instance); |
| 218 | |
| 219 | clock_ce_enable(instance); |
| 220 | |
| 221 | } |
Channagoud Kadabi | 3dcc4ed | 2014-04-10 14:59:41 -0700 | [diff] [blame] | 222 | |
| 223 | void clock_usb30_gdsc_enable(void) |
| 224 | { |
| 225 | uint32_t reg = readl(GCC_USB30_GDSCR); |
| 226 | |
| 227 | reg &= ~(0x1); |
| 228 | |
| 229 | writel(reg, GCC_USB30_GDSCR); |
| 230 | } |
| 231 | |
| 232 | /* enables usb30 clocks */ |
| 233 | void clock_usb30_init(void) |
| 234 | { |
| 235 | int ret; |
| 236 | |
| 237 | ret = clk_get_set_enable("usb30_iface_clk", 0, 1); |
| 238 | if(ret) |
| 239 | { |
| 240 | dprintf(CRITICAL, "failed to set usb30_iface_clk. ret = %d\n", ret); |
| 241 | ASSERT(0); |
| 242 | } |
| 243 | |
| 244 | clock_usb30_gdsc_enable(); |
| 245 | |
| 246 | ret = clk_get_set_enable("usb30_master_clk", 125000000, 1); |
| 247 | if(ret) |
| 248 | { |
| 249 | dprintf(CRITICAL, "failed to set usb30_master_clk. ret = %d\n", ret); |
| 250 | ASSERT(0); |
| 251 | } |
| 252 | |
| 253 | ret = clk_get_set_enable("usb30_phy_aux_clk", 1200000, 1); |
| 254 | if(ret) |
| 255 | { |
| 256 | dprintf(CRITICAL, "failed to set usb30_phy_aux_clk. ret = %d\n", ret); |
| 257 | ASSERT(0); |
| 258 | } |
| 259 | |
| 260 | ret = clk_get_set_enable("usb30_mock_utmi_clk", 60000000, 1); |
| 261 | if(ret) |
| 262 | { |
| 263 | dprintf(CRITICAL, "failed to set usb30_mock_utmi_clk ret = %d\n", ret); |
| 264 | ASSERT(0); |
| 265 | } |
| 266 | |
| 267 | ret = clk_get_set_enable("usb30_sleep_clk", 0, 1); |
| 268 | if(ret) |
| 269 | { |
| 270 | dprintf(CRITICAL, "failed to set usb30_sleep_clk ret = %d\n", ret); |
| 271 | ASSERT(0); |
| 272 | } |
| 273 | |
Channagoud Kadabi | 3c2be1c | 2014-06-01 18:59:21 -0700 | [diff] [blame] | 274 | ret = clk_get_set_enable("usb_phy_cfg_ahb2phy_clk", 0, 1); |
| 275 | if(ret) |
| 276 | { |
| 277 | dprintf(CRITICAL, "failed to enable usb_phy_cfg_ahb2phy_clk = %d\n", ret); |
| 278 | ASSERT(0); |
| 279 | } |
| 280 | |
Channagoud Kadabi | 3dcc4ed | 2014-04-10 14:59:41 -0700 | [diff] [blame] | 281 | pm8x41_lnbb_clock_ctrl(1); |
| 282 | } |
| 283 | |
| 284 | void clock_bumpup_pipe3_clk() |
| 285 | { |
| 286 | int ret = 0; |
| 287 | |
| 288 | ret = clk_get_set_enable("usb30_pipe_clk", 0, 1); |
| 289 | if(ret) |
| 290 | { |
| 291 | dprintf(CRITICAL, "failed to set usb30_pipe_clk. ret = %d\n", ret); |
| 292 | ASSERT(0); |
| 293 | } |
| 294 | |
| 295 | return; |
| 296 | } |
Dhaval Patel | 2c11a18 | 2014-08-12 14:17:41 -0700 | [diff] [blame] | 297 | |
| 298 | void mdp_gdsc_ctrl(uint8_t enable) |
| 299 | { |
| 300 | uint32_t reg = 0; |
| 301 | reg = readl(MDP_GDSCR); |
| 302 | if (enable) { |
| 303 | if (!(reg & GDSC_POWER_ON_BIT)) { |
| 304 | reg &= ~(BIT(0) | GDSC_EN_FEW_WAIT_MASK); |
| 305 | reg |= GDSC_EN_FEW_WAIT_256_MASK; |
| 306 | writel(reg, MDP_GDSCR); |
| 307 | while(!(readl(MDP_GDSCR) & (GDSC_POWER_ON_BIT))); |
| 308 | } else { |
| 309 | dprintf(INFO, "MDP GDSC already enabled\n"); |
| 310 | } |
| 311 | } else { |
| 312 | reg |= BIT(0); |
| 313 | writel(reg, MDP_GDSCR); |
| 314 | while(readl(MDP_GDSCR) & (GDSC_POWER_ON_BIT)); |
| 315 | } |
| 316 | } |
| 317 | |
| 318 | /* Configure MDP clock */ |
| 319 | void mdp_clock_enable(void) |
| 320 | { |
| 321 | int ret; |
| 322 | |
| 323 | /* Set MDP clock to 240MHz */ |
| 324 | ret = clk_get_set_enable("mdp_ahb_clk", 0, 1); |
| 325 | if(ret) |
| 326 | { |
| 327 | dprintf(CRITICAL, "failed to set mdp_ahb_clk ret = %d\n", ret); |
| 328 | ASSERT(0); |
| 329 | } |
| 330 | |
| 331 | ret = clk_get_set_enable("mdss_mdp_clk_src", 240000000, 1); |
| 332 | if(ret) |
| 333 | { |
| 334 | dprintf(CRITICAL, "failed to set mdp_clk_src ret = %d\n", ret); |
| 335 | ASSERT(0); |
| 336 | } |
| 337 | |
| 338 | ret = clk_get_set_enable("mdss_vsync_clk", 0, 1); |
| 339 | if(ret) |
| 340 | { |
| 341 | dprintf(CRITICAL, "failed to set mdss vsync clk ret = %d\n", ret); |
| 342 | ASSERT(0); |
| 343 | } |
| 344 | |
| 345 | ret = clk_get_set_enable("mdss_mdp_clk", 0, 1); |
| 346 | if(ret) |
| 347 | { |
| 348 | dprintf(CRITICAL, "failed to set mdp_clk ret = %d\n", ret); |
| 349 | ASSERT(0); |
| 350 | } |
Dhaval Patel | 2c11a18 | 2014-08-12 14:17:41 -0700 | [diff] [blame] | 351 | } |
| 352 | |
| 353 | void mdp_clock_disable() |
| 354 | { |
| 355 | clk_disable(clk_get("mdss_vsync_clk")); |
| 356 | clk_disable(clk_get("mdss_mdp_clk")); |
Dhaval Patel | 2c11a18 | 2014-08-12 14:17:41 -0700 | [diff] [blame] | 357 | clk_disable(clk_get("mdss_mdp_clk_src")); |
| 358 | clk_disable(clk_get("mdp_ahb_clk")); |
| 359 | |
| 360 | } |
| 361 | |
| 362 | void mmss_bus_clock_enable(void) |
| 363 | { |
| 364 | int ret; |
| 365 | /* Configure MMSSNOC AXI clock */ |
| 366 | ret = clk_get_set_enable("mmss_mmssnoc_axi_clk", 100000000, 1); |
| 367 | if(ret) |
| 368 | { |
| 369 | dprintf(CRITICAL, "failed to set mmssnoc_axi_clk ret = %d\n", ret); |
| 370 | ASSERT(0); |
| 371 | } |
| 372 | |
| 373 | /* Configure S0 AXI clock */ |
| 374 | ret = clk_get_set_enable("mmss_s0_axi_clk", 100000000, 1); |
| 375 | if(ret) |
| 376 | { |
| 377 | dprintf(CRITICAL, "failed to set mmss_s0_axi_clk ret = %d\n", ret); |
| 378 | ASSERT(0); |
| 379 | } |
| 380 | |
| 381 | /* Configure AXI clock */ |
| 382 | ret = clk_get_set_enable("mdss_axi_clk", 100000000, 1); |
| 383 | if(ret) |
| 384 | { |
| 385 | dprintf(CRITICAL, "failed to set mdss_axi_clk ret = %d\n", ret); |
| 386 | ASSERT(0); |
| 387 | } |
| 388 | } |
| 389 | |
| 390 | void mmss_bus_clock_disable(void) |
| 391 | { |
| 392 | /* Disable MDSS AXI clock */ |
| 393 | clk_disable(clk_get("mdss_axi_clk")); |
| 394 | |
| 395 | /* Disable MMSSNOC S0AXI clock */ |
| 396 | clk_disable(clk_get("mmss_s0_axi_clk")); |
| 397 | |
| 398 | /* Disable MMSSNOC AXI clock */ |
| 399 | clk_disable(clk_get("mmss_mmssnoc_axi_clk")); |
| 400 | } |
| 401 | |
| 402 | void mmss_dsi_clock_enable(uint32_t dsi_pixel0_cfg_rcgr, uint32_t dual_dsi, |
| 403 | uint8_t pclk0_m, uint8_t pclk0_n, uint8_t pclk0_d) |
| 404 | { |
| 405 | int ret; |
| 406 | |
| 407 | /* Configure Byte clock -autopll- This will not change because |
| 408 | byte clock does not need any divider*/ |
| 409 | writel(0x100, DSI_BYTE0_CFG_RCGR); |
| 410 | writel(0x1, DSI_BYTE0_CMD_RCGR); |
| 411 | writel(0x1, DSI_BYTE0_CBCR); |
| 412 | |
| 413 | /* Configure Pixel clock */ |
| 414 | writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL0_CFG_RCGR); |
| 415 | writel(0x1, DSI_PIXEL0_CMD_RCGR); |
| 416 | writel(0x1, DSI_PIXEL0_CBCR); |
| 417 | |
| 418 | writel(pclk0_m, DSI_PIXEL0_M); |
| 419 | writel(pclk0_n, DSI_PIXEL0_N); |
| 420 | writel(pclk0_d, DSI_PIXEL0_D); |
| 421 | |
| 422 | /* Configure ESC clock */ |
| 423 | ret = clk_get_set_enable("mdss_esc0_clk", 0, 1); |
| 424 | if(ret) |
| 425 | { |
| 426 | dprintf(CRITICAL, "failed to set esc0_clk ret = %d\n", ret); |
| 427 | ASSERT(0); |
| 428 | } |
| 429 | |
| 430 | if (dual_dsi) { |
| 431 | /* Configure Byte 1 clock */ |
| 432 | writel(0x100, DSI_BYTE1_CFG_RCGR); |
| 433 | writel(0x1, DSI_BYTE1_CMD_RCGR); |
| 434 | writel(0x1, DSI_BYTE1_CBCR); |
| 435 | |
| 436 | /* Configure Pixel clock */ |
| 437 | writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL1_CFG_RCGR); |
| 438 | writel(0x1, DSI_PIXEL1_CMD_RCGR); |
| 439 | writel(0x1, DSI_PIXEL1_CBCR); |
| 440 | |
| 441 | writel(pclk0_m, DSI_PIXEL1_M); |
| 442 | writel(pclk0_n, DSI_PIXEL1_N); |
| 443 | writel(pclk0_d, DSI_PIXEL1_D); |
| 444 | |
| 445 | /* Configure ESC clock */ |
| 446 | ret = clk_get_set_enable("mdss_esc1_clk", 0, 1); |
| 447 | if(ret) |
| 448 | { |
| 449 | dprintf(CRITICAL, "failed to set esc1_clk ret = %d\n", ret); |
| 450 | ASSERT(0); |
| 451 | } |
| 452 | } |
| 453 | } |
| 454 | |
| 455 | void mmss_dsi_clock_disable(uint32_t dual_dsi) |
| 456 | { |
| 457 | /* Disable ESC clock */ |
| 458 | clk_disable(clk_get("mdss_esc0_clk")); |
| 459 | writel(0x0, DSI_BYTE0_CBCR); |
| 460 | writel(0x0, DSI_PIXEL0_CBCR); |
| 461 | |
| 462 | if (dual_dsi) { |
| 463 | /* Disable ESC clock */ |
| 464 | clk_disable(clk_get("mdss_esc1_clk")); |
| 465 | writel(0x0, DSI_BYTE1_CBCR); |
| 466 | writel(0x0, DSI_PIXEL1_CBCR); |
| 467 | } |
| 468 | } |