Xipeng Gu | 8f53d60 | 2019-05-10 10:51:55 +0800 | [diff] [blame] | 1 | /* Copyright (c) 2019, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #ifndef _PANEL_EDO_RM67162_QVGA_CMD_H_ |
| 30 | #define _PANEL_EDO_RM67162_QVGA_CMD_H_ |
| 31 | /*---------------------------------------------------------------------------*/ |
| 32 | /* HEADER files */ |
| 33 | /*---------------------------------------------------------------------------*/ |
| 34 | #include "panel.h" |
| 35 | |
| 36 | /*---------------------------------------------------------------------------*/ |
| 37 | /* Panel configuration */ |
| 38 | /*---------------------------------------------------------------------------*/ |
| 39 | static struct panel_config edo_rm67162_qvga_cmd_panel_data = { |
| 40 | "qcom,mdss_dsi_edo_rm67162_qvga_cmd", "dsi:0:", "qcom,mdss-dsi-panel", |
Xipeng Gu | dbec1bd | 2019-06-18 14:41:15 +0800 | [diff] [blame] | 41 | 10, 1, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL |
Xipeng Gu | 8f53d60 | 2019-05-10 10:51:55 +0800 | [diff] [blame] | 42 | }; |
| 43 | |
| 44 | /*---------------------------------------------------------------------------*/ |
| 45 | /* Panel resolution */ |
| 46 | /*---------------------------------------------------------------------------*/ |
| 47 | static struct panel_resolution edo_rm67162_qvga_cmd_panel_res = { |
| 48 | 320, 360, 140, 164, 8, 0, 6, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 |
| 49 | }; |
| 50 | |
| 51 | /*---------------------------------------------------------------------------*/ |
| 52 | /* Panel color information */ |
| 53 | /*---------------------------------------------------------------------------*/ |
| 54 | static struct color_info edo_rm67162_qvga_cmd_color = { |
| 55 | 24, 0, 0xff, 0, 0, 0 |
| 56 | }; |
| 57 | |
| 58 | /*---------------------------------------------------------------------------*/ |
| 59 | /* Panel on/off command information */ |
| 60 | /*---------------------------------------------------------------------------*/ |
| 61 | static char edo_rm67162_qvga_cmd_on_cmd0[] = { |
| 62 | 0x02, 0x00, 0x29, 0xC0, |
| 63 | 0xFE, 0x0A, 0xFF, 0xFF, |
| 64 | }; |
| 65 | |
| 66 | static char edo_rm67162_qvga_cmd_on_cmd1[] = { |
| 67 | 0x02, 0x00, 0x29, 0xC0, |
| 68 | 0x29, 0x90, 0xFF, 0xFF, |
| 69 | }; |
| 70 | |
| 71 | static char edo_rm67162_qvga_cmd_on_cmd2[] = { |
| 72 | 0x02, 0x00, 0x29, 0xC0, |
| 73 | 0xFE, 0x05, 0xFF, 0xFF, |
| 74 | }; |
| 75 | |
| 76 | static char edo_rm67162_qvga_cmd_on_cmd3[] = { |
| 77 | 0x02, 0x00, 0x29, 0xC0, |
| 78 | 0x05, 0x00, 0xFF, 0xFF, |
| 79 | }; |
| 80 | |
| 81 | static char edo_rm67162_qvga_cmd_on_cmd4[] = { |
| 82 | 0x02, 0x00, 0x29, 0xC0, |
| 83 | 0xFE, 0x00, 0xFF, 0xFF, |
| 84 | }; |
| 85 | |
| 86 | static char edo_rm67162_qvga_cmd_on_cmd5[] = { |
| 87 | 0x02, 0x00, 0x29, 0xC0, |
| 88 | 0x35, 0x00, 0xFF, 0xFF, |
| 89 | }; |
| 90 | |
| 91 | static char edo_rm67162_qvga_cmd_on_cmd6[] = { |
| 92 | 0x02, 0x00, 0x29, 0xC0, |
Xipeng Gu | dbec1bd | 2019-06-18 14:41:15 +0800 | [diff] [blame] | 93 | 0x51, 0xFF, 0xFF, 0xFF, |
Xipeng Gu | 8f53d60 | 2019-05-10 10:51:55 +0800 | [diff] [blame] | 94 | }; |
| 95 | |
| 96 | static char edo_rm67162_qvga_cmd_on_cmd7[] = { |
| 97 | 0x02, 0x00, 0x29, 0xC0, |
| 98 | 0x53, 0x20, 0xFF, 0xFF, |
| 99 | }; |
| 100 | |
| 101 | static char edo_rm67162_qvga_cmd_on_cmd8[] = { |
| 102 | 0x02, 0x00, 0x29, 0xC0, |
| 103 | 0x11, 0x00, 0xFF, 0xFF, |
| 104 | }; |
| 105 | |
| 106 | static char edo_rm67162_qvga_cmd_on_cmd9[] = { |
| 107 | 0x02, 0x00, 0x29, 0xC0, |
| 108 | 0x29, 0x00, 0xFF, 0xFF, |
| 109 | }; |
| 110 | |
| 111 | static struct mipi_dsi_cmd edo_rm67162_qvga_cmd_on_command[] = { |
| 112 | {0x8, edo_rm67162_qvga_cmd_on_cmd0, 0x00}, |
| 113 | {0x8, edo_rm67162_qvga_cmd_on_cmd1, 0x00}, |
| 114 | {0x8, edo_rm67162_qvga_cmd_on_cmd2, 0x00}, |
| 115 | {0x8, edo_rm67162_qvga_cmd_on_cmd3, 0x00}, |
| 116 | {0x8, edo_rm67162_qvga_cmd_on_cmd4, 0x00}, |
| 117 | {0x8, edo_rm67162_qvga_cmd_on_cmd5, 0x00}, |
| 118 | {0x8, edo_rm67162_qvga_cmd_on_cmd6, 0x00}, |
| 119 | {0x8, edo_rm67162_qvga_cmd_on_cmd7, 0x00}, |
| 120 | {0x8, edo_rm67162_qvga_cmd_on_cmd8, 0x78}, |
| 121 | {0x8, edo_rm67162_qvga_cmd_on_cmd9, 0x05} |
| 122 | }; |
| 123 | |
| 124 | #define EDO_RM67162_QVGA_CMD_ON_COMMAND 10 |
| 125 | |
| 126 | |
| 127 | static char edo_rm67162_qvga_cmdoff_cmd0[] = { |
| 128 | 0x51, 0x00, 0x05, 0x80 |
| 129 | }; |
| 130 | |
| 131 | static char edo_rm67162_qvga_cmdoff_cmd1[] = { |
| 132 | 0x28, 0x00, 0x05, 0x80 |
| 133 | }; |
| 134 | |
| 135 | static char edo_rm67162_qvga_cmdoff_cmd2[] = { |
| 136 | 0x10, 0x00, 0x05, 0x80 |
| 137 | }; |
| 138 | |
| 139 | static char edo_rm67162_qvga_cmdoff_cmd3[] = { |
| 140 | 0x4F, 0x01, 0x05, 0x80 |
| 141 | }; |
| 142 | |
| 143 | static struct mipi_dsi_cmd edo_rm67162_qvga_cmd_off_command[] = { |
| 144 | {0x4, edo_rm67162_qvga_cmdoff_cmd0, 0x05}, |
| 145 | {0x4, edo_rm67162_qvga_cmdoff_cmd1, 0x14}, |
| 146 | {0x4, edo_rm67162_qvga_cmdoff_cmd2, 0x78}, |
| 147 | {0x4, edo_rm67162_qvga_cmdoff_cmd3, 0x14} |
| 148 | }; |
| 149 | |
| 150 | #define EDO_RM67162_QVGA_CMD_OFF_COMMAND 4 |
| 151 | |
| 152 | |
| 153 | static struct command_state edo_rm67162_qvga_cmd_state = { |
| 154 | 0, 1 |
| 155 | }; |
| 156 | |
| 157 | /*---------------------------------------------------------------------------*/ |
| 158 | /* Command mode panel information */ |
| 159 | /*---------------------------------------------------------------------------*/ |
| 160 | static struct commandpanel_info edo_rm67162_qvga_cmd_command_panel = { |
| 161 | 1, 1, 1, 0, 0, 0x2c, 0, 0, 0, 1, 0, 0 |
| 162 | }; |
| 163 | |
| 164 | /*---------------------------------------------------------------------------*/ |
| 165 | /* Video mode panel information */ |
| 166 | /*---------------------------------------------------------------------------*/ |
| 167 | static struct videopanel_info edo_rm67162_qvga_cmd_video_panel = { |
| 168 | 1, 0, 0, 0, 1, 1, 2, 0, 0x9 |
| 169 | }; |
| 170 | |
| 171 | /*---------------------------------------------------------------------------*/ |
| 172 | /* Lane configuration */ |
| 173 | /*---------------------------------------------------------------------------*/ |
| 174 | static struct lane_configuration edo_rm67162_qvga_cmd_lane_config = { |
Xipeng Gu | dbec1bd | 2019-06-18 14:41:15 +0800 | [diff] [blame] | 175 | 1, 0, 1, 0, 0, 0, 0 |
Xipeng Gu | 8f53d60 | 2019-05-10 10:51:55 +0800 | [diff] [blame] | 176 | }; |
| 177 | |
| 178 | /*---------------------------------------------------------------------------*/ |
| 179 | /* Panel timing */ |
| 180 | /*---------------------------------------------------------------------------*/ |
| 181 | static const uint32_t edo_rm67162_qvga_cmd_12nm_timings[] = { |
| 182 | 0x06, 0x05, 0x01, 0x01, 0x00, 0x03, 0x01, 0x03 |
| 183 | }; |
| 184 | |
| 185 | static struct panel_timing edo_rm67162_qvga_cmd_timing_info = { |
Xipeng Gu | dbec1bd | 2019-06-18 14:41:15 +0800 | [diff] [blame] | 186 | 0, 4, 0x09, 0x2c |
Xipeng Gu | 8f53d60 | 2019-05-10 10:51:55 +0800 | [diff] [blame] | 187 | }; |
| 188 | |
| 189 | /*---------------------------------------------------------------------------*/ |
| 190 | /* Panel reset sequence */ |
| 191 | /*---------------------------------------------------------------------------*/ |
| 192 | static struct panel_reset_sequence edo_rm67162_qvga_cmd_reset_seq = { |
| 193 | {1, 0, 1, }, {1, 12, 12, }, 2 |
| 194 | }; |
| 195 | |
| 196 | /*---------------------------------------------------------------------------*/ |
| 197 | /* Backlight setting */ |
| 198 | /*---------------------------------------------------------------------------*/ |
| 199 | static struct backlight edo_rm67162_qvga_cmd_backlight = { |
Xipeng Gu | dbec1bd | 2019-06-18 14:41:15 +0800 | [diff] [blame] | 200 | 2, 1, 255, 100, 2, "BL_CTL_DCS" |
Xipeng Gu | 8f53d60 | 2019-05-10 10:51:55 +0800 | [diff] [blame] | 201 | }; |
| 202 | |
| 203 | #endif /*_PANEL_EDO_RM67162_QVGA_CMD_H_*/ |