Jayant Shekhar | 9919248 | 2016-01-14 11:24:41 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2012-2016, The Linux Foundation. All rights reserved. |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are met: |
| 5 | * * Redistributions of source code must retain the above copyright |
| 6 | * notice, this list of conditions and the following disclaimer. |
| 7 | * * Redistributions in binary form must reproduce the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer in the |
| 9 | * documentation and/or other materials provided with the distribution. |
| 10 | * * Neither the name of The Linux Foundation nor |
| 11 | * the names of its contributors may be used to endorse or promote |
| 12 | * products derived from this software without specific prior written |
| 13 | * permission. |
| 14 | * |
| 15 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 16 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 17 | * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 18 | * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 19 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 20 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 21 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; |
| 22 | * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 23 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR |
| 24 | * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF |
| 25 | * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 26 | */ |
| 27 | |
| 28 | #include <mdp5.h> |
| 29 | #include <debug.h> |
| 30 | #include <reg.h> |
| 31 | #include <target/display.h> |
| 32 | #include <platform/timer.h> |
| 33 | #include <platform/iomap.h> |
| 34 | #include <dev/lcdc.h> |
| 35 | #include <dev/fbcon.h> |
| 36 | #include <bits.h> |
| 37 | #include <msm_panel.h> |
| 38 | #include <mipi_dsi.h> |
| 39 | #include <err.h> |
| 40 | #include <clock.h> |
Siddhartha Agrawal | 8d69082 | 2013-01-28 12:18:58 -0800 | [diff] [blame] | 41 | #include <scm.h> |
Sandeep Panda | 6c24af7 | 2015-12-23 15:36:07 +0530 | [diff] [blame] | 42 | #include <arch/defines.h> |
Siddhartha Agrawal | 8d69082 | 2013-01-28 12:18:58 -0800 | [diff] [blame] | 43 | |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 44 | #define MDSS_MDP_MAX_PREFILL_FETCH 25 |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 45 | |
Siddhartha Agrawal | 8d69082 | 2013-01-28 12:18:58 -0800 | [diff] [blame] | 46 | int restore_secure_cfg(uint32_t id); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 47 | |
| 48 | static int mdp_rev; |
| 49 | |
| 50 | void mdp_set_revision(int rev) |
| 51 | { |
| 52 | mdp_rev = rev; |
| 53 | } |
| 54 | |
| 55 | int mdp_get_revision() |
| 56 | { |
| 57 | return mdp_rev; |
| 58 | } |
| 59 | |
Dhaval Patel | 4401467 | 2015-03-26 10:58:32 -0700 | [diff] [blame] | 60 | static inline bool is_software_pixel_ext_config_needed() |
| 61 | { |
Padmanabhan Komanduru | f1d58a3 | 2015-11-13 19:02:22 +0530 | [diff] [blame] | 62 | return (MDSS_IS_MAJOR_MINOR_MATCHING(readl(MDP_HW_REV), |
| 63 | MDSS_MDP_HW_REV_107) || MDSS_IS_MAJOR_MINOR_MATCHING(readl(MDP_HW_REV), |
Jayant Shekhar | 9919248 | 2016-01-14 11:24:41 +0530 | [diff] [blame] | 64 | MDSS_MDP_HW_REV_114) || MDSS_IS_MAJOR_MINOR_MATCHING(readl(MDP_HW_REV), |
Jayant Shekhar | 85a8272 | 2016-01-28 11:22:47 +0530 | [diff] [blame] | 65 | MDSS_MDP_HW_REV_116) || MDSS_IS_MAJOR_MINOR_MATCHING(readl(MDP_HW_REV), |
| 66 | MDSS_MDP_HW_REV_115)); |
Dhaval Patel | 4401467 | 2015-03-26 10:58:32 -0700 | [diff] [blame] | 67 | } |
| 68 | |
| 69 | static inline bool has_fixed_size_smp() |
| 70 | { |
Padmanabhan Komanduru | f1d58a3 | 2015-11-13 19:02:22 +0530 | [diff] [blame] | 71 | return (MDSS_IS_MAJOR_MINOR_MATCHING(readl(MDP_HW_REV), |
| 72 | MDSS_MDP_HW_REV_107) || MDSS_IS_MAJOR_MINOR_MATCHING(readl(MDP_HW_REV), |
Jayant Shekhar | 9919248 | 2016-01-14 11:24:41 +0530 | [diff] [blame] | 73 | MDSS_MDP_HW_REV_114) || MDSS_IS_MAJOR_MINOR_MATCHING(readl(MDP_HW_REV), |
Jayant Shekhar | 85a8272 | 2016-01-28 11:22:47 +0530 | [diff] [blame] | 74 | MDSS_MDP_HW_REV_116) || MDSS_IS_MAJOR_MINOR_MATCHING(readl(MDP_HW_REV), |
| 75 | MDSS_MDP_HW_REV_115)); |
Dhaval Patel | 4401467 | 2015-03-26 10:58:32 -0700 | [diff] [blame] | 76 | } |
| 77 | |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 78 | uint32_t mdss_mdp_intf_offset() |
| 79 | { |
| 80 | uint32_t mdss_mdp_intf_off; |
| 81 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 82 | |
Padmanabhan Komanduru | 3908d17 | 2014-06-04 18:00:56 +0530 | [diff] [blame] | 83 | if ((mdss_mdp_rev == MDSS_MDP_HW_REV_106) || |
Padmanabhan Komanduru | fdb5683 | 2015-04-09 21:08:28 -0700 | [diff] [blame] | 84 | (mdss_mdp_rev == MDSS_MDP_HW_REV_108) || |
Padmanabhan Komanduru | f912cfb | 2015-06-08 16:36:58 +0530 | [diff] [blame] | 85 | (mdss_mdp_rev == MDSS_MDP_HW_REV_111) || |
Padmanabhan Komanduru | f1d58a3 | 2015-11-13 19:02:22 +0530 | [diff] [blame] | 86 | (mdss_mdp_rev == MDSS_MDP_HW_REV_112) || |
Jayant Shekhar | 9919248 | 2016-01-14 11:24:41 +0530 | [diff] [blame] | 87 | (mdss_mdp_rev == MDSS_MDP_HW_REV_114) || |
Jayant Shekhar | 85a8272 | 2016-01-28 11:22:47 +0530 | [diff] [blame] | 88 | (mdss_mdp_rev == MDSS_MDP_HW_REV_116) || |
| 89 | (mdss_mdp_rev == MDSS_MDP_HW_REV_115)) |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 90 | mdss_mdp_intf_off = 0x59100; |
| 91 | else if (mdss_mdp_rev >= MDSS_MDP_HW_REV_102) |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 92 | mdss_mdp_intf_off = 0; |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 93 | else |
Chandan Uddaraju | aab5851 | 2013-06-25 17:47:39 -0700 | [diff] [blame] | 94 | mdss_mdp_intf_off = 0xEC00; |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 95 | |
| 96 | return mdss_mdp_intf_off; |
| 97 | } |
| 98 | |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 99 | static uint32_t mdss_mdp_get_ppb_offset() |
| 100 | { |
| 101 | uint32_t mdss_mdp_ppb_off = 0; |
| 102 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 103 | |
| 104 | /* return MMSS_MDP_PPB0_CONFIG offset from MDSS base */ |
Padmanabhan Komanduru | f912cfb | 2015-06-08 16:36:58 +0530 | [diff] [blame] | 105 | if ((mdss_mdp_rev == MDSS_MDP_HW_REV_108) || |
Ujwal Patel | 5c3227b | 2015-08-12 14:48:02 -0700 | [diff] [blame] | 106 | (mdss_mdp_rev == MDSS_MDP_HW_REV_111)) |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 107 | mdss_mdp_ppb_off = 0x1420; |
| 108 | else if (mdss_mdp_rev == MDSS_MDP_HW_REV_110) |
| 109 | mdss_mdp_ppb_off = 0x1334; |
Ujwal Patel | 5c3227b | 2015-08-12 14:48:02 -0700 | [diff] [blame] | 110 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_107)) |
| 111 | mdss_mdp_ppb_off = 0x1330; |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 112 | else |
| 113 | dprintf(CRITICAL,"Invalid PPB0_CONFIG offset\n"); |
| 114 | |
| 115 | return mdss_mdp_ppb_off; |
| 116 | } |
| 117 | |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 118 | static uint32_t mdss_mdp_vbif_qos_remap_get_offset() |
| 119 | { |
| 120 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 121 | |
Padmanabhan Komanduru | f912cfb | 2015-06-08 16:36:58 +0530 | [diff] [blame] | 122 | if ((mdss_mdp_rev == MDSS_MDP_HW_REV_110) || |
Padmanabhan Komanduru | f1d58a3 | 2015-11-13 19:02:22 +0530 | [diff] [blame] | 123 | (mdss_mdp_rev == MDSS_MDP_HW_REV_111) || |
Jayant Shekhar | 9919248 | 2016-01-14 11:24:41 +0530 | [diff] [blame] | 124 | (mdss_mdp_rev == MDSS_MDP_HW_REV_114) || |
Jayant Shekhar | 85a8272 | 2016-01-28 11:22:47 +0530 | [diff] [blame] | 125 | (mdss_mdp_rev == MDSS_MDP_HW_REV_115) || |
Jayant Shekhar | 9919248 | 2016-01-14 11:24:41 +0530 | [diff] [blame] | 126 | (mdss_mdp_rev == MDSS_MDP_HW_REV_116)) |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 127 | return 0xB0020; |
Dhaval Patel | 225cde1 | 2015-05-04 11:14:12 -0700 | [diff] [blame] | 128 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_107)) |
| 129 | return 0xB0000; |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 130 | else |
| 131 | return 0xC8020; |
| 132 | } |
| 133 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 134 | void mdp_clk_gating_ctrl(void) |
| 135 | { |
Dhaval Patel | 225cde1 | 2015-05-04 11:14:12 -0700 | [diff] [blame] | 136 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 137 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_107)) |
| 138 | return; |
| 139 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 140 | writel(0x40000000, MDP_CLK_CTRL0); |
| 141 | udelay(20); |
| 142 | writel(0x40000040, MDP_CLK_CTRL0); |
| 143 | writel(0x40000000, MDP_CLK_CTRL1); |
| 144 | writel(0x00400000, MDP_CLK_CTRL3); |
| 145 | udelay(20); |
| 146 | writel(0x00404000, MDP_CLK_CTRL3); |
| 147 | writel(0x40000000, MDP_CLK_CTRL4); |
| 148 | } |
| 149 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 150 | static void mdp_select_pipe_type(struct msm_panel_info *pinfo, |
| 151 | uint32_t *left_pipe, uint32_t *right_pipe) |
| 152 | { |
| 153 | switch (pinfo->pipe_type) { |
| 154 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 155 | *left_pipe = MDP_VP_0_RGB_0_BASE; |
| 156 | *right_pipe = MDP_VP_0_RGB_1_BASE; |
| 157 | break; |
| 158 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 159 | *left_pipe = MDP_VP_0_DMA_0_BASE; |
| 160 | *right_pipe = MDP_VP_0_DMA_1_BASE; |
| 161 | break; |
| 162 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 163 | default: |
| 164 | *left_pipe = MDP_VP_0_VIG_0_BASE; |
| 165 | *right_pipe = MDP_VP_0_VIG_1_BASE; |
| 166 | break; |
| 167 | } |
| 168 | } |
| 169 | |
| 170 | static void mdss_mdp_set_flush(struct msm_panel_info *pinfo, |
| 171 | uint32_t *ctl0_reg_val, uint32_t *ctl1_reg_val) |
| 172 | { |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 173 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 174 | bool dual_pipe_single_ctl = pinfo->lcdc.dual_pipe && |
| 175 | !pinfo->mipi.dual_dsi && !pinfo->lcdc.split_display; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 176 | switch (pinfo->pipe_type) { |
| 177 | case MDSS_MDP_PIPE_TYPE_RGB: |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 178 | if (dual_pipe_single_ctl) |
| 179 | *ctl0_reg_val = 0x220D8; |
| 180 | else |
| 181 | *ctl0_reg_val = 0x22048; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 182 | *ctl1_reg_val = 0x24090; |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 183 | |
| 184 | if (pinfo->lcdc.dst_split) |
| 185 | *ctl0_reg_val |= BIT(4); |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 186 | break; |
| 187 | case MDSS_MDP_PIPE_TYPE_DMA: |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 188 | if (dual_pipe_single_ctl) |
| 189 | *ctl0_reg_val = 0x238C0; |
| 190 | else |
| 191 | *ctl0_reg_val = 0x22840; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 192 | *ctl1_reg_val = 0x25080; |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 193 | if (pinfo->lcdc.dst_split) |
| 194 | *ctl0_reg_val |= BIT(12); |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 195 | break; |
| 196 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 197 | default: |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 198 | if (dual_pipe_single_ctl) |
| 199 | *ctl0_reg_val = 0x220C3; |
| 200 | else |
| 201 | *ctl0_reg_val = 0x22041; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 202 | *ctl1_reg_val = 0x24082; |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 203 | if (pinfo->lcdc.dst_split) |
| 204 | *ctl0_reg_val |= BIT(1); |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 205 | break; |
| 206 | } |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 207 | /* For targets from MDP v1.5, MDP INTF registers are double buffered */ |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 208 | if ((mdss_mdp_rev == MDSS_MDP_HW_REV_106) || |
Padmanabhan Komanduru | fdb5683 | 2015-04-09 21:08:28 -0700 | [diff] [blame] | 209 | (mdss_mdp_rev == MDSS_MDP_HW_REV_108) || |
Padmanabhan Komanduru | f912cfb | 2015-06-08 16:36:58 +0530 | [diff] [blame] | 210 | (mdss_mdp_rev == MDSS_MDP_HW_REV_111) || |
Padmanabhan Komanduru | fdb5683 | 2015-04-09 21:08:28 -0700 | [diff] [blame] | 211 | (mdss_mdp_rev == MDSS_MDP_HW_REV_112)) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 212 | if (pinfo->dest == DISPLAY_2) { |
| 213 | *ctl0_reg_val |= BIT(31); |
| 214 | *ctl1_reg_val |= BIT(30); |
| 215 | } else { |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 216 | *ctl0_reg_val |= BIT(30); |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 217 | *ctl1_reg_val |= BIT(31); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 218 | } |
Chandan Uddaraju | 18a5037 | 2014-10-01 18:45:30 -0700 | [diff] [blame] | 219 | } else if ((mdss_mdp_rev == MDSS_MDP_HW_REV_105) || |
Jeevan Shriram | 47c936d | 2014-12-19 11:50:13 -0800 | [diff] [blame] | 220 | (mdss_mdp_rev == MDSS_MDP_HW_REV_109) || |
Dhaval Patel | 4401467 | 2015-03-26 10:58:32 -0700 | [diff] [blame] | 221 | MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, |
| 222 | MDSS_MDP_HW_REV_107) || |
Padmanabhan Komanduru | f1d58a3 | 2015-11-13 19:02:22 +0530 | [diff] [blame] | 223 | (mdss_mdp_rev == MDSS_MDP_HW_REV_114) || |
Jayant Shekhar | 9919248 | 2016-01-14 11:24:41 +0530 | [diff] [blame] | 224 | (mdss_mdp_rev == MDSS_MDP_HW_REV_116) || |
Jayant Shekhar | 85a8272 | 2016-01-28 11:22:47 +0530 | [diff] [blame] | 225 | (mdss_mdp_rev == MDSS_MDP_HW_REV_115) || |
Jeevan Shriram | 47c936d | 2014-12-19 11:50:13 -0800 | [diff] [blame] | 226 | (mdss_mdp_rev == MDSS_MDP_HW_REV_110)) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 227 | if (pinfo->dest == DISPLAY_2) { |
| 228 | *ctl0_reg_val |= BIT(29); |
| 229 | *ctl1_reg_val |= BIT(30); |
| 230 | } else { |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 231 | *ctl0_reg_val |= BIT(30); |
| 232 | *ctl1_reg_val |= BIT(29); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 233 | } |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 234 | } |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 235 | } |
| 236 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 237 | static void mdss_source_pipe_config(struct fbcon_config *fb, struct msm_panel_info |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 238 | *pinfo, uint32_t pipe_base) |
| 239 | { |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 240 | uint32_t img_size, out_size, stride; |
Siddhartha Agrawal | 6ef1e22 | 2013-06-12 18:24:58 -0700 | [diff] [blame] | 241 | uint32_t fb_off = 0; |
Prashant Nukala | 64eeff9 | 2014-07-11 07:35:34 +0530 | [diff] [blame] | 242 | uint32_t flip_bits = 0; |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 243 | uint32_t src_xy = 0, dst_xy = 0; |
| 244 | uint32_t height, width; |
| 245 | |
| 246 | height = fb->height - pinfo->border_top - pinfo->border_bottom; |
| 247 | width = fb->width - pinfo->border_left - pinfo->border_right; |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 248 | |
| 249 | /* write active region size*/ |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 250 | img_size = (height << 16) | width; |
| 251 | out_size = img_size; |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 252 | if (pinfo->lcdc.dual_pipe) { |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 253 | if ((pipe_base == MDP_VP_0_RGB_1_BASE) || |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 254 | (pipe_base == MDP_VP_0_DMA_1_BASE) || |
| 255 | (pipe_base == MDP_VP_0_VIG_1_BASE)) { |
Siddhartha Agrawal | 6ef1e22 | 2013-06-12 18:24:58 -0700 | [diff] [blame] | 256 | fb_off = (pinfo->xres / 2); |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 257 | out_size = (height << 16) + (pinfo->lm_split[1]); |
| 258 | } else { |
| 259 | out_size = (height << 16) + (pinfo->lm_split[0]); |
| 260 | } |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 261 | } |
| 262 | |
| 263 | stride = (fb->stride * fb->bpp/8); |
| 264 | |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 265 | if (fb_off == 0) { /* left */ |
| 266 | dst_xy = (pinfo->border_top << 16) | pinfo->border_left; |
| 267 | src_xy = dst_xy; |
| 268 | } else { /* right */ |
| 269 | dst_xy = (pinfo->border_top << 16); |
| 270 | src_xy = (pinfo->border_top << 16) | fb_off; |
| 271 | } |
| 272 | |
| 273 | dprintf(SPEW,"%s: src=%x fb_off=%x src_xy=%x dst_xy=%x\n", |
| 274 | __func__, out_size, fb_off, src_xy, dst_xy); |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 275 | writel((uint32_t) fb->base, pipe_base + PIPE_SSPP_SRC0_ADDR); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 276 | writel(stride, pipe_base + PIPE_SSPP_SRC_YSTRIDE); |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 277 | writel(img_size, pipe_base + PIPE_SSPP_SRC_IMG_SIZE); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 278 | writel(out_size, pipe_base + PIPE_SSPP_SRC_SIZE); |
| 279 | writel(out_size, pipe_base + PIPE_SSPP_SRC_OUT_SIZE); |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 280 | writel(src_xy, pipe_base + PIPE_SSPP_SRC_XY); |
| 281 | writel(dst_xy, pipe_base + PIPE_SSPP_OUT_XY); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 282 | |
| 283 | /* Tight Packing 3bpp 0-Alpha 8-bit R B G */ |
| 284 | writel(0x0002243F, pipe_base + PIPE_SSPP_SRC_FORMAT); |
| 285 | writel(0x00020001, pipe_base + PIPE_SSPP_SRC_UNPACK_PATTERN); |
Prashant Nukala | 64eeff9 | 2014-07-11 07:35:34 +0530 | [diff] [blame] | 286 | |
| 287 | /* bit(0) is set if hflip is required. |
| 288 | * bit(1) is set if vflip is required. |
| 289 | */ |
| 290 | if (pinfo->orientation & 0x1) |
| 291 | flip_bits |= MDSS_MDP_OP_MODE_FLIP_LR; |
| 292 | if (pinfo->orientation & 0x2) |
| 293 | flip_bits |= MDSS_MDP_OP_MODE_FLIP_UD; |
Dhaval Patel | 4401467 | 2015-03-26 10:58:32 -0700 | [diff] [blame] | 294 | |
| 295 | if (is_software_pixel_ext_config_needed()) { |
| 296 | flip_bits |= BIT(31); |
| 297 | writel(out_size, pipe_base + PIPE_SW_PIXEL_EXT_C0_REQ); |
| 298 | writel(out_size, pipe_base + PIPE_SW_PIXEL_EXT_C1C2_REQ); |
| 299 | writel(out_size, pipe_base + PIPE_SW_PIXEL_EXT_C3_REQ); |
| 300 | /* configure phase step 1 for all color components */ |
| 301 | writel(0x200000, pipe_base + PIPE_COMP0_3_PHASE_STEP_X); |
| 302 | writel(0x200000, pipe_base + PIPE_COMP0_3_PHASE_STEP_Y); |
| 303 | writel(0x200000, pipe_base + PIPE_COMP1_2_PHASE_STEP_X); |
| 304 | writel(0x200000, pipe_base + PIPE_COMP1_2_PHASE_STEP_Y); |
| 305 | } |
Prashant Nukala | 64eeff9 | 2014-07-11 07:35:34 +0530 | [diff] [blame] | 306 | writel(flip_bits, pipe_base + PIPE_SSPP_SRC_OP_MODE); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 307 | } |
| 308 | |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 309 | static void mdss_vbif_setup() |
| 310 | { |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 311 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
Dhaval Patel | 225cde1 | 2015-05-04 11:14:12 -0700 | [diff] [blame] | 312 | int access_secure = false; |
| 313 | if (!MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_107)) |
| 314 | access_secure = restore_secure_cfg(SECURE_DEVICE_MDSS); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 315 | |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 316 | if (!access_secure) { |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 317 | dprintf(SPEW, "MDSS VBIF registers unlocked by TZ.\n"); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 318 | |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 319 | /* Force VBIF Clocks on, needed for 8974 and 8x26 */ |
| 320 | if (mdp_hw_rev < MDSS_MDP_HW_REV_103) |
Ujwal Patel | 00e1985 | 2013-12-18 20:40:38 -0800 | [diff] [blame] | 321 | writel(0x1, VBIF_VBIF_DDR_FORCE_CLK_ON); |
| 322 | |
| 323 | /* |
| 324 | * Following configuration is needed because on some versions, |
| 325 | * recommended reset values are not stored. |
| 326 | */ |
| 327 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 328 | MDSS_MDP_HW_REV_100)) { |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 329 | writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST); |
| 330 | writel(0x00000030, VBIF_VBIF_DDR_ARB_CTRL ); |
| 331 | writel(0x00000001, VBIF_VBIF_DDR_RND_RBN_QOS_ARB); |
| 332 | writel(0x00000FFF, VBIF_VBIF_DDR_OUT_AOOO_AXI_EN); |
| 333 | writel(0x0FFF0FFF, VBIF_VBIF_DDR_OUT_AX_AOOO); |
| 334 | writel(0x22222222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0); |
| 335 | writel(0x00002222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1); |
Ujwal Patel | 00e1985 | 2013-12-18 20:40:38 -0800 | [diff] [blame] | 336 | } else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 337 | MDSS_MDP_HW_REV_101)) { |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 338 | writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST); |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 339 | writel(0x00000003, VBIF_VBIF_DDR_RND_RBN_QOS_ARB); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 340 | } |
| 341 | } |
| 342 | } |
| 343 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 344 | static uint32_t mdss_smp_alloc(uint32_t client_id, uint32_t smp_cnt, |
| 345 | uint32_t fixed_smp_cnt, uint32_t free_smp_offset) |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 346 | { |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 347 | uint32_t i, j; |
| 348 | uint32_t reg_val = 0; |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 349 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 350 | for (i = fixed_smp_cnt, j = 0; i < smp_cnt; i++) { |
| 351 | /* max 3 MMB per register */ |
| 352 | reg_val |= client_id << (((j++) % 3) * 8); |
| 353 | if ((j % 3) == 0) { |
| 354 | writel(reg_val, MMSS_MDP_SMP_ALLOC_W_BASE + |
| 355 | free_smp_offset); |
| 356 | writel(reg_val, MMSS_MDP_SMP_ALLOC_R_BASE + |
| 357 | free_smp_offset); |
| 358 | reg_val = 0; |
| 359 | free_smp_offset += 4; |
| 360 | } |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 361 | } |
| 362 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 363 | if (j % 3) { |
| 364 | writel(reg_val, MMSS_MDP_SMP_ALLOC_W_BASE + free_smp_offset); |
| 365 | writel(reg_val, MMSS_MDP_SMP_ALLOC_R_BASE + free_smp_offset); |
| 366 | free_smp_offset += 4; |
| 367 | } |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 368 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 369 | return free_smp_offset; |
| 370 | } |
| 371 | |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 372 | static void mdp_select_pipe_client_id(struct msm_panel_info *pinfo, |
| 373 | uint32_t *left_sspp_client_id, uint32_t *right_sspp_client_id) |
| 374 | { |
| 375 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 376 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_101) || |
| 377 | MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_106) || |
Padmanabhan Komanduru | fdb5683 | 2015-04-09 21:08:28 -0700 | [diff] [blame] | 378 | MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_108) || |
Padmanabhan Komanduru | f912cfb | 2015-06-08 16:36:58 +0530 | [diff] [blame] | 379 | MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_111) || |
Padmanabhan Komanduru | fdb5683 | 2015-04-09 21:08:28 -0700 | [diff] [blame] | 380 | MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_112)) { |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 381 | switch (pinfo->pipe_type) { |
| 382 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 383 | *left_sspp_client_id = 0x7; /* 7 */ |
Padmanabhan Komanduru | f912cfb | 2015-06-08 16:36:58 +0530 | [diff] [blame] | 384 | *right_sspp_client_id = 0x8; /* 8 */ |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 385 | break; |
| 386 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 387 | *left_sspp_client_id = 0x4; /* 4 */ |
| 388 | *right_sspp_client_id = 0xD; /* 13 */ |
| 389 | break; |
| 390 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 391 | default: |
| 392 | *left_sspp_client_id = 0x1; /* 1 */ |
Padmanabhan Komanduru | f912cfb | 2015-06-08 16:36:58 +0530 | [diff] [blame] | 393 | *right_sspp_client_id = 0x9; /* 9 */ |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 394 | break; |
| 395 | } |
| 396 | } else { |
| 397 | switch (pinfo->pipe_type) { |
| 398 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 399 | *left_sspp_client_id = 0x10; /* 16 */ |
| 400 | *right_sspp_client_id = 0x11; /* 17 */ |
| 401 | break; |
| 402 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 403 | *left_sspp_client_id = 0xA; /* 10 */ |
| 404 | *right_sspp_client_id = 0xD; /* 13 */ |
| 405 | break; |
| 406 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 407 | default: |
| 408 | *left_sspp_client_id = 0x1; /* 1 */ |
| 409 | *right_sspp_client_id = 0x4; /* 4 */ |
| 410 | break; |
| 411 | } |
| 412 | } |
| 413 | } |
| 414 | |
| 415 | static void mdp_select_pipe_xin_id(struct msm_panel_info *pinfo, |
| 416 | uint32_t *left_pipe_xin_id, uint32_t *right_pipe_xin_id) |
| 417 | { |
| 418 | switch (pinfo->pipe_type) { |
| 419 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 420 | *left_pipe_xin_id = 0x1; /* 1 */ |
| 421 | *right_pipe_xin_id = 0x5; /* 5 */ |
| 422 | break; |
| 423 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 424 | *left_pipe_xin_id = 0x2; /* 2 */ |
| 425 | *right_pipe_xin_id = 0xA; /* 10 */ |
| 426 | break; |
| 427 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 428 | default: |
| 429 | *left_pipe_xin_id = 0x0; /* 0 */ |
| 430 | *right_pipe_xin_id = 0x4; /* 4 */ |
| 431 | break; |
| 432 | } |
| 433 | } |
| 434 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 435 | static void mdss_smp_setup(struct msm_panel_info *pinfo, uint32_t left_pipe, |
| 436 | uint32_t right_pipe) |
| 437 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 438 | { |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 439 | uint32_t left_sspp_client_id, right_sspp_client_id; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 440 | uint32_t bpp = 3, free_smp_offset = 0, xres = MDSS_MAX_LINE_BUF_WIDTH; |
| 441 | uint32_t smp_cnt, smp_size = 4096, fixed_smp_cnt = 0; |
| 442 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 443 | |
Padmanabhan Komanduru | fdb5683 | 2015-04-09 21:08:28 -0700 | [diff] [blame] | 444 | if ((mdss_mdp_rev == MDSS_MDP_HW_REV_106) || |
| 445 | (mdss_mdp_rev == MDSS_MDP_HW_REV_112)) { |
| 446 | /* 8Kb per SMP on 8916/8952 */ |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 447 | smp_size = 8192; |
Padmanabhan Komanduru | f912cfb | 2015-06-08 16:36:58 +0530 | [diff] [blame] | 448 | } else if ((mdss_mdp_rev == MDSS_MDP_HW_REV_108) || |
| 449 | (mdss_mdp_rev == MDSS_MDP_HW_REV_111)) { |
| 450 | /* 10Kb per SMP on 8939/8956 */ |
Padmanabhan Komanduru | 3908d17 | 2014-06-04 18:00:56 +0530 | [diff] [blame] | 451 | smp_size = 10240; |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 452 | } else if ((mdss_mdp_rev >= MDSS_MDP_HW_REV_103) && |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 453 | (mdss_mdp_rev < MDSS_MDP_HW_REV_200)) { |
| 454 | smp_size = 8192; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 455 | free_smp_offset = 0xC; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 456 | if (pinfo->pipe_type == MDSS_MDP_PIPE_TYPE_RGB) |
| 457 | fixed_smp_cnt = 2; |
| 458 | else |
| 459 | fixed_smp_cnt = 0; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 460 | } |
| 461 | |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 462 | mdp_select_pipe_client_id(pinfo, |
| 463 | &left_sspp_client_id, &right_sspp_client_id); |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 464 | |
| 465 | /* Each pipe driving half the screen */ |
| 466 | if (pinfo->lcdc.dual_pipe) |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 467 | xres = pinfo->lm_split[0]; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 468 | |
| 469 | /* bpp = bytes per pixel of input image */ |
| 470 | smp_cnt = (xres * bpp * 2) + smp_size - 1; |
| 471 | smp_cnt /= smp_size; |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 472 | |
| 473 | if (smp_cnt > 4) { |
| 474 | dprintf(CRITICAL, "ERROR: %s: Out of SMP's, cnt=%d! \n", __func__, |
| 475 | smp_cnt); |
| 476 | ASSERT(0); /* Max 4 SMPs can be allocated per client */ |
| 477 | } |
| 478 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 479 | writel(smp_cnt * 0x40, left_pipe + REQPRIORITY_FIFO_WATERMARK0); |
| 480 | writel(smp_cnt * 0x80, left_pipe + REQPRIORITY_FIFO_WATERMARK1); |
| 481 | writel(smp_cnt * 0xc0, left_pipe + REQPRIORITY_FIFO_WATERMARK2); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 482 | |
| 483 | if (pinfo->lcdc.dual_pipe) { |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 484 | xres = pinfo->lm_split[1]; |
| 485 | |
| 486 | smp_cnt = (xres * bpp * 2) + smp_size - 1; |
| 487 | smp_cnt /= smp_size; |
| 488 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 489 | writel(smp_cnt * 0x40, right_pipe + REQPRIORITY_FIFO_WATERMARK0); |
| 490 | writel(smp_cnt * 0x80, right_pipe + REQPRIORITY_FIFO_WATERMARK1); |
| 491 | writel(smp_cnt * 0xc0, right_pipe + REQPRIORITY_FIFO_WATERMARK2); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 492 | } |
| 493 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 494 | free_smp_offset = mdss_smp_alloc(left_sspp_client_id, smp_cnt, |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 495 | fixed_smp_cnt, free_smp_offset); |
| 496 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 497 | mdss_smp_alloc(right_sspp_client_id, smp_cnt, fixed_smp_cnt, |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 498 | free_smp_offset); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 499 | } |
| 500 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 501 | static void mdss_intf_tg_setup(struct msm_panel_info *pinfo, uint32_t intf_base) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 502 | { |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 503 | uint32_t hsync_period, vsync_period; |
| 504 | uint32_t hsync_start_x, hsync_end_x; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 505 | uint32_t display_hctl, hsync_ctl, display_vstart, display_vend; |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 506 | uint32_t adjust_xres = 0; |
Dhaval Patel | 55c1217 | 2015-05-04 22:25:22 -0700 | [diff] [blame] | 507 | uint32_t upper = 0, lower = 0; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 508 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 509 | struct lcdc_panel_info *lcdc = NULL; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 510 | struct intf_timing_params itp = {0}; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 511 | |
| 512 | if (pinfo == NULL) |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 513 | return; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 514 | |
| 515 | lcdc = &(pinfo->lcdc); |
| 516 | if (lcdc == NULL) |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 517 | return; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 518 | |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 519 | adjust_xres = pinfo->xres; |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 520 | if (pinfo->lcdc.split_display) { |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 521 | if (pinfo->lcdc.dst_split) { |
| 522 | adjust_xres /= 2; |
| 523 | } else if(pinfo->lcdc.dual_pipe) { |
| 524 | if (intf_base == (MDP_INTF_1_BASE + mdss_mdp_intf_offset())) |
| 525 | adjust_xres = pinfo->lm_split[0]; |
| 526 | else |
| 527 | adjust_xres = pinfo->lm_split[1]; |
| 528 | } |
| 529 | |
Jayant Shekhar | 4e895d0 | 2015-03-30 12:30:14 +0530 | [diff] [blame] | 530 | if (intf_base == (MDP_INTF_1_BASE + mdss_mdp_intf_offset())) { |
Dhaval Patel | 55c1217 | 2015-05-04 22:25:22 -0700 | [diff] [blame] | 531 | if (pinfo->lcdc.pipe_swap) { |
| 532 | lower |= BIT(4); |
| 533 | upper |= BIT(8); |
| 534 | } else { |
| 535 | lower |= BIT(8); |
| 536 | upper |= BIT(4); |
| 537 | } |
| 538 | writel(lower, MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL); |
| 539 | writel(upper, MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 540 | writel(0x1, MDP_REG_SPLIT_DISPLAY_EN); |
| 541 | } |
| 542 | } |
| 543 | |
Ujwal Patel | 5c3227b | 2015-08-12 14:48:02 -0700 | [diff] [blame] | 544 | if (pinfo->lcdc.dst_split && (intf_base == (MDP_INTF_1_BASE + mdss_mdp_intf_offset()))) { |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 545 | uint32_t ppb_offset = mdss_mdp_get_ppb_offset(); |
Ujwal Patel | 5c3227b | 2015-08-12 14:48:02 -0700 | [diff] [blame] | 546 | writel(BIT(5), REG_MDP(ppb_offset)); /* MMSS_MDP_PPB0_CNTL */ |
| 547 | writel(BIT(16) | (0x3 << 20), REG_MDP(ppb_offset + 0x4)); /* MMSS_MDP_PPB0_CONFIG */ |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 548 | } |
| 549 | |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 550 | if (pinfo->compression_mode == COMPRESSION_FBC) |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 551 | if (!pinfo->fbc.enabled || !pinfo->fbc.comp_ratio) |
| 552 | pinfo->fbc.comp_ratio = 1; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 553 | |
| 554 | itp.xres = (adjust_xres / pinfo->fbc.comp_ratio); |
| 555 | itp.yres = pinfo->yres; |
| 556 | itp.width =((adjust_xres + pinfo->lcdc.xres_pad) / pinfo->fbc.comp_ratio); |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 557 | |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 558 | if (pinfo->compression_mode == COMPRESSION_DSC) { |
| 559 | itp.xres = pinfo->dsc.pclk_per_line; |
| 560 | itp.width = pinfo->dsc.pclk_per_line; |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 561 | } |
| 562 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 563 | itp.height = pinfo->yres + pinfo->lcdc.yres_pad; |
| 564 | itp.h_back_porch = pinfo->lcdc.h_back_porch; |
| 565 | itp.h_front_porch = pinfo->lcdc.h_front_porch; |
| 566 | itp.v_back_porch = pinfo->lcdc.v_back_porch; |
| 567 | itp.v_front_porch = pinfo->lcdc.v_front_porch; |
| 568 | itp.hsync_pulse_width = pinfo->lcdc.h_pulse_width; |
| 569 | itp.vsync_pulse_width = pinfo->lcdc.v_pulse_width; |
| 570 | |
| 571 | itp.border_clr = pinfo->lcdc.border_clr; |
| 572 | itp.underflow_clr = pinfo->lcdc.underflow_clr; |
| 573 | itp.hsync_skew = pinfo->lcdc.hsync_skew; |
| 574 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 575 | hsync_period = itp.hsync_pulse_width + itp.h_back_porch + |
| 576 | itp.width + itp.h_front_porch; |
| 577 | |
| 578 | vsync_period = itp.vsync_pulse_width + itp.v_back_porch + |
| 579 | itp.height + itp.v_front_porch; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 580 | |
| 581 | hsync_start_x = |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 582 | itp.hsync_pulse_width + |
| 583 | itp.h_back_porch; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 584 | hsync_end_x = |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 585 | hsync_period - itp.h_front_porch - 1; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 586 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 587 | display_vstart = (itp.vsync_pulse_width + |
| 588 | itp.v_back_porch) |
| 589 | * hsync_period + itp.hsync_skew; |
| 590 | display_vend = ((vsync_period - itp.v_front_porch) * hsync_period) |
| 591 | + itp.hsync_skew - 1; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 592 | |
Jayant Shekhar | 4e895d0 | 2015-03-30 12:30:14 +0530 | [diff] [blame] | 593 | if (intf_base == (MDP_INTF_0_BASE + mdss_mdp_intf_offset())) { /* eDP */ |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 594 | display_vstart += itp.hsync_pulse_width + itp.h_back_porch; |
| 595 | display_vend -= itp.h_front_porch; |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 596 | } |
| 597 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 598 | hsync_ctl = (hsync_period << 16) | itp.hsync_pulse_width; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 599 | display_hctl = (hsync_end_x << 16) | hsync_start_x; |
| 600 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 601 | writel(hsync_ctl, MDP_HSYNC_CTL + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 602 | writel(vsync_period*hsync_period, MDP_VSYNC_PERIOD_F0 + |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 603 | intf_base); |
| 604 | writel(0x00, MDP_VSYNC_PERIOD_F1 + intf_base); |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 605 | writel(itp.vsync_pulse_width*hsync_period, |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 606 | MDP_VSYNC_PULSE_WIDTH_F0 + |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 607 | intf_base); |
| 608 | writel(0x00, MDP_VSYNC_PULSE_WIDTH_F1 + intf_base); |
| 609 | writel(display_hctl, MDP_DISPLAY_HCTL + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 610 | writel(display_vstart, MDP_DISPLAY_V_START_F0 + |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 611 | intf_base); |
| 612 | writel(0x00, MDP_DISPLAY_V_START_F1 + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 613 | writel(display_vend, MDP_DISPLAY_V_END_F0 + |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 614 | intf_base); |
| 615 | writel(0x00, MDP_DISPLAY_V_END_F1 + intf_base); |
| 616 | writel(0x00, MDP_ACTIVE_HCTL + intf_base); |
| 617 | writel(0x00, MDP_ACTIVE_V_START_F0 + intf_base); |
| 618 | writel(0x00, MDP_ACTIVE_V_START_F1 + intf_base); |
| 619 | writel(0x00, MDP_ACTIVE_V_END_F0 + intf_base); |
| 620 | writel(0x00, MDP_ACTIVE_V_END_F1 + intf_base); |
| 621 | writel(0xFF, MDP_UNDERFFLOW_COLOR + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 622 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 623 | if (intf_base == (MDP_INTF_0_BASE + mdss_mdp_intf_offset())) /* eDP */ |
| 624 | writel(0x212A, MDP_PANEL_FORMAT + intf_base); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 625 | else |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 626 | writel(0x213F, MDP_PANEL_FORMAT + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 627 | } |
| 628 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 629 | static void mdss_intf_fetch_start_config(struct msm_panel_info *pinfo, |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 630 | uint32_t intf_base) |
| 631 | { |
| 632 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 633 | uint32_t v_total, h_total, fetch_start, vfp_start; |
| 634 | uint32_t prefetch_avail, prefetch_needed; |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 635 | uint32_t adjust_xres = 0; |
Huaibin Yang | 617cbb0 | 2015-01-14 14:17:07 -0800 | [diff] [blame] | 636 | uint32_t fetch_enable = BIT(31); |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 637 | |
| 638 | struct lcdc_panel_info *lcdc = NULL; |
| 639 | |
| 640 | if (pinfo == NULL) |
| 641 | return; |
| 642 | |
| 643 | lcdc = &(pinfo->lcdc); |
| 644 | if (lcdc == NULL) |
| 645 | return; |
| 646 | |
| 647 | /* |
| 648 | * MDP programmable fetch is for MDP with rev >= 1.05. |
| 649 | * Programmable fetch is not needed if vertical back porch |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 650 | * plus vertical puls width is >= 25. |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 651 | */ |
| 652 | if (mdp_hw_rev < MDSS_MDP_HW_REV_105 || |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 653 | (lcdc->v_back_porch + lcdc->v_pulse_width) >= |
| 654 | MDSS_MDP_MAX_PREFILL_FETCH) |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 655 | return; |
| 656 | |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 657 | adjust_xres = pinfo->xres; |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 658 | if (pinfo->lcdc.split_display) { |
| 659 | if (pinfo->lcdc.dst_split) { |
| 660 | adjust_xres /= 2; |
| 661 | } else if(pinfo->lcdc.dual_pipe) { |
| 662 | if (intf_base == (MDP_INTF_1_BASE + mdss_mdp_intf_offset())) |
| 663 | adjust_xres = pinfo->lm_split[0]; |
| 664 | else |
| 665 | adjust_xres = pinfo->lm_split[1]; |
| 666 | } |
| 667 | } |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 668 | |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 669 | if (pinfo->compression_mode == COMPRESSION_DSC) { |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 670 | adjust_xres = pinfo->dsc.pclk_per_line; |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 671 | } else if (pinfo->compression_mode == COMPRESSION_FBC) { |
| 672 | if (pinfo->fbc.enabled && pinfo->fbc.comp_ratio) |
| 673 | adjust_xres /= pinfo->fbc.comp_ratio; |
| 674 | } |
Jeevan Shriram | 4466729 | 2015-03-17 17:28:39 -0700 | [diff] [blame] | 675 | |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 676 | /* |
| 677 | * Fetch should always be outside the active lines. If the fetching |
| 678 | * is programmed within active region, hardware behavior is unknown. |
| 679 | */ |
| 680 | v_total = lcdc->v_pulse_width + lcdc->v_back_porch + pinfo->yres + |
| 681 | lcdc->v_front_porch; |
| 682 | h_total = lcdc->h_pulse_width + lcdc->h_back_porch + adjust_xres + |
| 683 | lcdc->h_front_porch; |
| 684 | vfp_start = lcdc->v_pulse_width + lcdc->v_back_porch + pinfo->yres; |
| 685 | |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 686 | prefetch_avail = v_total - vfp_start; |
| 687 | prefetch_needed = MDSS_MDP_MAX_PREFILL_FETCH - |
| 688 | lcdc->v_back_porch - |
| 689 | lcdc->v_pulse_width; |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 690 | |
| 691 | /* |
| 692 | * In some cases, vertical front porch is too high. In such cases limit |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 693 | * the mdp fetch lines as the last (25 - vbp - vpw) lines of vertical front porch. |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 694 | */ |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 695 | if (prefetch_avail > prefetch_needed) |
| 696 | prefetch_avail = prefetch_needed; |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 697 | |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 698 | fetch_start = (v_total - prefetch_avail) * h_total + 1; |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 699 | |
Huaibin Yang | 617cbb0 | 2015-01-14 14:17:07 -0800 | [diff] [blame] | 700 | if (pinfo->dfps.panel_dfps.enabled) |
| 701 | fetch_enable |= BIT(23); |
| 702 | |
| 703 | writel_relaxed(fetch_start, MDP_PROG_FETCH_START + intf_base); |
| 704 | writel_relaxed(fetch_enable, MDP_INTF_CONFIG + intf_base); |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 705 | } |
| 706 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 707 | void mdss_layer_mixer_setup(struct fbcon_config *fb, struct msm_panel_info |
| 708 | *pinfo) |
| 709 | { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 710 | uint32_t mdp_rgb_size, height, width; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 711 | uint32_t left_staging_level, right_staging_level; |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 712 | |
Dhaval Patel | 0a9ab81 | 2013-10-25 10:25:06 -0700 | [diff] [blame] | 713 | height = fb->height; |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 714 | width = fb->width; |
| 715 | |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 716 | if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split) |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 717 | width = pinfo->lm_split[0]; |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 718 | |
| 719 | /* write active region size*/ |
| 720 | mdp_rgb_size = (height << 16) | width; |
| 721 | |
| 722 | writel(mdp_rgb_size, MDP_VP_0_MIXER_0_BASE + LAYER_0_OUT_SIZE); |
| 723 | writel(0x00, MDP_VP_0_MIXER_0_BASE + LAYER_0_OP_MODE); |
| 724 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_0_BLEND_OP); |
| 725 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_0_BLEND0_FG_ALPHA); |
| 726 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_1_BLEND_OP); |
| 727 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_1_BLEND0_FG_ALPHA); |
| 728 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_2_BLEND_OP); |
| 729 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_2_BLEND0_FG_ALPHA); |
| 730 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_3_BLEND_OP); |
| 731 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_3_BLEND0_FG_ALPHA); |
| 732 | |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 733 | switch (pinfo->pipe_type) { |
| 734 | case MDSS_MDP_PIPE_TYPE_RGB: |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 735 | left_staging_level = 0x0000200; |
| 736 | right_staging_level = 0x1000; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 737 | break; |
| 738 | case MDSS_MDP_PIPE_TYPE_DMA: |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 739 | left_staging_level = 0x0040000; |
| 740 | right_staging_level = 0x200000; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 741 | break; |
| 742 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 743 | default: |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 744 | left_staging_level = 0x1; |
| 745 | right_staging_level = 0x8; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 746 | break; |
| 747 | } |
| 748 | |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 749 | /* |
| 750 | * When ping-pong split is enabled and two pipes are used, |
| 751 | * both the pipes need to be staged on the same layer mixer. |
| 752 | */ |
| 753 | if (pinfo->lcdc.dual_pipe && pinfo->lcdc.dst_split) |
| 754 | left_staging_level |= right_staging_level; |
| 755 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 756 | /* Base layer for layer mixer 0 */ |
| 757 | writel(left_staging_level, MDP_CTL_0_BASE + CTL_LAYER_0); |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 758 | |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 759 | if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split) { |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 760 | /* write active region size*/ |
| 761 | mdp_rgb_size = (height << 16) | pinfo->lm_split[1]; |
| 762 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 763 | writel(mdp_rgb_size, MDP_VP_0_MIXER_1_BASE + LAYER_0_OUT_SIZE); |
| 764 | writel(0x00, MDP_VP_0_MIXER_1_BASE + LAYER_0_OP_MODE); |
| 765 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_0_BLEND_OP); |
| 766 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_0_BLEND0_FG_ALPHA); |
| 767 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_1_BLEND_OP); |
| 768 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_1_BLEND0_FG_ALPHA); |
| 769 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_2_BLEND_OP); |
| 770 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_2_BLEND0_FG_ALPHA); |
| 771 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND_OP); |
| 772 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND0_FG_ALPHA); |
| 773 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 774 | /* Base layer for layer mixer 1 */ |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 775 | if (pinfo->lcdc.split_display) |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 776 | writel(right_staging_level, MDP_CTL_1_BASE + CTL_LAYER_1); |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 777 | else |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 778 | writel(right_staging_level, MDP_CTL_0_BASE + CTL_LAYER_1); |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 779 | } |
| 780 | } |
| 781 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 782 | void mdss_fbc_cfg(struct msm_panel_info *pinfo) |
| 783 | { |
| 784 | uint32_t mode = 0; |
| 785 | uint32_t budget_ctl = 0; |
| 786 | uint32_t lossy_mode = 0; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 787 | struct fbc_panel_info *fbc; |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 788 | uint32_t enc_mode, width; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 789 | |
| 790 | fbc = &pinfo->fbc; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 791 | |
| 792 | if (!pinfo->fbc.enabled) |
| 793 | return; |
| 794 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 795 | /* enc_mode defines FBC version. 0 = FBC 1.0 and 1 = FBC 2.0 */ |
| 796 | enc_mode = (fbc->comp_ratio == 2) ? 0 : 1; |
| 797 | |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 798 | width = pinfo->xres; |
| 799 | if (enc_mode) |
| 800 | width = (pinfo->xres/fbc->comp_ratio); |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 801 | |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 802 | if (pinfo->mipi.dual_dsi) |
| 803 | width /= 2; |
| 804 | |
| 805 | mode = ((width) << 16) | ((fbc->slice_height) << 11) | |
| 806 | ((fbc->pred_mode) << 10) | (enc_mode) << 9 | |
| 807 | ((fbc->comp_mode) << 8) | ((fbc->qerr_enable) << 7) | |
| 808 | ((fbc->cd_bias) << 4) | ((fbc->pat_enable) << 3) | |
| 809 | ((fbc->vlc_enable) << 2) | ((fbc->bflc_enable) << 1) | 1; |
| 810 | |
| 811 | dprintf(SPEW, "width = %d, slice height = %d, pred_mode =%d, enc_mode = %d, \ |
| 812 | comp_mode %d, qerr_enable = %d, cd_bias = %d\n", |
| 813 | width, fbc->slice_height, fbc->pred_mode, enc_mode, |
| 814 | fbc->comp_mode, fbc->qerr_enable, fbc->cd_bias); |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 815 | dprintf(SPEW, "pat_enable %d, vlc_enable = %d, bflc_enable = %d\n", |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 816 | fbc->pat_enable, fbc->vlc_enable, fbc->bflc_enable); |
| 817 | |
| 818 | budget_ctl = ((fbc->line_x_budget) << 12) | |
| 819 | ((fbc->block_x_budget) << 8) | fbc->block_budget; |
| 820 | |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 821 | lossy_mode = (((fbc->max_pred_err) << 28) | (fbc->lossless_mode_thd) << 16) | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 822 | ((fbc->lossy_mode_thd) << 8) | |
| 823 | ((fbc->lossy_rgb_thd) << 4) | fbc->lossy_mode_idx; |
| 824 | |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 825 | dprintf(SPEW, "mode= 0x%x, budget_ctl = 0x%x, lossy_mode= 0x%x\n", |
| 826 | mode, budget_ctl, lossy_mode); |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 827 | writel(mode, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_MODE); |
| 828 | writel(budget_ctl, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_BUDGET_CTL); |
| 829 | writel(lossy_mode, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_LOSSY_MODE); |
| 830 | |
| 831 | if (pinfo->mipi.dual_dsi) { |
| 832 | writel(mode, MDP_PP_1_BASE + MDSS_MDP_REG_PP_FBC_MODE); |
| 833 | writel(budget_ctl, MDP_PP_1_BASE + |
| 834 | MDSS_MDP_REG_PP_FBC_BUDGET_CTL); |
| 835 | writel(lossy_mode, MDP_PP_1_BASE + |
| 836 | MDSS_MDP_REG_PP_FBC_LOSSY_MODE); |
| 837 | } |
| 838 | } |
| 839 | |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 840 | void mdss_qos_remapper_setup(void) |
| 841 | { |
| 842 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
| 843 | uint32_t map; |
| 844 | |
| 845 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_100) || |
| 846 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 847 | MDSS_MDP_HW_REV_102)) |
| 848 | map = 0xE9; |
| 849 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 850 | MDSS_MDP_HW_REV_101)) |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 851 | map = 0xA5; |
| 852 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | 3908d17 | 2014-06-04 18:00:56 +0530 | [diff] [blame] | 853 | MDSS_MDP_HW_REV_106) || |
| 854 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | fdb5683 | 2015-04-09 21:08:28 -0700 | [diff] [blame] | 855 | MDSS_MDP_HW_REV_108) || |
| 856 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | f912cfb | 2015-06-08 16:36:58 +0530 | [diff] [blame] | 857 | MDSS_MDP_HW_REV_111) || |
| 858 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | fdb5683 | 2015-04-09 21:08:28 -0700 | [diff] [blame] | 859 | MDSS_MDP_HW_REV_112)) |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 860 | map = 0xE4; |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 861 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Chandan Uddaraju | 18a5037 | 2014-10-01 18:45:30 -0700 | [diff] [blame] | 862 | MDSS_MDP_HW_REV_105) || |
| 863 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Jeevan Shriram | 47c936d | 2014-12-19 11:50:13 -0800 | [diff] [blame] | 864 | MDSS_MDP_HW_REV_109) || |
| 865 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Dhaval Patel | 4401467 | 2015-03-26 10:58:32 -0700 | [diff] [blame] | 866 | MDSS_MDP_HW_REV_107) || |
| 867 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Jeevan Shriram | 47c936d | 2014-12-19 11:50:13 -0800 | [diff] [blame] | 868 | MDSS_MDP_HW_REV_110)) |
Ingrid Gallardo | 998ea44 | 2014-09-10 17:22:08 -0700 | [diff] [blame] | 869 | map = 0xA4; |
| 870 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 871 | MDSS_MDP_HW_REV_103)) |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 872 | map = 0xFA; |
| 873 | else |
| 874 | return; |
| 875 | |
| 876 | writel(map, MDP_QOS_REMAPPER_CLASS_0); |
| 877 | } |
| 878 | |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 879 | void mdss_vbif_qos_remapper_setup(struct msm_panel_info *pinfo) |
| 880 | { |
| 881 | uint32_t mask, reg_val, i; |
| 882 | uint32_t left_pipe_xin_id, right_pipe_xin_id; |
| 883 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
| 884 | uint32_t vbif_qos[4] = {0, 0, 0, 0}; |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 885 | uint32_t vbif_offset; |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 886 | |
| 887 | mdp_select_pipe_xin_id(pinfo, |
| 888 | &left_pipe_xin_id, &right_pipe_xin_id); |
| 889 | |
| 890 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_106) || |
Padmanabhan Komanduru | fdb5683 | 2015-04-09 21:08:28 -0700 | [diff] [blame] | 891 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_108) || |
Padmanabhan Komanduru | f912cfb | 2015-06-08 16:36:58 +0530 | [diff] [blame] | 892 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_111) || |
Padmanabhan Komanduru | fdb5683 | 2015-04-09 21:08:28 -0700 | [diff] [blame] | 893 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_112)) { |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 894 | vbif_qos[0] = 2; |
| 895 | vbif_qos[1] = 2; |
| 896 | vbif_qos[2] = 2; |
| 897 | vbif_qos[3] = 2; |
Chandan Uddaraju | 18a5037 | 2014-10-01 18:45:30 -0700 | [diff] [blame] | 898 | } else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_105) || |
Jeevan Shriram | 47c936d | 2014-12-19 11:50:13 -0800 | [diff] [blame] | 899 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_109) || |
Dhaval Patel | 4401467 | 2015-03-26 10:58:32 -0700 | [diff] [blame] | 900 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_107) || |
Jeevan Shriram | 47c936d | 2014-12-19 11:50:13 -0800 | [diff] [blame] | 901 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_110)) { |
Ingrid Gallardo | 998ea44 | 2014-09-10 17:22:08 -0700 | [diff] [blame] | 902 | vbif_qos[0] = 1; |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 903 | vbif_qos[1] = 2; |
| 904 | vbif_qos[2] = 2; |
Ingrid Gallardo | 998ea44 | 2014-09-10 17:22:08 -0700 | [diff] [blame] | 905 | vbif_qos[3] = 2; |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 906 | } else { |
| 907 | return; |
| 908 | } |
| 909 | |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 910 | vbif_offset = mdss_mdp_vbif_qos_remap_get_offset(); |
| 911 | |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 912 | for (i = 0; i < 4; i++) { |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 913 | /* VBIF_VBIF_QOS_REMAP_00 */ |
| 914 | reg_val = readl(REG_MDP(vbif_offset) + i*4); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 915 | mask = 0x3 << (left_pipe_xin_id * 2); |
| 916 | reg_val &= ~(mask); |
| 917 | reg_val |= vbif_qos[i] << (left_pipe_xin_id * 2); |
| 918 | |
| 919 | if (pinfo->lcdc.dual_pipe) { |
| 920 | mask = 0x3 << (right_pipe_xin_id * 2); |
| 921 | reg_val &= ~(mask); |
| 922 | reg_val |= vbif_qos[i] << (right_pipe_xin_id * 2); |
| 923 | } |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 924 | writel(reg_val, REG_MDP(vbif_offset) + i*4); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 925 | } |
| 926 | } |
| 927 | |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 928 | static uint32_t mdss_mdp_ctl_out_sel(struct msm_panel_info *pinfo, |
| 929 | int is_main_ctl) |
| 930 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 931 | uint32_t mctl_intf_sel; |
| 932 | uint32_t sctl_intf_sel; |
| 933 | |
| 934 | if ((pinfo->dest == DISPLAY_2) || |
| 935 | ((pinfo->dest = DISPLAY_1) && (pinfo->lcdc.pipe_swap))) { |
| 936 | mctl_intf_sel = BIT(4) | BIT(5); /* Interface 2 */ |
| 937 | sctl_intf_sel = BIT(5); /* Interface 1 */ |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 938 | } else { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 939 | mctl_intf_sel = BIT(5); /* Interface 1 */ |
| 940 | sctl_intf_sel = BIT(4) | BIT(5); /* Interface 2 */ |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 941 | } |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 942 | dprintf(SPEW, "%s: main ctl dest=%s sec ctl dest=%s\n", __func__, |
| 943 | (mctl_intf_sel & BIT(4)) ? "Intf2" : "Intf1", |
| 944 | (sctl_intf_sel & BIT(4)) ? "Intf2" : "Intf1"); |
| 945 | return is_main_ctl ? mctl_intf_sel : sctl_intf_sel; |
| 946 | } |
| 947 | |
| 948 | static void mdp_set_intf_base(struct msm_panel_info *pinfo, |
| 949 | uint32_t *intf_sel, uint32_t *sintf_sel, |
| 950 | uint32_t *intf_base, uint32_t *sintf_base) |
| 951 | { |
| 952 | if (pinfo->dest == DISPLAY_2) { |
| 953 | *intf_sel = BIT(16); |
| 954 | *sintf_sel = BIT(8); |
| 955 | *intf_base = MDP_INTF_2_BASE + mdss_mdp_intf_offset(); |
| 956 | *sintf_base = MDP_INTF_1_BASE + mdss_mdp_intf_offset(); |
| 957 | } else { |
| 958 | *intf_sel = BIT(8); |
| 959 | *sintf_sel = BIT(16); |
| 960 | *intf_base = MDP_INTF_1_BASE + mdss_mdp_intf_offset(); |
| 961 | *sintf_base = MDP_INTF_2_BASE + mdss_mdp_intf_offset(); |
| 962 | } |
| 963 | dprintf(SPEW, "%s: main intf=%s, sec intf=%s\n", __func__, |
| 964 | (pinfo->dest == DISPLAY_2) ? "Intf2" : "Intf1", |
| 965 | (pinfo->dest == DISPLAY_2) ? "Intf1" : "Intf2"); |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 966 | } |
| 967 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 968 | int mdp_dsi_video_config(struct msm_panel_info *pinfo, |
| 969 | struct fbcon_config *fb) |
| 970 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 971 | uint32_t intf_sel, sintf_sel; |
| 972 | uint32_t intf_base, sintf_base; |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 973 | uint32_t left_pipe, right_pipe; |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 974 | uint32_t reg; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 975 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 976 | mdp_set_intf_base(pinfo, &intf_sel, &sintf_sel, &intf_base, &sintf_base); |
| 977 | |
| 978 | mdss_intf_tg_setup(pinfo, intf_base); |
| 979 | mdss_intf_fetch_start_config(pinfo, intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 980 | |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 981 | if (pinfo->mipi.dual_dsi) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 982 | mdss_intf_tg_setup(pinfo, sintf_base); |
| 983 | mdss_intf_fetch_start_config(pinfo, sintf_base); |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 984 | } |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 985 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 986 | mdp_clk_gating_ctrl(); |
| 987 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 988 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 989 | mdss_vbif_setup(); |
Dhaval Patel | 4401467 | 2015-03-26 10:58:32 -0700 | [diff] [blame] | 990 | if (!has_fixed_size_smp()) |
| 991 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
Siddhartha Agrawal | b1b5a1f | 2013-04-17 19:53:41 -0700 | [diff] [blame] | 992 | |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 993 | mdss_qos_remapper_setup(); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 994 | mdss_vbif_qos_remapper_setup(pinfo); |
Siddhartha Agrawal | b1b5a1f | 2013-04-17 19:53:41 -0700 | [diff] [blame] | 995 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 996 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
| 997 | |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 998 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 999 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1000 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 1001 | mdss_layer_mixer_setup(fb, pinfo); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1002 | |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 1003 | reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo, 1); |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 1004 | |
| 1005 | /* enable 3D mux for dual_pipe but single interface config */ |
| 1006 | if (pinfo->lcdc.dual_pipe && !pinfo->mipi.dual_dsi && |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 1007 | !pinfo->lcdc.split_display) { |
| 1008 | |
| 1009 | if (pinfo->num_dsc_enc != 2) |
| 1010 | reg |= BIT(19) | BIT(20); |
| 1011 | } |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 1012 | |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 1013 | writel(reg, MDP_CTL_0_BASE + CTL_TOP); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1014 | |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 1015 | if ((pinfo->compression_mode == COMPRESSION_DSC) && |
| 1016 | pinfo->dsc.mdp_dsc_config) { |
| 1017 | struct dsc_desc *dsc = &pinfo->dsc; |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 1018 | |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 1019 | if (pinfo->lcdc.dual_pipe && !pinfo->mipi.dual_dsi && |
| 1020 | !pinfo->lcdc.split_display && (pinfo->num_dsc_enc == 2)) { |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 1021 | |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 1022 | dsc->mdp_dsc_config(pinfo, MDP_PP_0_BASE, |
| 1023 | MDP_DSC_0_BASE, true, true); |
| 1024 | dsc->mdp_dsc_config(pinfo, MDP_PP_1_BASE, |
| 1025 | MDP_DSC_1_BASE, true, true); |
| 1026 | } else { |
| 1027 | dsc->mdp_dsc_config(pinfo, MDP_PP_0_BASE, |
| 1028 | MDP_DSC_0_BASE, false, false); |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 1029 | } |
| 1030 | } else if (pinfo->compression_mode == COMPRESSION_FBC) { |
| 1031 | if (pinfo->fbc.enabled) |
| 1032 | mdss_fbc_cfg(pinfo); |
| 1033 | } |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 1034 | |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 1035 | /* |
| 1036 | * if dst_split is enabled, intf 1 & 2 needs to be enabled but |
| 1037 | * CTL_1 path should not be set since CTL_0 itself is going |
| 1038 | * to split after DSPP block and drive both intf. |
| 1039 | */ |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 1040 | if (pinfo->mipi.dual_dsi) { |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 1041 | if (!pinfo->lcdc.dst_split) { |
| 1042 | reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo,0); |
| 1043 | writel(reg, MDP_CTL_1_BASE + CTL_TOP); |
| 1044 | } |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1045 | intf_sel |= sintf_sel; /* INTF 2 enable */ |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 1046 | } |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 1047 | |
| 1048 | writel(intf_sel, MDP_DISP_INTF_SEL); |
| 1049 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1050 | writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); |
| 1051 | writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); |
| 1052 | writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); |
| 1053 | |
| 1054 | return 0; |
| 1055 | } |
| 1056 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1057 | int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb) |
| 1058 | { |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1059 | uint32_t left_pipe, right_pipe; |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1060 | |
| 1061 | mdss_intf_tg_setup(pinfo, MDP_INTF_0_BASE); |
| 1062 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 1063 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1064 | mdp_clk_gating_ctrl(); |
| 1065 | |
| 1066 | mdss_vbif_setup(); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1067 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1068 | |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 1069 | mdss_qos_remapper_setup(); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 1070 | mdss_vbif_qos_remapper_setup(pinfo); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1071 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1072 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 1073 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1074 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1075 | |
| 1076 | mdss_layer_mixer_setup(fb, pinfo); |
| 1077 | |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 1078 | if (pinfo->lcdc.dual_pipe) |
| 1079 | writel(0x181F10, MDP_CTL_0_BASE + CTL_TOP); |
| 1080 | else |
| 1081 | writel(0x1F10, MDP_CTL_0_BASE + CTL_TOP); |
| 1082 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1083 | writel(0x9, MDP_DISP_INTF_SEL); |
| 1084 | writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); |
| 1085 | writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); |
| 1086 | writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); |
| 1087 | |
| 1088 | return 0; |
| 1089 | } |
| 1090 | |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 1091 | int mdss_hdmi_config(struct msm_panel_info *pinfo, struct fbcon_config *fb) |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 1092 | { |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 1093 | uint32_t left_pipe, right_pipe; |
Casey Piper | 77f69c5 | 2015-03-20 15:55:12 -0700 | [diff] [blame] | 1094 | dprintf(SPEW, "ENTER: %s\n", __func__); |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 1095 | |
Casey Piper | 77f69c5 | 2015-03-20 15:55:12 -0700 | [diff] [blame] | 1096 | mdss_intf_tg_setup(pinfo, MDP_INTF_3_BASE + mdss_mdp_intf_offset()); |
| 1097 | pinfo->pipe_type = MDSS_MDP_PIPE_TYPE_RGB; |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 1098 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
| 1099 | |
| 1100 | mdp_clk_gating_ctrl(); |
| 1101 | mdss_vbif_setup(); |
| 1102 | |
| 1103 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
| 1104 | |
| 1105 | mdss_qos_remapper_setup(); |
| 1106 | |
| 1107 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
| 1108 | if (pinfo->lcdc.dual_pipe) |
| 1109 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
| 1110 | |
| 1111 | mdss_layer_mixer_setup(fb, pinfo); |
| 1112 | |
| 1113 | if (pinfo->lcdc.dual_pipe) |
| 1114 | writel(0x181F40, MDP_CTL_0_BASE + CTL_TOP); |
| 1115 | else |
| 1116 | writel(0x40, MDP_CTL_0_BASE + CTL_TOP); |
| 1117 | |
| 1118 | writel(BIT(24) | BIT(25), MDP_DISP_INTF_SEL); |
| 1119 | writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); |
| 1120 | writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); |
| 1121 | writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); |
| 1122 | |
| 1123 | return 0; |
| 1124 | } |
| 1125 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1126 | int mdp_dsi_cmd_config(struct msm_panel_info *pinfo, |
| 1127 | struct fbcon_config *fb) |
| 1128 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1129 | uint32_t intf_sel, sintf_sel; |
| 1130 | uint32_t intf_base, sintf_base; |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 1131 | uint32_t reg; |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1132 | int ret = NO_ERROR; |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1133 | uint32_t left_pipe, right_pipe; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1134 | |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1135 | struct lcdc_panel_info *lcdc = NULL; |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1136 | |
| 1137 | if (pinfo == NULL) |
| 1138 | return ERR_INVALID_ARGS; |
| 1139 | |
| 1140 | lcdc = &(pinfo->lcdc); |
| 1141 | if (lcdc == NULL) |
| 1142 | return ERR_INVALID_ARGS; |
| 1143 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1144 | mdp_set_intf_base(pinfo, &intf_sel, &sintf_sel, &intf_base, &sintf_base); |
| 1145 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1146 | if (pinfo->lcdc.split_display) { |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 1147 | reg = BIT(1); /* Command mode */ |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 1148 | if (pinfo->lcdc.dst_split) |
| 1149 | reg |= BIT(2); /* Enable SMART_PANEL_FREE_RUN mode */ |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 1150 | if (pinfo->lcdc.pipe_swap) |
| 1151 | reg |= BIT(4); /* Use intf2 as trigger */ |
| 1152 | else |
| 1153 | reg |= BIT(8); /* Use intf1 as trigger */ |
| 1154 | writel(reg, MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL); |
| 1155 | writel(reg, MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL); |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1156 | writel(0x1, MDP_REG_SPLIT_DISPLAY_EN); |
| 1157 | } |
| 1158 | |
Padmanabhan Komanduru | 4677a12 | 2014-09-26 16:55:05 +0530 | [diff] [blame] | 1159 | if (pinfo->lcdc.dst_split) { |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 1160 | uint32_t ppb_offset = mdss_mdp_get_ppb_offset(); |
Ujwal Patel | 5c3227b | 2015-08-12 14:48:02 -0700 | [diff] [blame] | 1161 | writel(BIT(5), REG_MDP(ppb_offset)); /* MMSS_MDP_PPB0_CNTL */ |
| 1162 | writel(BIT(16) | (0x3 << 20), REG_MDP(ppb_offset + 0x4)); /* MMSS_MDP_PPB0_CONFIG */ |
Padmanabhan Komanduru | 4677a12 | 2014-09-26 16:55:05 +0530 | [diff] [blame] | 1163 | } |
| 1164 | |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1165 | mdp_clk_gating_ctrl(); |
| 1166 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1167 | if (pinfo->mipi.dual_dsi) |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1168 | intf_sel |= sintf_sel; /* INTF 2 enable */ |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1169 | |
| 1170 | writel(intf_sel, MDP_DISP_INTF_SEL); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1171 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 1172 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 1173 | mdss_vbif_setup(); |
Padmanabhan Komanduru | f1d58a3 | 2015-11-13 19:02:22 +0530 | [diff] [blame] | 1174 | if (!has_fixed_size_smp()) |
| 1175 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 1176 | mdss_qos_remapper_setup(); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 1177 | mdss_vbif_qos_remapper_setup(pinfo); |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 1178 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1179 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
| 1180 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1181 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1182 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1183 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 1184 | mdss_layer_mixer_setup(fb, pinfo); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1185 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1186 | writel(0x213F, MDP_PANEL_FORMAT + intf_base); |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 1187 | reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 1); |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 1188 | |
| 1189 | /* enable 3D mux for dual_pipe but single interface config */ |
| 1190 | if (pinfo->lcdc.dual_pipe && !pinfo->mipi.dual_dsi && |
| 1191 | !pinfo->lcdc.split_display) { |
| 1192 | |
| 1193 | if (pinfo->num_dsc_enc != 2) |
| 1194 | reg |= BIT(19) | BIT(20); |
| 1195 | } |
| 1196 | |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 1197 | writel(reg, MDP_CTL_0_BASE + CTL_TOP); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1198 | |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 1199 | if ((pinfo->compression_mode == COMPRESSION_DSC) && |
| 1200 | pinfo->dsc.mdp_dsc_config) { |
| 1201 | struct dsc_desc *dsc = &pinfo->dsc; |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 1202 | |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 1203 | if (pinfo->lcdc.dual_pipe && !pinfo->mipi.dual_dsi && |
| 1204 | !pinfo->lcdc.split_display && (pinfo->num_dsc_enc == 2)) { |
| 1205 | |
| 1206 | dsc->mdp_dsc_config(pinfo, MDP_PP_0_BASE, |
| 1207 | MDP_DSC_0_BASE, true, true); |
| 1208 | dsc->mdp_dsc_config(pinfo, MDP_PP_1_BASE, |
| 1209 | MDP_DSC_1_BASE, true, true); |
| 1210 | } else { |
| 1211 | dsc->mdp_dsc_config(pinfo, MDP_PP_0_BASE, |
| 1212 | MDP_DSC_0_BASE, false, false); |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 1213 | } |
| 1214 | } else if (pinfo->compression_mode == COMPRESSION_FBC) { |
| 1215 | if (pinfo->fbc.enabled) |
| 1216 | mdss_fbc_cfg(pinfo); |
| 1217 | } |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 1218 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1219 | if (pinfo->mipi.dual_dsi) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1220 | writel(0x213F, sintf_base + MDP_PANEL_FORMAT); |
Padmanabhan Komanduru | 4677a12 | 2014-09-26 16:55:05 +0530 | [diff] [blame] | 1221 | if (!pinfo->lcdc.dst_split) { |
| 1222 | reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 0); |
| 1223 | writel(reg, MDP_CTL_1_BASE + CTL_TOP); |
| 1224 | } |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1225 | } |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1226 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1227 | return ret; |
| 1228 | } |
| 1229 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1230 | int mdp_dsi_video_on(struct msm_panel_info *pinfo) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1231 | { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1232 | uint32_t ctl0_reg_val, ctl1_reg_val; |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1233 | uint32_t timing_engine_en; |
| 1234 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 1235 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1236 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 1237 | if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split) |
| 1238 | writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1239 | |
| 1240 | if (pinfo->dest == DISPLAY_1) |
| 1241 | timing_engine_en = MDP_INTF_1_TIMING_ENGINE_EN; |
| 1242 | else |
| 1243 | timing_engine_en = MDP_INTF_2_TIMING_ENGINE_EN; |
| 1244 | writel(0x01, timing_engine_en + mdss_mdp_intf_offset()); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1245 | |
| 1246 | return NO_ERROR; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1247 | } |
| 1248 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1249 | int mdp_dsi_video_off(struct msm_panel_info *pinfo) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1250 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1251 | uint32_t timing_engine_en; |
| 1252 | |
| 1253 | if (pinfo->dest == DISPLAY_1) |
| 1254 | timing_engine_en = MDP_INTF_1_TIMING_ENGINE_EN; |
| 1255 | else |
| 1256 | timing_engine_en = MDP_INTF_2_TIMING_ENGINE_EN; |
| 1257 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1258 | if(!target_cont_splash_screen()) |
| 1259 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1260 | writel(0x00000000, timing_engine_en + mdss_mdp_intf_offset()); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1261 | mdelay(60); |
| 1262 | /* Ping-Pong done Tear Check Read/Write */ |
| 1263 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 1264 | writel(0xFF777713, MDP_INTR_CLEAR); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1265 | } |
| 1266 | |
Siddhartha Agrawal | 6a59822 | 2013-02-17 18:33:27 -0800 | [diff] [blame] | 1267 | writel(0x00000000, MDP_INTR_EN); |
| 1268 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1269 | return NO_ERROR; |
| 1270 | } |
| 1271 | |
| 1272 | int mdp_dsi_cmd_off() |
| 1273 | { |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1274 | if(!target_cont_splash_screen()) |
| 1275 | { |
| 1276 | /* Ping-Pong done Tear Check Read/Write */ |
| 1277 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 1278 | writel(0xFF777713, MDP_INTR_CLEAR); |
| 1279 | } |
| 1280 | writel(0x00000000, MDP_INTR_EN); |
| 1281 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1282 | return NO_ERROR; |
| 1283 | } |
| 1284 | |
Sandeep Panda | 6c24af7 | 2015-12-23 15:36:07 +0530 | [diff] [blame] | 1285 | static void mdp_set_cmd_autorefresh_mode(struct msm_panel_info *pinfo) |
| 1286 | { |
| 1287 | uint32_t total_lines = 0, vclks_line = 0, cfg = 0; |
| 1288 | |
| 1289 | if (!pinfo || (pinfo->type != MIPI_CMD_PANEL) || |
| 1290 | !pinfo->autorefresh_enable) |
| 1291 | return; |
| 1292 | |
| 1293 | total_lines = pinfo->lcdc.v_front_porch + |
| 1294 | pinfo->lcdc.v_back_porch + |
| 1295 | pinfo->lcdc.v_pulse_width + |
| 1296 | pinfo->border_top + pinfo->border_bottom + |
| 1297 | pinfo->yres; |
| 1298 | total_lines *= pinfo->mipi.frame_rate; |
| 1299 | |
| 1300 | vclks_line = (total_lines) ? 19200000 / total_lines : 0; |
| 1301 | vclks_line = vclks_line * pinfo->mipi.frame_rate * 100 / 6000; |
| 1302 | |
| 1303 | cfg = BIT(19) | vclks_line; |
| 1304 | |
| 1305 | /* Configure tearcheck VSYNC param */ |
| 1306 | writel(cfg, MDP_REG_PP_0_SYNC_CONFIG_VSYNC); |
| 1307 | if (pinfo->lcdc.dst_split) |
| 1308 | writel(cfg, MDP_REG_PP_SLAVE_SYNC_CONFIG_VSYNC); |
| 1309 | if (pinfo->lcdc.dual_pipe) |
| 1310 | writel(cfg, MDP_REG_PP_1_SYNC_CONFIG_VSYNC); |
| 1311 | dsb(); |
| 1312 | |
| 1313 | /* Enable autorefresh mode */ |
| 1314 | writel((BIT(31) | pinfo->autorefresh_framenum), |
| 1315 | MDP_REG_PP_0_AUTOREFRESH_CONFIG); |
| 1316 | if (pinfo->lcdc.dst_split) |
| 1317 | writel((BIT(31) | pinfo->autorefresh_framenum), |
| 1318 | MDP_REG_PP_SLAVE_AUTOREFRESH_CONFIG); |
| 1319 | if (pinfo->lcdc.dual_pipe) |
| 1320 | writel((BIT(31) | pinfo->autorefresh_framenum), |
| 1321 | MDP_REG_PP_1_AUTOREFRESH_CONFIG); |
| 1322 | dsb(); |
| 1323 | } |
| 1324 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1325 | int mdp_dma_on(struct msm_panel_info *pinfo) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1326 | { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1327 | uint32_t ctl0_reg_val, ctl1_reg_val; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 1328 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1329 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 1330 | if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split) |
| 1331 | writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH); |
| 1332 | |
Sandeep Panda | 6c24af7 | 2015-12-23 15:36:07 +0530 | [diff] [blame] | 1333 | if (pinfo->autorefresh_enable) |
| 1334 | mdp_set_cmd_autorefresh_mode(pinfo); |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 1335 | writel(0x01, MDP_CTL_0_BASE + CTL_START); |
Sandeep Panda | 6c24af7 | 2015-12-23 15:36:07 +0530 | [diff] [blame] | 1336 | |
| 1337 | return NO_ERROR; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1338 | } |
| 1339 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1340 | int mdp_edp_on(struct msm_panel_info *pinfo) |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1341 | { |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 1342 | uint32_t ctl0_reg_val, ctl1_reg_val; |
| 1343 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1344 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1345 | writel(0x01, MDP_INTF_0_TIMING_ENGINE_EN + mdss_mdp_intf_offset()); |
| 1346 | return NO_ERROR; |
| 1347 | } |
| 1348 | |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 1349 | int mdss_hdmi_on(struct msm_panel_info *pinfo) |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 1350 | { |
| 1351 | uint32_t ctl0_reg_val, ctl1_reg_val; |
| 1352 | |
| 1353 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
| 1354 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
| 1355 | |
| 1356 | writel(0x01, MDP_INTF_3_TIMING_ENGINE_EN + mdss_mdp_intf_offset()); |
| 1357 | |
| 1358 | return NO_ERROR; |
| 1359 | } |
| 1360 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1361 | int mdp_edp_off(void) |
| 1362 | { |
| 1363 | if (!target_cont_splash_screen()) { |
| 1364 | |
| 1365 | writel(0x00000000, MDP_INTF_0_TIMING_ENGINE_EN + |
| 1366 | mdss_mdp_intf_offset()); |
| 1367 | mdelay(60); |
| 1368 | /* Ping-Pong done Tear Check Read/Write */ |
| 1369 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 1370 | writel(0xFF777713, MDP_INTR_CLEAR); |
| 1371 | writel(0x00000000, MDP_INTR_EN); |
| 1372 | } |
| 1373 | |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 1374 | writel(0x00000000, MDP_INTR_EN); |
| 1375 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1376 | return NO_ERROR; |
| 1377 | } |