Channagoud Kadabi | de6bab0 | 2015-01-21 10:39:46 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <stdint.h> |
| 30 | #include <debug.h> |
| 31 | #include <reg.h> |
| 32 | #include <mmc.h> |
| 33 | #include <clock.h> |
| 34 | #include <platform/timer.h> |
| 35 | #include <platform/clock.h> |
| 36 | #include <platform/iomap.h> |
| 37 | #include <pm8x41.h> |
Channagoud Kadabi | 33686bb | 2015-06-29 11:59:46 -0700 | [diff] [blame] | 38 | #include <rpm-smd.h> |
| 39 | #include <regulator.h> |
Siddharth Zaveri | 1cf08b9 | 2015-12-02 17:09:14 -0500 | [diff] [blame] | 40 | #include <blsp_qup.h> |
| 41 | #include <err.h> |
Channagoud Kadabi | 33686bb | 2015-06-29 11:59:46 -0700 | [diff] [blame] | 42 | |
| 43 | #define RPM_CE_CLK_TYPE 0x6563 |
| 44 | #define CE1_CLK_ID 0x0 |
| 45 | #define RPM_SMD_KEY_RATE 0x007A484B |
| 46 | |
| 47 | uint32_t CE1_CLK[][8]= |
| 48 | { |
| 49 | { |
| 50 | RPM_CE_CLK_TYPE, CE1_CLK_ID, |
| 51 | KEY_SOFTWARE_ENABLE, 4, GENERIC_DISABLE, |
| 52 | RPM_SMD_KEY_RATE, 4, 0, |
| 53 | }, |
| 54 | { |
| 55 | RPM_CE_CLK_TYPE, CE1_CLK_ID, |
| 56 | KEY_SOFTWARE_ENABLE, 4, GENERIC_ENABLE, |
| 57 | RPM_SMD_KEY_RATE, 4, 176128, /* clk rate in KHZ */ |
| 58 | }, |
| 59 | }; |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 60 | |
| 61 | void clock_init_mmc(uint32_t interface) |
| 62 | { |
| 63 | char clk_name[64]; |
| 64 | int ret; |
| 65 | |
| 66 | snprintf(clk_name, sizeof(clk_name), "sdc%u_iface_clk", interface); |
| 67 | |
| 68 | /* enable interface clock */ |
| 69 | ret = clk_get_set_enable(clk_name, 0, true); |
| 70 | if(ret) |
| 71 | { |
| 72 | dprintf(CRITICAL, "failed to set sdc%u_iface_clk ret = %d\n", interface, ret); |
| 73 | ASSERT(0); |
| 74 | } |
| 75 | } |
| 76 | |
| 77 | /* Configure MMC clock */ |
| 78 | void clock_config_mmc(uint32_t interface, uint32_t freq) |
| 79 | { |
| 80 | int ret = 0; |
| 81 | char clk_name[64]; |
| 82 | |
| 83 | snprintf(clk_name, sizeof(clk_name), "sdc%u_core_clk", interface); |
| 84 | |
| 85 | if(freq == MMC_CLK_400KHZ) |
| 86 | { |
| 87 | ret = clk_get_set_enable(clk_name, 400000, true); |
| 88 | } |
| 89 | else if(freq == MMC_CLK_50MHZ) |
| 90 | { |
| 91 | ret = clk_get_set_enable(clk_name, 50000000, true); |
| 92 | } |
| 93 | else if(freq == MMC_CLK_96MHZ) |
| 94 | { |
Channagoud Kadabi | 99d2370 | 2015-02-02 20:52:17 -0800 | [diff] [blame] | 95 | ret = clk_get_set_enable(clk_name, 96000000, true); |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 96 | } |
| 97 | else if(freq == MMC_CLK_192MHZ) |
| 98 | { |
| 99 | ret = clk_get_set_enable(clk_name, 192000000, true); |
| 100 | } |
Channagoud Kadabi | 99d2370 | 2015-02-02 20:52:17 -0800 | [diff] [blame] | 101 | else if(freq == MMC_CLK_400MHZ) |
| 102 | { |
| 103 | ret = clk_get_set_enable(clk_name, 384000000, 1); |
| 104 | } |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 105 | else |
| 106 | { |
| 107 | dprintf(CRITICAL, "sdc frequency (%u) is not supported\n", freq); |
| 108 | ASSERT(0); |
| 109 | } |
| 110 | |
| 111 | if(ret) |
| 112 | { |
| 113 | dprintf(CRITICAL, "failed to set sdc%u_core_clk ret = %d\n", interface, ret); |
| 114 | ASSERT(0); |
| 115 | } |
| 116 | } |
| 117 | |
| 118 | /* Configure UART clock based on the UART block id*/ |
| 119 | void clock_config_uart_dm(uint8_t id) |
| 120 | { |
| 121 | int ret; |
| 122 | char iclk[64]; |
| 123 | char cclk[64]; |
| 124 | |
| 125 | snprintf(iclk, sizeof(iclk), "uart%u_iface_clk", id); |
| 126 | snprintf(cclk, sizeof(cclk), "uart%u_core_clk", id); |
| 127 | |
| 128 | ret = clk_get_set_enable(iclk, 0, true); |
| 129 | if(ret) |
| 130 | { |
| 131 | dprintf(CRITICAL, "failed to set uart%u_iface_clk ret = %d\n", id, ret); |
| 132 | ASSERT(0); |
| 133 | } |
| 134 | |
| 135 | ret = clk_get_set_enable(cclk, 7372800, true); |
| 136 | if(ret) |
| 137 | { |
| 138 | dprintf(CRITICAL, "failed to set uart%u_core_clk ret = %d\n", id, ret); |
| 139 | ASSERT(0); |
| 140 | } |
| 141 | } |
| 142 | |
| 143 | /* Function to asynchronously reset CE (Crypto Engine). |
| 144 | * Function assumes that all the CE clocks are off. |
| 145 | */ |
| 146 | static void ce_async_reset(uint8_t instance) |
| 147 | { |
Channagoud Kadabi | 037c8b8 | 2015-02-05 12:09:32 -0800 | [diff] [blame] | 148 | if (instance == 1) |
| 149 | { |
| 150 | /* Start the block reset for CE */ |
| 151 | writel(1, GCC_CE1_BCR); |
| 152 | udelay(2); |
| 153 | /* Take CE block out of reset */ |
| 154 | writel(0, GCC_CE1_BCR); |
| 155 | udelay(2); |
| 156 | } |
| 157 | else |
| 158 | { |
| 159 | dprintf(CRITICAL, "Unsupported CE instance: %u\n", instance); |
| 160 | ASSERT(0); |
| 161 | } |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 162 | } |
| 163 | |
| 164 | void clock_ce_enable(uint8_t instance) |
| 165 | { |
Channagoud Kadabi | 33686bb | 2015-06-29 11:59:46 -0700 | [diff] [blame] | 166 | if (instance == 1) |
| 167 | rpm_send_data(&CE1_CLK[GENERIC_ENABLE][0], 24, RPM_REQUEST_TYPE); |
| 168 | else |
| 169 | { |
| 170 | dprintf(CRITICAL, "Unsupported CE instance: %u\n", instance); |
| 171 | ASSERT(0); |
| 172 | } |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 173 | } |
| 174 | |
| 175 | void clock_ce_disable(uint8_t instance) |
| 176 | { |
Channagoud Kadabi | 33686bb | 2015-06-29 11:59:46 -0700 | [diff] [blame] | 177 | if (instance == 1) |
| 178 | rpm_send_data(&CE1_CLK[GENERIC_DISABLE][0], 24, RPM_REQUEST_TYPE); |
| 179 | else |
| 180 | { |
| 181 | dprintf(CRITICAL, "Unsupported CE instance: %u\n", instance); |
| 182 | ASSERT(0); |
| 183 | } |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 184 | } |
| 185 | |
| 186 | void clock_config_ce(uint8_t instance) |
| 187 | { |
| 188 | /* Need to enable the clock before disabling since the clk_disable() |
| 189 | * has a check to default to nop when the clk_enable() is not called |
| 190 | * on that particular clock. |
| 191 | */ |
| 192 | clock_ce_enable(instance); |
| 193 | |
| 194 | clock_ce_disable(instance); |
| 195 | |
| 196 | ce_async_reset(instance); |
| 197 | |
| 198 | clock_ce_enable(instance); |
| 199 | |
| 200 | } |
| 201 | |
| 202 | void clock_usb30_gdsc_enable(void) |
| 203 | { |
| 204 | uint32_t reg = readl(GCC_USB30_GDSCR); |
| 205 | |
| 206 | reg &= ~(0x1); |
| 207 | |
| 208 | writel(reg, GCC_USB30_GDSCR); |
| 209 | } |
| 210 | |
| 211 | /* enables usb30 clocks */ |
| 212 | void clock_usb30_init(void) |
| 213 | { |
| 214 | int ret; |
| 215 | |
| 216 | ret = clk_get_set_enable("usb30_iface_clk", 0, true); |
| 217 | if(ret) |
| 218 | { |
| 219 | dprintf(CRITICAL, "failed to set usb30_iface_clk. ret = %d\n", ret); |
| 220 | ASSERT(0); |
| 221 | } |
| 222 | |
| 223 | clock_usb30_gdsc_enable(); |
| 224 | |
Channagoud Kadabi | df233d2 | 2015-02-11 11:56:48 -0800 | [diff] [blame] | 225 | ret = clk_get_set_enable("usb30_master_clk", 150000000, true); |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 226 | if(ret) |
| 227 | { |
| 228 | dprintf(CRITICAL, "failed to set usb30_master_clk. ret = %d\n", ret); |
| 229 | ASSERT(0); |
| 230 | } |
| 231 | |
Channagoud Kadabi | df233d2 | 2015-02-11 11:56:48 -0800 | [diff] [blame] | 232 | ret = clk_get_set_enable("gcc_aggre2_usb3_axi_clk", 150000000, true); |
| 233 | if (ret) |
| 234 | { |
| 235 | dprintf(CRITICAL, "failed to set aggre2_usb3_axi_clk, ret = %d\n", ret); |
| 236 | ASSERT(0); |
| 237 | } |
| 238 | |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 239 | ret = clk_get_set_enable("usb30_phy_aux_clk", 1200000, true); |
| 240 | if(ret) |
| 241 | { |
| 242 | dprintf(CRITICAL, "failed to set usb30_phy_aux_clk. ret = %d\n", ret); |
| 243 | ASSERT(0); |
| 244 | } |
| 245 | |
| 246 | ret = clk_get_set_enable("usb30_mock_utmi_clk", 60000000, true); |
| 247 | if(ret) |
| 248 | { |
| 249 | dprintf(CRITICAL, "failed to set usb30_mock_utmi_clk ret = %d\n", ret); |
| 250 | ASSERT(0); |
| 251 | } |
| 252 | |
| 253 | ret = clk_get_set_enable("usb30_sleep_clk", 0, true); |
| 254 | if(ret) |
| 255 | { |
| 256 | dprintf(CRITICAL, "failed to set usb30_sleep_clk ret = %d\n", ret); |
| 257 | ASSERT(0); |
| 258 | } |
| 259 | |
| 260 | ret = clk_get_set_enable("usb_phy_cfg_ahb2phy_clk", 0, true); |
| 261 | if(ret) |
| 262 | { |
| 263 | dprintf(CRITICAL, "failed to enable usb_phy_cfg_ahb2phy_clk = %d\n", ret); |
| 264 | ASSERT(0); |
| 265 | } |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 266 | } |
| 267 | |
| 268 | void clock_bumpup_pipe3_clk() |
| 269 | { |
| 270 | int ret = 0; |
| 271 | |
| 272 | ret = clk_get_set_enable("usb30_pipe_clk", 0, true); |
| 273 | if(ret) |
| 274 | { |
| 275 | dprintf(CRITICAL, "failed to set usb30_pipe_clk. ret = %d\n", ret); |
| 276 | ASSERT(0); |
| 277 | } |
| 278 | |
| 279 | return; |
| 280 | } |
| 281 | |
| 282 | void clock_reset_usb_phy() |
| 283 | { |
| 284 | int ret; |
| 285 | |
| 286 | struct clk *phy_reset_clk = NULL; |
| 287 | struct clk *pipe_reset_clk = NULL; |
Channagoud Kadabi | a42fb7d | 2015-06-24 12:50:01 -0700 | [diff] [blame] | 288 | struct clk *master_clk = NULL; |
| 289 | |
| 290 | master_clk = clk_get("usb30_master_clk"); |
| 291 | ASSERT(master_clk); |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 292 | |
| 293 | /* Look if phy com clock is present */ |
| 294 | phy_reset_clk = clk_get("usb30_phy_reset"); |
| 295 | ASSERT(phy_reset_clk); |
| 296 | |
| 297 | pipe_reset_clk = clk_get("usb30_pipe_clk"); |
| 298 | ASSERT(pipe_reset_clk); |
| 299 | |
| 300 | /* ASSERT */ |
Channagoud Kadabi | a42fb7d | 2015-06-24 12:50:01 -0700 | [diff] [blame] | 301 | ret = clk_reset(master_clk, CLK_RESET_ASSERT); |
| 302 | if (ret) |
| 303 | { |
| 304 | dprintf(CRITICAL, "Failed to assert usb30_master_reset clk\n"); |
| 305 | return; |
| 306 | } |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 307 | ret = clk_reset(phy_reset_clk, CLK_RESET_ASSERT); |
| 308 | |
| 309 | if (ret) |
| 310 | { |
| 311 | dprintf(CRITICAL, "Failed to assert usb30_phy_reset clk\n"); |
Channagoud Kadabi | a42fb7d | 2015-06-24 12:50:01 -0700 | [diff] [blame] | 312 | goto deassert_master_clk; |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 313 | } |
| 314 | |
| 315 | ret = clk_reset(pipe_reset_clk, CLK_RESET_ASSERT); |
| 316 | if (ret) |
| 317 | { |
| 318 | dprintf(CRITICAL, "Failed to assert usb30_pipe_clk\n"); |
| 319 | goto deassert_phy_clk; |
| 320 | } |
| 321 | |
| 322 | udelay(100); |
| 323 | |
| 324 | /* DEASSERT */ |
| 325 | ret = clk_reset(pipe_reset_clk, CLK_RESET_DEASSERT); |
| 326 | if (ret) |
| 327 | { |
| 328 | dprintf(CRITICAL, "Failed to deassert usb_pipe_clk\n"); |
| 329 | return; |
| 330 | } |
| 331 | |
| 332 | deassert_phy_clk: |
| 333 | |
| 334 | ret = clk_reset(phy_reset_clk, CLK_RESET_DEASSERT); |
| 335 | if (ret) |
| 336 | { |
| 337 | dprintf(CRITICAL, "Failed to deassert usb30_phy_com_reset clk\n"); |
| 338 | return; |
| 339 | } |
Channagoud Kadabi | a42fb7d | 2015-06-24 12:50:01 -0700 | [diff] [blame] | 340 | deassert_master_clk: |
| 341 | |
| 342 | ret = clk_reset(master_clk, CLK_RESET_DEASSERT); |
| 343 | if (ret) |
| 344 | { |
| 345 | dprintf(CRITICAL, "Failed to deassert usb30_master clk\n"); |
| 346 | return; |
| 347 | } |
| 348 | |
Channagoud Kadabi | ed60a8b | 2014-06-27 15:35:09 -0700 | [diff] [blame] | 349 | } |
Dhaval Patel | 0f3cbeb | 2015-03-17 11:52:12 -0700 | [diff] [blame] | 350 | |
| 351 | void mmss_gdsc_enable() |
| 352 | { |
| 353 | uint32_t reg = 0; |
| 354 | |
| 355 | reg = readl(MMAGIC_BIMC_GDSCR); |
| 356 | if (!(reg & GDSC_POWER_ON_BIT)) { |
| 357 | reg &= ~(BIT(0) | GDSC_EN_FEW_WAIT_MASK); |
| 358 | reg |= GDSC_EN_FEW_WAIT_256_MASK; |
| 359 | writel(reg, MMAGIC_BIMC_GDSCR); |
| 360 | while(!(readl(MMAGIC_BIMC_GDSCR) & (GDSC_POWER_ON_BIT))); |
| 361 | } else { |
| 362 | dprintf(SPEW, "MMAGIC BIMC GDSC already enabled\n"); |
| 363 | } |
| 364 | |
| 365 | reg = readl(MMAGIC_MDSS_GDSCR); |
| 366 | if (!(reg & GDSC_POWER_ON_BIT)) { |
| 367 | reg &= ~(BIT(0) | GDSC_EN_FEW_WAIT_MASK); |
| 368 | reg |= GDSC_EN_FEW_WAIT_256_MASK; |
| 369 | writel(reg, MMAGIC_MDSS_GDSCR); |
| 370 | while(!(readl(MMAGIC_MDSS_GDSCR) & (GDSC_POWER_ON_BIT))); |
| 371 | } else { |
| 372 | dprintf(SPEW, "MMAGIC MDSS GDSC already enabled\n"); |
| 373 | } |
| 374 | |
| 375 | reg = readl(MDSS_GDSCR); |
| 376 | if (!(reg & GDSC_POWER_ON_BIT)) { |
| 377 | reg &= ~(BIT(0) | GDSC_EN_FEW_WAIT_MASK); |
| 378 | reg |= GDSC_EN_FEW_WAIT_256_MASK; |
| 379 | writel(reg, MDSS_GDSCR); |
| 380 | while(!(readl(MDSS_GDSCR) & (GDSC_POWER_ON_BIT))); |
| 381 | } else { |
| 382 | dprintf(SPEW, "MDSS GDSC already enabled\n"); |
| 383 | } |
| 384 | } |
| 385 | |
| 386 | void mmss_gdsc_disable() |
| 387 | { |
| 388 | uint32_t reg = 0; |
| 389 | |
| 390 | reg = readl(MDSS_GDSCR); |
| 391 | reg |= BIT(0); |
| 392 | writel(reg, MDSS_GDSCR); |
| 393 | while(readl(MDSS_GDSCR) & (GDSC_POWER_ON_BIT)); |
| 394 | |
| 395 | reg = readl(MMAGIC_MDSS_GDSCR); |
| 396 | reg |= BIT(0); |
| 397 | writel(reg, MMAGIC_MDSS_GDSCR); |
| 398 | while(readl(MMAGIC_MDSS_GDSCR) & (GDSC_POWER_ON_BIT)); |
| 399 | |
| 400 | reg = readl(MMAGIC_BIMC_GDSCR); |
| 401 | reg |= BIT(0); |
| 402 | writel(reg, MMAGIC_BIMC_GDSCR); |
| 403 | while(readl(MMAGIC_BIMC_GDSCR) & (GDSC_POWER_ON_BIT)); |
| 404 | } |
| 405 | |
| 406 | void video_gdsc_enable() |
| 407 | { |
| 408 | uint32_t reg = 0; |
| 409 | |
| 410 | reg = readl(MMAGIC_VIDEO_GDSCR); |
| 411 | if (!(reg & GDSC_POWER_ON_BIT)) { |
| 412 | reg &= ~(BIT(0) | GDSC_EN_FEW_WAIT_MASK); |
| 413 | reg |= GDSC_EN_FEW_WAIT_256_MASK; |
| 414 | writel(reg, MMAGIC_VIDEO_GDSCR); |
| 415 | while(!(readl(MMAGIC_VIDEO_GDSCR) & (GDSC_POWER_ON_BIT))); |
| 416 | } else { |
| 417 | dprintf(SPEW, "VIDEO BIMC GDSC already enabled\n"); |
| 418 | } |
| 419 | |
| 420 | reg = readl(VIDEO_GDSCR); |
| 421 | if (!(reg & GDSC_POWER_ON_BIT)) { |
| 422 | reg &= ~(BIT(0) | GDSC_EN_FEW_WAIT_MASK); |
| 423 | reg |= GDSC_EN_FEW_WAIT_256_MASK; |
| 424 | writel(reg, VIDEO_GDSCR); |
| 425 | while(!(readl(VIDEO_GDSCR) & (GDSC_POWER_ON_BIT))); |
| 426 | } else { |
| 427 | dprintf(SPEW, "VIDEO GDSC already enabled\n"); |
| 428 | } |
| 429 | } |
| 430 | |
| 431 | void video_gdsc_disable() |
| 432 | { |
| 433 | uint32_t reg = 0; |
| 434 | |
| 435 | reg = readl(VIDEO_GDSCR); |
| 436 | reg |= BIT(0); |
| 437 | writel(reg, VIDEO_GDSCR); |
| 438 | while(readl(VIDEO_GDSCR) & (GDSC_POWER_ON_BIT)); |
| 439 | |
| 440 | reg = readl(MMAGIC_VIDEO_GDSCR); |
| 441 | reg |= BIT(0); |
| 442 | writel(reg, MMAGIC_VIDEO_GDSCR); |
| 443 | while(readl(MMAGIC_VIDEO_GDSCR) & (GDSC_POWER_ON_BIT)); |
| 444 | } |
| 445 | |
| 446 | /* Configure MDP clock */ |
| 447 | void mdp_clock_enable(void) |
| 448 | { |
| 449 | int ret; |
| 450 | |
| 451 | ret = clk_get_set_enable("mmss_mmagic_ahb_clk", 19200000, 1); |
| 452 | if(ret) |
| 453 | { |
| 454 | dprintf(CRITICAL, "failed to set mmagic_ahb_clk ret = %d\n", ret); |
| 455 | ASSERT(0); |
| 456 | } |
| 457 | |
| 458 | ret = clk_get_set_enable("smmu_mdp_ahb_clk", 0, 1); |
| 459 | if(ret) |
| 460 | { |
| 461 | dprintf(CRITICAL, "failed to set smmu_mdp_ahb_clk ret = %d\n", ret); |
| 462 | ASSERT(0); |
| 463 | } |
| 464 | |
| 465 | ret = clk_get_set_enable("mdp_ahb_clk", 0, 1); |
| 466 | if(ret) |
| 467 | { |
| 468 | dprintf(CRITICAL, "failed to set mdp_ahb_clk ret = %d\n", ret); |
| 469 | ASSERT(0); |
| 470 | } |
| 471 | |
| 472 | ret = clk_get_set_enable("mdss_mdp_clk", 320000000, 1); |
| 473 | if(ret) |
| 474 | { |
| 475 | dprintf(CRITICAL, "failed to set mdp_clk_src ret = %d\n", ret); |
| 476 | ASSERT(0); |
| 477 | } |
| 478 | |
| 479 | ret = clk_get_set_enable("mdss_vsync_clk", 0, 1); |
| 480 | if(ret) |
| 481 | { |
| 482 | dprintf(CRITICAL, "failed to set mdss vsync clk ret = %d\n", ret); |
| 483 | ASSERT(0); |
| 484 | } |
| 485 | |
| 486 | } |
| 487 | |
| 488 | void mdp_clock_disable() |
| 489 | { |
| 490 | clk_disable(clk_get("mdss_vsync_clk")); |
| 491 | clk_disable(clk_get("mdss_mdp_clk")); |
| 492 | clk_disable(clk_get("mdp_ahb_clk")); |
| 493 | clk_disable(clk_get("smmu_mdp_ahb_clk")); |
| 494 | clk_disable(clk_get("mmss_mmagic_ahb_clk")); |
| 495 | } |
| 496 | |
| 497 | void mmss_bus_clock_enable(void) |
| 498 | { |
| 499 | int ret; |
| 500 | ret = clk_get_set_enable("mmss_mmagic_axi_clk", 320000000, 1); |
| 501 | if(ret) |
| 502 | { |
| 503 | dprintf(CRITICAL, "failed to set mmss_mmagic_axi_clk ret = %d\n", ret); |
| 504 | ASSERT(0); |
| 505 | } |
| 506 | |
| 507 | ret = clk_get_set_enable("mmagic_bimc_axi_clk", 320000000, 1); |
| 508 | if(ret) |
| 509 | { |
| 510 | dprintf(CRITICAL, "failed to set mmss_s0_axi_clk ret = %d\n", ret); |
| 511 | ASSERT(0); |
| 512 | } |
| 513 | |
| 514 | ret = clk_get_set_enable("mmss_s0_axi_clk", 320000000, 1); |
| 515 | if(ret) |
| 516 | { |
| 517 | dprintf(CRITICAL, "failed to set mmss_s0_axi_clk ret = %d\n", ret); |
| 518 | ASSERT(0); |
| 519 | } |
| 520 | |
| 521 | ret = clk_get_set_enable("mmagic_mdss_axi_clk", 320000000, 1); |
| 522 | if(ret) |
| 523 | { |
| 524 | dprintf(CRITICAL, "failed to set mmss_mmagic_axi_clk ret = %d\n", ret); |
| 525 | ASSERT(0); |
| 526 | } |
| 527 | |
| 528 | ret = clk_get_set_enable("smmu_mdp_axi_clk", 320000000, 1); |
| 529 | if(ret) |
| 530 | { |
| 531 | dprintf(CRITICAL, "failed to set smmu_mdp_axi_clk ret = %d\n", ret); |
| 532 | ASSERT(0); |
| 533 | } |
| 534 | |
| 535 | ret = clk_get_set_enable("mdss_axi_clk", 320000000, 1); |
| 536 | if(ret) |
| 537 | { |
| 538 | dprintf(CRITICAL, "failed to set mdss_axi_clk ret = %d\n", ret); |
| 539 | ASSERT(0); |
| 540 | } |
| 541 | } |
| 542 | |
| 543 | void mmss_bus_clock_disable(void) |
| 544 | { |
| 545 | clk_disable(clk_get("mdss_axi_clk")); |
| 546 | clk_disable(clk_get("smmu_mdp_axi_clk")); |
| 547 | clk_disable(clk_get("mmagic_mdss_axi_clk")); |
| 548 | clk_disable(clk_get("mmss_s0_axi_clk")); |
| 549 | clk_disable(clk_get("mmagic_bimc_axi_clk")); |
| 550 | clk_disable(clk_get("mmss_mmagic_axi_clk")); |
| 551 | } |
| 552 | |
Aravind Venkateswaran | 9586be6 | 2015-05-20 00:51:06 -0700 | [diff] [blame] | 553 | void mmss_dsi_clock_enable(uint32_t cfg_rcgr, uint32_t flags) |
Dhaval Patel | 0f3cbeb | 2015-03-17 11:52:12 -0700 | [diff] [blame] | 554 | { |
| 555 | int ret; |
| 556 | |
| 557 | if (flags & MMSS_DSI_CLKS_FLAG_DSI0) { |
| 558 | /* Enable DSI0 branch clocks */ |
| 559 | |
Aravind Venkateswaran | 9586be6 | 2015-05-20 00:51:06 -0700 | [diff] [blame] | 560 | writel(cfg_rcgr, DSI_BYTE0_CFG_RCGR); |
Dhaval Patel | 0f3cbeb | 2015-03-17 11:52:12 -0700 | [diff] [blame] | 561 | writel(0x1, DSI_BYTE0_CMD_RCGR); |
| 562 | writel(0x1, DSI_BYTE0_CBCR); |
| 563 | |
Aravind Venkateswaran | 9586be6 | 2015-05-20 00:51:06 -0700 | [diff] [blame] | 564 | writel(cfg_rcgr, DSI_PIXEL0_CFG_RCGR); |
Dhaval Patel | 0f3cbeb | 2015-03-17 11:52:12 -0700 | [diff] [blame] | 565 | writel(0x1, DSI_PIXEL0_CMD_RCGR); |
| 566 | writel(0x1, DSI_PIXEL0_CBCR); |
| 567 | |
| 568 | ret = clk_get_set_enable("mdss_esc0_clk", 0, 1); |
| 569 | if(ret) |
| 570 | { |
| 571 | dprintf(CRITICAL, "failed to set esc0_clk ret = %d\n", ret); |
| 572 | ASSERT(0); |
| 573 | } |
| 574 | } |
| 575 | |
| 576 | if (flags & MMSS_DSI_CLKS_FLAG_DSI1) { |
| 577 | /* Enable DSI1 branch clocks */ |
Aravind Venkateswaran | 9586be6 | 2015-05-20 00:51:06 -0700 | [diff] [blame] | 578 | writel(cfg_rcgr, DSI_BYTE1_CFG_RCGR); |
Dhaval Patel | 0f3cbeb | 2015-03-17 11:52:12 -0700 | [diff] [blame] | 579 | writel(0x1, DSI_BYTE1_CMD_RCGR); |
| 580 | writel(0x1, DSI_BYTE1_CBCR); |
| 581 | |
Aravind Venkateswaran | 9586be6 | 2015-05-20 00:51:06 -0700 | [diff] [blame] | 582 | writel(cfg_rcgr, DSI_PIXEL1_CFG_RCGR); |
Dhaval Patel | 0f3cbeb | 2015-03-17 11:52:12 -0700 | [diff] [blame] | 583 | writel(0x1, DSI_PIXEL1_CMD_RCGR); |
| 584 | writel(0x1, DSI_PIXEL1_CBCR); |
| 585 | |
| 586 | ret = clk_get_set_enable("mdss_esc1_clk", 0, 1); |
| 587 | if(ret) |
| 588 | { |
| 589 | dprintf(CRITICAL, "failed to set esc1_clk ret = %d\n", ret); |
| 590 | ASSERT(0); |
| 591 | } |
| 592 | } |
| 593 | } |
| 594 | |
| 595 | void mmss_dsi_clock_disable(uint32_t flags) |
| 596 | { |
| 597 | if (flags & MMSS_DSI_CLKS_FLAG_DSI0) { |
| 598 | clk_disable(clk_get("mdss_esc0_clk")); |
| 599 | writel(0x0, DSI_BYTE0_CBCR); |
| 600 | writel(0x0, DSI_PIXEL0_CBCR); |
| 601 | } |
| 602 | |
| 603 | if (flags & MMSS_DSI_CLKS_FLAG_DSI1) { |
| 604 | clk_disable(clk_get("mdss_esc1_clk")); |
| 605 | writel(0x0, DSI_BYTE1_CBCR); |
| 606 | writel(0x0, DSI_PIXEL1_CBCR); |
| 607 | } |
| 608 | } |
Siddharth Zaveri | 1cf08b9 | 2015-12-02 17:09:14 -0500 | [diff] [blame] | 609 | |
| 610 | |
| 611 | void clock_config_blsp_i2c(uint8_t blsp_id, uint8_t qup_id) |
| 612 | { |
| 613 | uint8_t ret = 0; |
| 614 | char clk_name[64]; |
| 615 | |
| 616 | struct clk *qup_clk; |
| 617 | |
| 618 | if((blsp_id != BLSP_ID_2) || ((qup_id != QUP_ID_1) && |
| 619 | (qup_id != QUP_ID_3))) { |
| 620 | dprintf(CRITICAL, "Incorrect BLSP-%d or QUP-%d configuration\n", |
| 621 | blsp_id, qup_id); |
| 622 | ASSERT(0); |
| 623 | } |
| 624 | |
| 625 | if (qup_id == QUP_ID_1) { |
| 626 | snprintf(clk_name, sizeof(clk_name), "blsp2_qup2_ahb_iface_clk"); |
| 627 | } |
| 628 | else if (qup_id == QUP_ID_3) { |
| 629 | snprintf(clk_name, sizeof(clk_name), "blsp1_qup4_ahb_iface_clk"); |
| 630 | } |
| 631 | |
| 632 | ret = clk_get_set_enable(clk_name, 0 , 1); |
| 633 | if (ret) { |
| 634 | dprintf(CRITICAL, "Failed to enable %s clock\n", clk_name); |
| 635 | return; |
| 636 | } |
| 637 | |
| 638 | if (qup_id == QUP_ID_1) { |
| 639 | snprintf(clk_name, sizeof(clk_name), "gcc_blsp2_qup2_i2c_apps_clk"); |
| 640 | } |
| 641 | else if (qup_id == QUP_ID_3) { |
| 642 | snprintf(clk_name, sizeof(clk_name), "gcc_blsp1_qup4_i2c_apps_clk"); |
| 643 | } |
| 644 | |
| 645 | qup_clk = clk_get(clk_name); |
| 646 | if (!qup_clk) { |
| 647 | dprintf(CRITICAL, "Failed to get %s\n", clk_name); |
| 648 | return; |
| 649 | } |
| 650 | |
| 651 | ret = clk_enable(qup_clk); |
| 652 | if (ret) { |
| 653 | dprintf(CRITICAL, "Failed to enable %s\n", clk_name); |
| 654 | return; |
| 655 | } |
| 656 | } |