Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved. |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 12 | * * Neither the name of The Linux Foundation nor the names of its |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #include <reg.h> |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 31 | #include <endian.h> |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 32 | #include <mipi_dsi.h> |
| 33 | #include <dev/fbcon.h> |
Greg Grisco | d625055 | 2011-06-29 14:40:23 -0700 | [diff] [blame] | 34 | #include <stdlib.h> |
Greg Grisco | 1073a5e | 2011-07-28 18:59:18 -0700 | [diff] [blame] | 35 | #include <string.h> |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 36 | #include <debug.h> |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 37 | #include <target/display.h> |
| 38 | #include <platform/iomap.h> |
| 39 | #include <platform/clock.h> |
Greg Grisco | 1073a5e | 2011-07-28 18:59:18 -0700 | [diff] [blame] | 40 | #include <platform/timer.h> |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 41 | #include <err.h> |
| 42 | #include <msm_panel.h> |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 43 | |
| 44 | extern void mdp_disable(void); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 45 | extern int mipi_dsi_cmd_config(struct fbcon_config mipi_fb_cfg, |
| 46 | unsigned short num_of_lanes); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 47 | extern void mdp_shutdown(void); |
| 48 | extern void mdp_start_dma(void); |
Deepa Dinamani | a080a40 | 2011-11-05 18:59:26 -0700 | [diff] [blame] | 49 | extern void dsb(void); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 50 | |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 51 | #if (DISPLAY_TYPE_MDSS == 0) |
| 52 | #define MIPI_DSI0_BASE MIPI_DSI_BASE |
| 53 | #define MIPI_DSI1_BASE MIPI_DSI_BASE |
| 54 | #endif |
| 55 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 56 | #if DISPLAY_MIPI_PANEL_TOSHIBA |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 57 | static struct fbcon_config mipi_fb_cfg = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 58 | .height = TSH_MIPI_FB_HEIGHT, |
| 59 | .width = TSH_MIPI_FB_WIDTH, |
| 60 | .stride = TSH_MIPI_FB_WIDTH, |
| 61 | .format = FB_FORMAT_RGB888, |
| 62 | .bpp = 24, |
| 63 | .update_start = NULL, |
| 64 | .update_done = NULL, |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 65 | }; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 66 | |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 67 | struct mipi_dsi_panel_config toshiba_panel_info = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 68 | .mode = MIPI_VIDEO_MODE, |
| 69 | .num_of_lanes = 1, |
| 70 | .dsi_phy_config = &mipi_dsi_toshiba_panel_phy_ctrl, |
| 71 | .panel_cmds = toshiba_panel_video_mode_cmds, |
| 72 | .num_of_panel_cmds = ARRAY_SIZE(toshiba_panel_video_mode_cmds), |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 73 | }; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 74 | #elif DISPLAY_MIPI_PANEL_NOVATEK_BLUE |
| 75 | static struct fbcon_config mipi_fb_cfg = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 76 | .height = NOV_MIPI_FB_HEIGHT, |
| 77 | .width = NOV_MIPI_FB_WIDTH, |
| 78 | .stride = NOV_MIPI_FB_WIDTH, |
| 79 | .format = FB_FORMAT_RGB888, |
| 80 | .bpp = 24, |
| 81 | .update_start = NULL, |
| 82 | .update_done = NULL, |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 83 | }; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 84 | |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 85 | struct mipi_dsi_panel_config novatek_panel_info = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 86 | .mode = MIPI_CMD_MODE, |
| 87 | .num_of_lanes = 2, |
| 88 | .dsi_phy_config = &mipi_dsi_novatek_panel_phy_ctrl, |
| 89 | .panel_cmds = novatek_panel_cmd_mode_cmds, |
| 90 | .num_of_panel_cmds = ARRAY_SIZE(novatek_panel_cmd_mode_cmds), |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 91 | }; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 92 | #else |
| 93 | static struct fbcon_config mipi_fb_cfg = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 94 | .height = 0, |
| 95 | .width = 0, |
| 96 | .stride = 0, |
| 97 | .format = 0, |
| 98 | .bpp = 0, |
| 99 | .update_start = NULL, |
| 100 | .update_done = NULL, |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 101 | }; |
| 102 | #endif |
| 103 | |
| 104 | static int cmd_mode_status = 0; |
Greg Grisco | d625055 | 2011-06-29 14:40:23 -0700 | [diff] [blame] | 105 | void secure_writel(uint32_t, uint32_t); |
| 106 | uint32_t secure_readl(uint32_t); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 107 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 108 | struct mipi_dsi_panel_config *get_panel_info(void) |
| 109 | { |
| 110 | #if DISPLAY_MIPI_PANEL_TOSHIBA |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 111 | return &toshiba_panel_info; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 112 | #elif DISPLAY_MIPI_PANEL_NOVATEK_BLUE |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 113 | return &novatek_panel_info; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 114 | #endif |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 115 | return NULL; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 116 | } |
| 117 | |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 118 | int mdss_dual_dsi_cmd_dma_trigger_for_panel() |
| 119 | { |
| 120 | uint32_t ReadValue; |
| 121 | uint32_t count = 0; |
| 122 | int status = 0; |
| 123 | |
| 124 | writel(0x03030303, MIPI_DSI0_BASE + INT_CTRL); |
| 125 | writel(0x1, MIPI_DSI0_BASE + CMD_MODE_DMA_SW_TRIGGER); |
| 126 | dsb(); |
| 127 | |
| 128 | writel(0x03030303, MIPI_DSI1_BASE + INT_CTRL); |
| 129 | writel(0x1, MIPI_DSI1_BASE + CMD_MODE_DMA_SW_TRIGGER); |
| 130 | dsb(); |
| 131 | |
| 132 | ReadValue = readl(MIPI_DSI1_BASE + INT_CTRL) & 0x00000001; |
| 133 | while (ReadValue != 0x00000001) { |
| 134 | ReadValue = readl(MIPI_DSI1_BASE + INT_CTRL) & 0x00000001; |
| 135 | count++; |
| 136 | if (count > 0xffff) { |
| 137 | status = FAIL; |
| 138 | dprintf(CRITICAL, |
| 139 | "Panel CMD: command mode dma test failed\n"); |
| 140 | return status; |
| 141 | } |
| 142 | } |
| 143 | |
| 144 | writel((readl(MIPI_DSI1_BASE + INT_CTRL) | 0x01000001), |
| 145 | MIPI_DSI1_BASE + INT_CTRL); |
| 146 | dprintf(SPEW, "Panel CMD: command mode dma tested successfully\n"); |
| 147 | return status; |
| 148 | } |
| 149 | |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 150 | int dsi_cmd_dma_trigger_for_panel() |
| 151 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 152 | unsigned long ReadValue; |
| 153 | unsigned long count = 0; |
| 154 | int status = 0; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 155 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 156 | writel(0x03030303, DSI_INT_CTRL); |
| 157 | writel(0x1, DSI_CMD_MODE_DMA_SW_TRIGGER); |
| 158 | dsb(); |
| 159 | ReadValue = readl(DSI_INT_CTRL) & 0x00000001; |
| 160 | while (ReadValue != 0x00000001) { |
| 161 | ReadValue = readl(DSI_INT_CTRL) & 0x00000001; |
| 162 | count++; |
| 163 | if (count > 0xffff) { |
| 164 | status = FAIL; |
| 165 | dprintf(CRITICAL, |
| 166 | "Panel CMD: command mode dma test failed\n"); |
| 167 | return status; |
| 168 | } |
| 169 | } |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 170 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 171 | writel((readl(DSI_INT_CTRL) | 0x01000001), DSI_INT_CTRL); |
| 172 | dprintf(SPEW, "Panel CMD: command mode dma tested successfully\n"); |
| 173 | return status; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 174 | } |
| 175 | |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 176 | int mdss_dual_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count) |
| 177 | { |
| 178 | int ret = 0; |
| 179 | struct mipi_dsi_cmd *cm; |
| 180 | int i = 0; |
| 181 | char pload[256]; |
| 182 | uint32_t off; |
| 183 | |
| 184 | /* Align pload at 8 byte boundry */ |
| 185 | off = pload; |
| 186 | off &= 0x07; |
| 187 | if (off) |
| 188 | off = 8 - off; |
| 189 | off += pload; |
| 190 | |
| 191 | cm = cmds; |
| 192 | for (i = 0; i < count; i++) { |
| 193 | memcpy((void *)off, (cm->payload), cm->size); |
| 194 | writel(off, MIPI_DSI0_BASE + DMA_CMD_OFFSET); |
| 195 | writel(cm->size, MIPI_DSI0_BASE + DMA_CMD_LENGTH); // reg 0x48 for this build |
| 196 | writel(off, MIPI_DSI1_BASE + DMA_CMD_OFFSET); |
| 197 | writel(cm->size, MIPI_DSI1_BASE + DMA_CMD_LENGTH); // reg 0x48 for this build |
| 198 | dsb(); |
| 199 | ret += mdss_dual_dsi_cmd_dma_trigger_for_panel(); |
| 200 | udelay(80); |
| 201 | cm++; |
| 202 | } |
| 203 | return ret; |
| 204 | } |
| 205 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 206 | int mipi_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count) |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 207 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 208 | int ret = 0; |
| 209 | struct mipi_dsi_cmd *cm; |
| 210 | int i = 0; |
| 211 | char pload[256]; |
| 212 | uint32_t off; |
Deepa Dinamani | a080a40 | 2011-11-05 18:59:26 -0700 | [diff] [blame] | 213 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 214 | /* Align pload at 8 byte boundry */ |
| 215 | off = pload; |
| 216 | off &= 0x07; |
| 217 | if (off) |
| 218 | off = 8 - off; |
| 219 | off += pload; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 220 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 221 | cm = cmds; |
| 222 | for (i = 0; i < count; i++) { |
| 223 | memcpy((void *)off, (cm->payload), cm->size); |
| 224 | writel(off, DSI_DMA_CMD_OFFSET); |
| 225 | writel(cm->size, DSI_DMA_CMD_LENGTH); // reg 0x48 for this build |
| 226 | dsb(); |
| 227 | ret += dsi_cmd_dma_trigger_for_panel(); |
| 228 | udelay(80); |
| 229 | cm++; |
| 230 | } |
| 231 | return ret; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 232 | } |
| 233 | |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 234 | /* |
| 235 | * mipi_dsi_cmd_rx: can receive at most 16 bytes |
| 236 | * per transaction since it only have 4 32bits reigsters |
| 237 | * to hold data. |
| 238 | * therefore Maximum Return Packet Size need to be set to 16. |
| 239 | * any return data more than MRPS need to be break down |
| 240 | * to multiple transactions. |
| 241 | */ |
| 242 | int mipi_dsi_cmds_rx(char **rp, int len) |
| 243 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 244 | uint32_t *lp, data; |
| 245 | char *dp; |
| 246 | int i, off, cnt; |
| 247 | int rlen, res; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 248 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 249 | if (len <= 2) |
| 250 | rlen = 4; /* short read */ |
| 251 | else |
| 252 | rlen = MIPI_DSI_MRPS + 6; /* 4 bytes header + 2 bytes crc */ |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 253 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 254 | if (rlen > MIPI_DSI_REG_LEN) { |
| 255 | return 0; |
| 256 | } |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 257 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 258 | res = rlen & 0x03; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 259 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 260 | rlen += res; /* 4 byte align */ |
| 261 | lp = (uint32_t *) (*rp); |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 262 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 263 | cnt = rlen; |
| 264 | cnt += 3; |
| 265 | cnt >>= 2; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 266 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 267 | if (cnt > 4) |
| 268 | cnt = 4; /* 4 x 32 bits registers only */ |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 269 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 270 | off = 0x068; /* DSI_RDBK_DATA0 */ |
| 271 | off += ((cnt - 1) * 4); |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 272 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 273 | for (i = 0; i < cnt; i++) { |
| 274 | data = (uint32_t) readl(MIPI_DSI_BASE + off); |
| 275 | *lp++ = ntohl(data); /* to network byte order */ |
| 276 | off -= 4; |
| 277 | } |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 278 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 279 | if (len > 2) { |
| 280 | /*First 4 bytes + paded bytes will be header next len bytes would be payload */ |
| 281 | for (i = 0; i < len; i++) { |
| 282 | dp = *rp; |
| 283 | dp[i] = dp[4 + res + i]; |
| 284 | } |
| 285 | } |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 286 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 287 | return len; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 288 | } |
| 289 | |
| 290 | static int mipi_dsi_cmd_bta_sw_trigger(void) |
| 291 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 292 | uint32_t data; |
| 293 | int cnt = 0; |
| 294 | int err = 0; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 295 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 296 | writel(0x01, MIPI_DSI_BASE + 0x094); /* trigger */ |
| 297 | while (cnt < 10000) { |
| 298 | data = readl(MIPI_DSI_BASE + 0x0004); /*DSI_STATUS */ |
| 299 | if ((data & 0x0010) == 0) |
| 300 | break; |
| 301 | cnt++; |
| 302 | } |
| 303 | if (cnt == 10000) |
| 304 | err = 1; |
| 305 | return err; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 306 | } |
| 307 | |
| 308 | static uint32_t mipi_novatek_manufacture_id(void) |
| 309 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 310 | char rec_buf[24]; |
| 311 | char *rp = rec_buf; |
| 312 | uint32_t *lp, data; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 313 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 314 | mipi_dsi_cmds_tx(&novatek_panel_manufacture_id_cmd, 1); |
| 315 | mipi_dsi_cmds_rx(&rp, 3); |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 316 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 317 | lp = (uint32_t *) rp; |
| 318 | data = (uint32_t) * lp; |
| 319 | data = ntohl(data); |
| 320 | data = data >> 8; |
| 321 | return data; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 322 | } |
| 323 | |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 324 | int mdss_dsi_panel_initialize(struct mipi_dsi_panel_config *pinfo, uint32_t |
| 325 | broadcast) |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 326 | { |
| 327 | uint8_t DMA_STREAM1 = 0; // for mdp display processor path |
| 328 | uint8_t EMBED_MODE1 = 1; // from frame buffer |
| 329 | uint8_t POWER_MODE2 = 1; // from frame buffer |
| 330 | uint8_t PACK_TYPE1; // long packet |
| 331 | uint8_t VC1 = 0; |
| 332 | uint8_t DT1 = 0; // non embedded mode |
| 333 | uint8_t WC1 = 0; // for non embedded mode only |
| 334 | int status = 0; |
| 335 | uint8_t DLNx_EN; |
| 336 | |
| 337 | switch (pinfo->num_of_lanes) { |
| 338 | default: |
| 339 | case 1: |
| 340 | DLNx_EN = 1; // 1 lane |
| 341 | break; |
| 342 | case 2: |
| 343 | DLNx_EN = 3; // 2 lane |
| 344 | break; |
| 345 | case 3: |
| 346 | DLNx_EN = 7; // 3 lane |
| 347 | break; |
| 348 | case 4: |
| 349 | DLNx_EN = 0x0F; /* 4 lanes */ |
| 350 | break; |
| 351 | } |
| 352 | |
| 353 | PACK_TYPE1 = pinfo->pack; |
| 354 | |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 355 | if (broadcast) { |
| 356 | writel(0x0001, MIPI_DSI1_BASE + SOFT_RESET); |
| 357 | writel(0x0000, MIPI_DSI1_BASE + SOFT_RESET); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 358 | |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 359 | writel((0 << 16) | 0x3f, MIPI_DSI1_BASE + CLK_CTRL); /* Turn on all DSI Clks */ |
| 360 | writel(DMA_STREAM1 << 8 | 0x04, MIPI_DSI1_BASE + TRIG_CTRL); // reg 0x80 dma trigger: sw |
| 361 | // trigger 0x4; dma stream1 |
| 362 | |
| 363 | writel(0 << 30 | DLNx_EN << 4 | 0x105, MIPI_DSI1_BASE + CTRL); // reg 0x00 for this |
| 364 | // build |
| 365 | writel(broadcast << 31 | EMBED_MODE1 << 28 | POWER_MODE2 << 26 |
| 366 | | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1, |
| 367 | MIPI_DSI1_BASE + COMMAND_MODE_DMA_CTRL); |
| 368 | } |
| 369 | |
| 370 | writel(0x0001, MIPI_DSI0_BASE + SOFT_RESET); |
| 371 | writel(0x0000, MIPI_DSI0_BASE + SOFT_RESET); |
| 372 | |
| 373 | writel((0 << 16) | 0x3f, MIPI_DSI0_BASE + CLK_CTRL); /* Turn on all DSI Clks */ |
| 374 | writel(DMA_STREAM1 << 8 | 0x04, MIPI_DSI0_BASE + TRIG_CTRL); // reg 0x80 dma trigger: sw |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 375 | // trigger 0x4; dma stream1 |
| 376 | |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 377 | writel(0 << 30 | DLNx_EN << 4 | 0x105, MIPI_DSI0_BASE + CTRL); // reg 0x00 for this |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 378 | // build |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 379 | writel(broadcast << 31 | EMBED_MODE1 << 28 | POWER_MODE2 << 26 |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 380 | | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1, |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 381 | MIPI_DSI0_BASE + COMMAND_MODE_DMA_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 382 | |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 383 | if (pinfo->panel_cmds) { |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 384 | |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 385 | if (broadcast) { |
| 386 | status = mdss_dual_dsi_cmds_tx(pinfo->panel_cmds, |
| 387 | pinfo->num_of_panel_cmds); |
| 388 | |
| 389 | } else { |
| 390 | status = mipi_dsi_cmds_tx(pinfo->panel_cmds, |
| 391 | pinfo->num_of_panel_cmds); |
| 392 | } |
| 393 | } |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 394 | return status; |
| 395 | } |
| 396 | |
| 397 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 398 | int mipi_dsi_panel_initialize(struct mipi_dsi_panel_config *pinfo) |
| 399 | { |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 400 | uint8_t DMA_STREAM1 = 0; // for mdp display processor path |
| 401 | uint8_t EMBED_MODE1 = 1; // from frame buffer |
| 402 | uint8_t POWER_MODE2 = 1; // from frame buffer |
| 403 | uint8_t PACK_TYPE1; // long packet |
| 404 | uint8_t VC1 = 0; |
| 405 | uint8_t DT1 = 0; // non embedded mode |
| 406 | uint8_t WC1 = 0; // for non embedded mode only |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 407 | int status = 0; |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 408 | uint8_t DLNx_EN; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 409 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 410 | switch (pinfo->num_of_lanes) { |
| 411 | default: |
| 412 | case 1: |
| 413 | DLNx_EN = 1; // 1 lane |
| 414 | break; |
| 415 | case 2: |
| 416 | DLNx_EN = 3; // 2 lane |
| 417 | break; |
| 418 | case 3: |
| 419 | DLNx_EN = 7; // 3 lane |
| 420 | break; |
Amir Samuelov | 2d4ba16 | 2012-07-22 11:53:14 +0300 | [diff] [blame] | 421 | case 4: |
| 422 | DLNx_EN = 0x0F; /* 4 lanes */ |
| 423 | break; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 424 | } |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 425 | |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 426 | PACK_TYPE1 = pinfo->pack; |
| 427 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 428 | writel(0x0001, DSI_SOFT_RESET); |
| 429 | writel(0x0000, DSI_SOFT_RESET); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 430 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 431 | writel((0 << 16) | 0x3f, DSI_CLK_CTRL); /* Turn on all DSI Clks */ |
| 432 | writel(DMA_STREAM1 << 8 | 0x04, DSI_TRIG_CTRL); // reg 0x80 dma trigger: sw |
| 433 | // trigger 0x4; dma stream1 |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 434 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 435 | writel(0 << 30 | DLNx_EN << 4 | 0x105, DSI_CTRL); // reg 0x00 for this |
| 436 | // build |
| 437 | writel(EMBED_MODE1 << 28 | POWER_MODE2 << 26 |
| 438 | | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1, |
| 439 | DSI_COMMAND_MODE_DMA_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 440 | |
Amir Samuelov | 2d4ba16 | 2012-07-22 11:53:14 +0300 | [diff] [blame] | 441 | if (pinfo->panel_cmds) |
| 442 | status = mipi_dsi_cmds_tx(pinfo->panel_cmds, |
| 443 | pinfo->num_of_panel_cmds); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 444 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 445 | return status; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 446 | } |
| 447 | |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 448 | //TODO: Clean up arguments being passed in not being used |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 449 | int |
| 450 | config_dsi_video_mode(unsigned short disp_width, unsigned short disp_height, |
| 451 | unsigned short img_width, unsigned short img_height, |
| 452 | unsigned short hsync_porch0_fp, |
| 453 | unsigned short hsync_porch0_bp, |
| 454 | unsigned short vsync_porch0_fp, |
| 455 | unsigned short vsync_porch0_bp, |
| 456 | unsigned short hsync_width, |
| 457 | unsigned short vsync_width, unsigned short dst_format, |
| 458 | unsigned short traffic_mode, unsigned short datalane_num) |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 459 | { |
| 460 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 461 | unsigned char DST_FORMAT; |
| 462 | unsigned char TRAFIC_MODE; |
| 463 | unsigned char DLNx_EN; |
| 464 | // video mode data ctrl |
| 465 | int status = 0; |
| 466 | unsigned long low_pwr_stop_mode = 0; |
| 467 | unsigned char eof_bllp_pwr = 0x9; |
| 468 | unsigned char interleav = 0; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 469 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 470 | // disable mdp first |
| 471 | mdp_disable(); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 472 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 473 | writel(0x00000000, DSI_CLK_CTRL); |
| 474 | writel(0x00000000, DSI_CLK_CTRL); |
| 475 | writel(0x00000000, DSI_CLK_CTRL); |
| 476 | writel(0x00000000, DSI_CLK_CTRL); |
| 477 | writel(0x00000002, DSI_CLK_CTRL); |
| 478 | writel(0x00000006, DSI_CLK_CTRL); |
| 479 | writel(0x0000000e, DSI_CLK_CTRL); |
| 480 | writel(0x0000001e, DSI_CLK_CTRL); |
| 481 | writel(0x0000003e, DSI_CLK_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 482 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 483 | writel(0, DSI_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 484 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 485 | writel(0, DSI_ERR_INT_MASK0); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 486 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 487 | DST_FORMAT = 0; // RGB565 |
| 488 | dprintf(SPEW, "DSI_Video_Mode - Dst Format: RGB565\n"); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 489 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 490 | DLNx_EN = 1; // 1 lane with clk programming |
| 491 | dprintf(SPEW, "Data Lane: 1 lane\n"); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 492 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 493 | TRAFIC_MODE = 0; // non burst mode with sync pulses |
| 494 | dprintf(SPEW, "Traffic mode: non burst mode with sync pulses\n"); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 495 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 496 | writel(0x02020202, DSI_INT_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 497 | |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 498 | writel(((hsync_width + img_width + hsync_porch0_bp) << 16) |
| 499 | | (hsync_width + hsync_porch0_bp), |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 500 | DSI_VIDEO_MODE_ACTIVE_H); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 501 | |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 502 | writel(((vsync_width + img_height + vsync_porch0_bp) << 16) |
| 503 | | (vsync_width + vsync_porch0_bp), |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 504 | DSI_VIDEO_MODE_ACTIVE_V); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 505 | |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 506 | writel(((vsync_width + img_height + vsync_porch0_fp + vsync_porch0_bp - 1) << 16) |
| 507 | | (hsync_width + img_width + hsync_porch0_fp + hsync_porch0_bp - 1), |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 508 | DSI_VIDEO_MODE_TOTAL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 509 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 510 | writel((hsync_width << 16) | 0, DSI_VIDEO_MODE_HSYNC); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 511 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 512 | writel(0 << 16 | 0, DSI_VIDEO_MODE_VSYNC); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 513 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 514 | writel(vsync_width << 16 | 0, DSI_VIDEO_MODE_VSYNC_VPOS); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 515 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 516 | writel(1, DSI_EOT_PACKET_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 517 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 518 | writel(0x00000100, DSI_MISR_VIDEO_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 519 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 520 | writel(low_pwr_stop_mode << 16 | eof_bllp_pwr << 12 | TRAFIC_MODE << 8 |
| 521 | | DST_FORMAT << 4 | 0x0, DSI_VIDEO_MODE_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 522 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 523 | writel(0x67, DSI_CAL_STRENGTH_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 524 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 525 | writel(0x80006711, DSI_CAL_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 526 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 527 | writel(0x00010100, DSI_MISR_VIDEO_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 528 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 529 | writel(0x00010100, DSI_INT_CTRL); |
| 530 | writel(0x02010202, DSI_INT_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 531 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 532 | writel(0x02030303, DSI_INT_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 533 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 534 | writel(interleav << 30 | 0 << 24 | 0 << 20 | DLNx_EN << 4 |
| 535 | | 0x103, DSI_CTRL); |
| 536 | mdelay(10); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 537 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 538 | return status; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 539 | } |
| 540 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 541 | int |
| 542 | config_dsi_cmd_mode(unsigned short disp_width, unsigned short disp_height, |
| 543 | unsigned short img_width, unsigned short img_height, |
| 544 | unsigned short dst_format, |
| 545 | unsigned short traffic_mode, unsigned short datalane_num) |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 546 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 547 | unsigned char DST_FORMAT; |
| 548 | unsigned char TRAFIC_MODE; |
| 549 | unsigned char DLNx_EN; |
| 550 | // video mode data ctrl |
| 551 | int status = 0; |
Greg Grisco | d625055 | 2011-06-29 14:40:23 -0700 | [diff] [blame] | 552 | unsigned char interleav = 0; |
| 553 | unsigned char ystride = 0x03; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 554 | // disable mdp first |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 555 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 556 | writel(0x00000000, DSI_CLK_CTRL); |
| 557 | writel(0x00000000, DSI_CLK_CTRL); |
| 558 | writel(0x00000000, DSI_CLK_CTRL); |
| 559 | writel(0x00000000, DSI_CLK_CTRL); |
| 560 | writel(0x00000002, DSI_CLK_CTRL); |
| 561 | writel(0x00000006, DSI_CLK_CTRL); |
| 562 | writel(0x0000000e, DSI_CLK_CTRL); |
| 563 | writel(0x0000001e, DSI_CLK_CTRL); |
| 564 | writel(0x0000003e, DSI_CLK_CTRL); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 565 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 566 | writel(0x10000000, DSI_ERR_INT_MASK0); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 567 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 568 | // writel(0, DSI_CTRL); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 569 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 570 | // writel(0, DSI_ERR_INT_MASK0); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 571 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 572 | DST_FORMAT = 8; // RGB888 |
| 573 | dprintf(SPEW, "DSI_Cmd_Mode - Dst Format: RGB888\n"); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 574 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 575 | DLNx_EN = 3; // 2 lane with clk programming |
| 576 | dprintf(SPEW, "Data Lane: 2 lane\n"); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 577 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 578 | TRAFIC_MODE = 0; // non burst mode with sync pulses |
| 579 | dprintf(SPEW, "Traffic mode: non burst mode with sync pulses\n"); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 580 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 581 | writel(0x02020202, DSI_INT_CTRL); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 582 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 583 | writel(0x00100000 | DST_FORMAT, DSI_COMMAND_MODE_MDP_CTRL); |
| 584 | writel((img_width * ystride + 1) << 16 | 0x0039, |
| 585 | DSI_COMMAND_MODE_MDP_STREAM0_CTRL); |
| 586 | writel((img_width * ystride + 1) << 16 | 0x0039, |
| 587 | DSI_COMMAND_MODE_MDP_STREAM1_CTRL); |
| 588 | writel(img_height << 16 | img_width, |
| 589 | DSI_COMMAND_MODE_MDP_STREAM0_TOTAL); |
| 590 | writel(img_height << 16 | img_width, |
| 591 | DSI_COMMAND_MODE_MDP_STREAM1_TOTAL); |
| 592 | writel(0xEE, DSI_CAL_STRENGTH_CTRL); |
| 593 | writel(0x80000000, DSI_CAL_CTRL); |
| 594 | writel(0x40, DSI_TRIG_CTRL); |
| 595 | writel(0x13c2c, DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL); |
| 596 | writel(interleav << 30 | 0 << 24 | 0 << 20 | DLNx_EN << 4 | 0x105, |
| 597 | DSI_CTRL); |
| 598 | mdelay(10); |
| 599 | writel(0x10000000, DSI_COMMAND_MODE_DMA_CTRL); |
| 600 | writel(0x10000000, DSI_MISR_CMD_CTRL); |
| 601 | writel(0x00000040, DSI_ERR_INT_MASK0); |
| 602 | writel(0x1, DSI_EOT_PACKET_CTRL); |
| 603 | // writel(0x0, MDP_OVERLAYPROC0_START); |
| 604 | mdp_start_dma(); |
| 605 | mdelay(10); |
| 606 | writel(0x1, DSI_CMD_MODE_MDP_SW_TRIGGER); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 607 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 608 | status = 1; |
| 609 | return status; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 610 | } |
| 611 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 612 | int mipi_dsi_video_config(unsigned short num_of_lanes) |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 613 | { |
| 614 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 615 | int status = 0; |
| 616 | unsigned long ReadValue; |
| 617 | unsigned long count = 0; |
| 618 | unsigned long low_pwr_stop_mode = 0; // low power mode 0x1111 start from |
| 619 | // bit16, high spd mode 0x0 |
| 620 | unsigned char eof_bllp_pwr = 0x9; // bit 12, 15, 1:low power stop mode or |
| 621 | // let cmd mode eng send packets in hs |
| 622 | // or lp mode |
| 623 | unsigned short image_wd = mipi_fb_cfg.width; |
| 624 | unsigned short image_ht = mipi_fb_cfg.height; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 625 | unsigned short display_wd = mipi_fb_cfg.width; |
| 626 | unsigned short display_ht = mipi_fb_cfg.height; |
| 627 | unsigned short hsync_porch_fp = MIPI_HSYNC_FRONT_PORCH_DCLK; |
| 628 | unsigned short hsync_porch_bp = MIPI_HSYNC_BACK_PORCH_DCLK; |
| 629 | unsigned short vsync_porch_fp = MIPI_VSYNC_FRONT_PORCH_LINES; |
| 630 | unsigned short vsync_porch_bp = MIPI_VSYNC_BACK_PORCH_LINES; |
| 631 | unsigned short hsync_width = MIPI_HSYNC_PULSE_WIDTH; |
| 632 | unsigned short vsync_width = MIPI_VSYNC_PULSE_WIDTH; |
| 633 | unsigned short dst_format = 0; |
| 634 | unsigned short traffic_mode = 0; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 635 | unsigned short pack_pattern = 0x12; //BGR |
| 636 | unsigned char ystride = 3; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 637 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 638 | low_pwr_stop_mode = 0x1111; // low pwr mode bit16:HSA, bit20:HBA, |
| 639 | // bit24:HFP, bit28:PULSE MODE, need enough |
| 640 | // time for swithc from LP to HS |
| 641 | eof_bllp_pwr = 0x9; // low power stop mode or let cmd mode eng send |
| 642 | // packets in hs or lp mode |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 643 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 644 | status += |
| 645 | config_dsi_video_mode(display_wd, display_ht, image_wd, image_ht, |
| 646 | hsync_porch_fp, hsync_porch_bp, |
| 647 | vsync_porch_fp, vsync_porch_bp, hsync_width, |
| 648 | vsync_width, dst_format, traffic_mode, |
| 649 | num_of_lanes); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 650 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 651 | status += |
| 652 | mdp_setup_dma_p_video_mode(display_wd, display_ht, image_wd, |
| 653 | image_ht, hsync_porch_fp, hsync_porch_bp, |
| 654 | vsync_porch_fp, vsync_porch_bp, |
| 655 | hsync_width, vsync_width, MIPI_FB_ADDR, |
| 656 | image_wd, pack_pattern, ystride); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 657 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 658 | ReadValue = readl(DSI_INT_CTRL) & 0x00010000; |
| 659 | while (ReadValue != 0x00010000) { |
| 660 | ReadValue = readl(DSI_INT_CTRL) & 0x00010000; |
| 661 | count++; |
| 662 | if (count > 0xffff) { |
| 663 | status = FAIL; |
| 664 | dprintf(CRITICAL, "Video lane test failed\n"); |
| 665 | return status; |
| 666 | } |
| 667 | } |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 668 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 669 | dprintf(SPEW, "Video lane tested successfully\n"); |
| 670 | return status; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 671 | } |
| 672 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 673 | int is_cmd_mode_enabled(void) |
| 674 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 675 | return cmd_mode_status; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 676 | } |
| 677 | |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 678 | #if DISPLAY_MIPI_PANEL_NOVATEK_BLUE |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 679 | void mipi_dsi_cmd_mode_trigger(void) |
| 680 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 681 | int status = 0; |
| 682 | unsigned short display_wd = mipi_fb_cfg.width; |
| 683 | unsigned short display_ht = mipi_fb_cfg.height; |
| 684 | unsigned short image_wd = mipi_fb_cfg.width; |
| 685 | unsigned short image_ht = mipi_fb_cfg.height; |
| 686 | unsigned short dst_format = 0; |
| 687 | unsigned short traffic_mode = 0; |
| 688 | struct mipi_dsi_panel_config *panel_info = &novatek_panel_info; |
| 689 | status += mipi_dsi_cmd_config(mipi_fb_cfg, panel_info->num_of_lanes); |
| 690 | mdelay(50); |
| 691 | config_dsi_cmd_mode(display_wd, display_ht, image_wd, image_ht, |
| 692 | dst_format, traffic_mode, |
| 693 | panel_info->num_of_lanes /* num_of_lanes */ ); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 694 | } |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 695 | #endif |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 696 | |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 697 | void mipi_dsi_shutdown(void) |
| 698 | { |
Amol Jadi | 6834f1a | 2012-06-29 14:42:59 -0700 | [diff] [blame] | 699 | if(!target_cont_splash_screen()) |
| 700 | { |
| 701 | mdp_shutdown(); |
| 702 | writel(0x01010101, DSI_INT_CTRL); |
| 703 | writel(0x13FF3BFF, DSI_ERR_INT_MASK0); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 704 | |
| 705 | #if (DISPLAY_MIPI_PANEL_NOVATEK_BLUE \ |
Amol Jadi | 6834f1a | 2012-06-29 14:42:59 -0700 | [diff] [blame] | 706 | || DISPLAY_MIPI_PANEL_TOSHIBA) |
| 707 | secure_writel(0x0, DSI_CC_REG); |
| 708 | secure_writel(0x0, DSI_PIXEL_CC_REG); |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 709 | #endif |
Amol Jadi | 6834f1a | 2012-06-29 14:42:59 -0700 | [diff] [blame] | 710 | |
| 711 | writel(0, DSI_CLK_CTRL); |
| 712 | writel(0, DSI_CTRL); |
| 713 | writel(0, DSIPHY_PLL_CTRL(0)); |
| 714 | } |
| 715 | else |
| 716 | { |
Chandan Uddaraju | 4877d37 | 2011-07-21 12:51:51 -0700 | [diff] [blame] | 717 | /* To keep the splash screen displayed till kernel driver takes |
| 718 | control, do not turn off the video mode engine and clocks. |
| 719 | Only disabling the MIPI DSI IRQs */ |
| 720 | writel(0x01010101, DSI_INT_CTRL); |
| 721 | writel(0x13FF3BFF, DSI_ERR_INT_MASK0); |
Amol Jadi | 6834f1a | 2012-06-29 14:42:59 -0700 | [diff] [blame] | 722 | } |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 723 | } |
| 724 | |
| 725 | struct fbcon_config *mipi_init(void) |
| 726 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 727 | int status = 0; |
| 728 | struct mipi_dsi_panel_config *panel_info = get_panel_info(); |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 729 | |
| 730 | if (panel_info == NULL) { |
| 731 | dprintf(CRITICAL, "Panel info is null\n"); |
| 732 | return NULL; |
| 733 | } |
| 734 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 735 | /* Enable MMSS_AHB_ARB_MATER_PORT_E for arbiter master0 and master 1 request */ |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 736 | #if (!DISPLAY_MIPI_PANEL_RENESAS && !DISPLAY_TYPE_DSI6G) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 737 | writel(0x00001800, MMSS_SFPB_GPREG); |
Aparna Mallavarapu | f712f5e | 2011-08-04 21:11:00 +0530 | [diff] [blame] | 738 | #endif |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 739 | |
| 740 | #if DISPLAY_MIPI_PANEL_TOSHIBA_MDT61 |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 741 | mipi_dsi_phy_init(panel_info); |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 742 | #else |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 743 | mipi_dsi_phy_ctrl_config(panel_info); |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 744 | #endif |
| 745 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 746 | status += mipi_dsi_panel_initialize(panel_info); |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 747 | |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 748 | #if DISPLAY_MIPI_PANEL_NOVATEK_BLUE |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 749 | mipi_dsi_cmd_bta_sw_trigger(); |
| 750 | mipi_novatek_manufacture_id(); |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 751 | #endif |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 752 | mipi_fb_cfg.base = MIPI_FB_ADDR; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 753 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 754 | if (panel_info->mode == MIPI_VIDEO_MODE) |
| 755 | status += mipi_dsi_video_config(panel_info->num_of_lanes); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 756 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 757 | if (panel_info->mode == MIPI_CMD_MODE) |
| 758 | cmd_mode_status = 1; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 759 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 760 | return &mipi_fb_cfg; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 761 | } |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 762 | |
| 763 | int mipi_config(struct msm_fb_panel_data *panel) |
| 764 | { |
| 765 | int ret = NO_ERROR; |
| 766 | struct msm_panel_info *pinfo; |
| 767 | struct mipi_dsi_panel_config mipi_pinfo; |
| 768 | |
| 769 | if (!panel) |
| 770 | return ERR_INVALID_ARGS; |
| 771 | |
| 772 | pinfo = &(panel->panel_info); |
| 773 | mipi_pinfo.mode = pinfo->mipi.mode; |
| 774 | mipi_pinfo.num_of_lanes = pinfo->mipi.num_of_lanes; |
| 775 | mipi_pinfo.dsi_phy_config = pinfo->mipi.dsi_phy_db; |
| 776 | mipi_pinfo.panel_cmds = pinfo->mipi.panel_cmds; |
| 777 | mipi_pinfo.num_of_panel_cmds = pinfo->mipi.num_of_panel_cmds; |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 778 | mipi_pinfo.lane_swap = pinfo->mipi.lane_swap; |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 779 | mipi_pinfo.pack = 1; |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 780 | |
| 781 | /* Enable MMSS_AHB_ARB_MATER_PORT_E for |
| 782 | arbiter master0 and master 1 request */ |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 783 | #if (!DISPLAY_MIPI_PANEL_RENESAS && !DISPLAY_TYPE_DSI6G) |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 784 | writel(0x00001800, MMSS_SFPB_GPREG); |
| 785 | #endif |
| 786 | |
| 787 | mipi_dsi_phy_init(&mipi_pinfo); |
| 788 | |
| 789 | ret += mipi_dsi_panel_initialize(&mipi_pinfo); |
| 790 | |
Channagoud Kadabi | 01c9182 | 2012-06-06 15:53:30 +0530 | [diff] [blame] | 791 | if (pinfo->rotate && panel->rotate) |
| 792 | pinfo->rotate(); |
| 793 | |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 794 | return ret; |
| 795 | } |
| 796 | |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 797 | int mdss_dsi_video_mode_config(uint16_t disp_width, |
| 798 | uint16_t disp_height, |
| 799 | uint16_t img_width, |
| 800 | uint16_t img_height, |
| 801 | uint16_t hsync_porch0_fp, |
| 802 | uint16_t hsync_porch0_bp, |
| 803 | uint16_t vsync_porch0_fp, |
| 804 | uint16_t vsync_porch0_bp, |
| 805 | uint16_t hsync_width, |
| 806 | uint16_t vsync_width, |
| 807 | uint16_t dst_format, |
| 808 | uint16_t traffic_mode, |
| 809 | uint8_t lane_en, |
| 810 | uint16_t low_pwr_stop_mode, |
| 811 | uint8_t eof_bllp_pwr, |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame^] | 812 | uint8_t interleav, |
| 813 | uint32_t ctl_base) |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 814 | { |
| 815 | |
| 816 | int status = 0; |
| 817 | |
| 818 | /* disable mdp first */ |
| 819 | mdp_disable(); |
| 820 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame^] | 821 | writel(0x00000000, ctl_base + CLK_CTRL); |
| 822 | writel(0x00000002, ctl_base + CLK_CTRL); |
| 823 | writel(0x00000006, ctl_base + CLK_CTRL); |
| 824 | writel(0x0000000e, ctl_base + CLK_CTRL); |
| 825 | writel(0x0000001e, ctl_base + CLK_CTRL); |
| 826 | writel(0x0000023f, ctl_base + CLK_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 827 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame^] | 828 | writel(0, ctl_base + CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 829 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame^] | 830 | writel(0, ctl_base + DSI_ERR_INT_MASK0); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 831 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame^] | 832 | writel(0x02020202, ctl_base + INT_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 833 | |
| 834 | writel(((disp_width + hsync_porch0_bp) << 16) | hsync_porch0_bp, |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame^] | 835 | ctl_base + VIDEO_MODE_ACTIVE_H); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 836 | |
| 837 | writel(((disp_height + vsync_porch0_bp) << 16) | (vsync_porch0_bp), |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame^] | 838 | ctl_base + VIDEO_MODE_ACTIVE_V); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 839 | |
| 840 | if (mdp_get_revision() >= MDP_REV_41) { |
| 841 | writel(((disp_height + vsync_porch0_fp |
| 842 | + vsync_porch0_bp - 1) << 16) |
| 843 | | (disp_width + hsync_porch0_fp |
| 844 | + hsync_porch0_bp - 1), |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame^] | 845 | ctl_base + VIDEO_MODE_TOTAL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 846 | } else { |
| 847 | writel(((disp_height + vsync_porch0_fp |
| 848 | + vsync_porch0_bp) << 16) |
| 849 | | (disp_width + hsync_porch0_fp |
| 850 | + hsync_porch0_bp), |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame^] | 851 | ctl_base + VIDEO_MODE_TOTAL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 852 | } |
| 853 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame^] | 854 | writel((hsync_width << 16) | 0, ctl_base + VIDEO_MODE_HSYNC); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 855 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame^] | 856 | writel(0 << 16 | 0, ctl_base + VIDEO_MODE_VSYNC); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 857 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame^] | 858 | writel(vsync_width << 16 | 0, ctl_base + VIDEO_MODE_VSYNC_VPOS); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 859 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame^] | 860 | writel(0x0, ctl_base + EOT_PACKET_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 861 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame^] | 862 | writel(0x00000100, ctl_base + MISR_VIDEO_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 863 | |
| 864 | if (mdp_get_revision() >= MDP_REV_41) { |
| 865 | writel(low_pwr_stop_mode << 16 | |
| 866 | eof_bllp_pwr << 12 | traffic_mode << 8 |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame^] | 867 | | dst_format << 4 | 0x0, ctl_base + VIDEO_MODE_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 868 | } else { |
| 869 | writel(1 << 28 | 1 << 24 | 1 << 20 | low_pwr_stop_mode << 16 | |
| 870 | eof_bllp_pwr << 12 | traffic_mode << 8 |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame^] | 871 | | dst_format << 4 | 0x0, ctl_base + VIDEO_MODE_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 872 | } |
| 873 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame^] | 874 | writel(0x3fd08, ctl_base + HS_TIMER_CTRL); |
| 875 | writel(0x00010100, ctl_base + MISR_VIDEO_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 876 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame^] | 877 | writel(0x00010100, ctl_base + INT_CTRL); |
| 878 | writel(0x02010202, ctl_base + INT_CTRL); |
| 879 | writel(0x02030303, ctl_base + INT_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 880 | |
| 881 | writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4 |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame^] | 882 | | 0x103, ctl_base + CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 883 | |
| 884 | return status; |
| 885 | } |
| 886 | |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 887 | int mdss_dsi_config(struct msm_fb_panel_data *panel) |
| 888 | { |
| 889 | int ret = NO_ERROR; |
| 890 | struct msm_panel_info *pinfo; |
| 891 | struct mipi_dsi_panel_config mipi_pinfo; |
| 892 | |
| 893 | if (!panel) |
| 894 | return ERR_INVALID_ARGS; |
| 895 | |
| 896 | pinfo = &(panel->panel_info); |
| 897 | mipi_pinfo.mode = pinfo->mipi.mode; |
| 898 | mipi_pinfo.num_of_lanes = pinfo->mipi.num_of_lanes; |
| 899 | mipi_pinfo.mdss_dsi_phy_config = pinfo->mipi.mdss_dsi_phy_db; |
| 900 | mipi_pinfo.panel_cmds = pinfo->mipi.panel_cmds; |
| 901 | mipi_pinfo.num_of_panel_cmds = pinfo->mipi.num_of_panel_cmds; |
| 902 | mipi_pinfo.lane_swap = pinfo->mipi.lane_swap; |
| 903 | mipi_pinfo.pack = 0; |
| 904 | |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 905 | mdss_dsi_phy_init(&mipi_pinfo, MIPI_DSI0_BASE); |
| 906 | if (pinfo->mipi.dual_dsi) |
| 907 | mdss_dsi_phy_init(&mipi_pinfo, MIPI_DSI1_BASE); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 908 | |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 909 | ret += mdss_dsi_panel_initialize(&mipi_pinfo, pinfo->mipi.broadcast); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 910 | |
| 911 | if (pinfo->rotate && panel->rotate) |
| 912 | pinfo->rotate(); |
| 913 | |
| 914 | return ret; |
| 915 | } |
| 916 | |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 917 | int mipi_dsi_video_mode_config(unsigned short disp_width, |
| 918 | unsigned short disp_height, |
| 919 | unsigned short img_width, |
| 920 | unsigned short img_height, |
| 921 | unsigned short hsync_porch0_fp, |
| 922 | unsigned short hsync_porch0_bp, |
| 923 | unsigned short vsync_porch0_fp, |
| 924 | unsigned short vsync_porch0_bp, |
| 925 | unsigned short hsync_width, |
| 926 | unsigned short vsync_width, |
| 927 | unsigned short dst_format, |
| 928 | unsigned short traffic_mode, |
| 929 | unsigned char lane_en, |
| 930 | unsigned low_pwr_stop_mode, |
| 931 | unsigned char eof_bllp_pwr, |
| 932 | unsigned char interleav) |
| 933 | { |
| 934 | |
| 935 | int status = 0; |
| 936 | |
| 937 | /* disable mdp first */ |
| 938 | mdp_disable(); |
| 939 | |
| 940 | writel(0x00000000, DSI_CLK_CTRL); |
| 941 | writel(0x00000000, DSI_CLK_CTRL); |
| 942 | writel(0x00000000, DSI_CLK_CTRL); |
| 943 | writel(0x00000000, DSI_CLK_CTRL); |
| 944 | writel(0x00000002, DSI_CLK_CTRL); |
| 945 | writel(0x00000006, DSI_CLK_CTRL); |
| 946 | writel(0x0000000e, DSI_CLK_CTRL); |
| 947 | writel(0x0000001e, DSI_CLK_CTRL); |
Chandan Uddaraju | eb1decb | 2013-04-23 14:27:49 -0700 | [diff] [blame] | 948 | writel(0x0000023f, DSI_CLK_CTRL); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 949 | |
| 950 | writel(0, DSI_CTRL); |
| 951 | |
| 952 | writel(0, DSI_ERR_INT_MASK0); |
| 953 | |
| 954 | writel(0x02020202, DSI_INT_CTRL); |
| 955 | |
| 956 | writel(((disp_width + hsync_porch0_bp) << 16) | hsync_porch0_bp, |
| 957 | DSI_VIDEO_MODE_ACTIVE_H); |
| 958 | |
| 959 | writel(((disp_height + vsync_porch0_bp) << 16) | (vsync_porch0_bp), |
| 960 | DSI_VIDEO_MODE_ACTIVE_V); |
| 961 | |
| 962 | if (mdp_get_revision() >= MDP_REV_41) { |
| 963 | writel(((disp_height + vsync_porch0_fp |
| 964 | + vsync_porch0_bp - 1) << 16) |
| 965 | | (disp_width + hsync_porch0_fp |
| 966 | + hsync_porch0_bp - 1), |
| 967 | DSI_VIDEO_MODE_TOTAL); |
| 968 | } else { |
| 969 | writel(((disp_height + vsync_porch0_fp |
| 970 | + vsync_porch0_bp) << 16) |
| 971 | | (disp_width + hsync_porch0_fp |
| 972 | + hsync_porch0_bp), |
| 973 | DSI_VIDEO_MODE_TOTAL); |
| 974 | } |
| 975 | |
| 976 | writel((hsync_width << 16) | 0, DSI_VIDEO_MODE_HSYNC); |
| 977 | |
| 978 | writel(0 << 16 | 0, DSI_VIDEO_MODE_VSYNC); |
| 979 | |
| 980 | writel(vsync_width << 16 | 0, DSI_VIDEO_MODE_VSYNC_VPOS); |
| 981 | |
Chandan Uddaraju | eb1decb | 2013-04-23 14:27:49 -0700 | [diff] [blame] | 982 | writel(0x0, DSI_EOT_PACKET_CTRL); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 983 | |
| 984 | writel(0x00000100, DSI_MISR_VIDEO_CTRL); |
| 985 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 986 | if (mdp_get_revision() >= MDP_REV_41) { |
| 987 | writel(low_pwr_stop_mode << 16 | |
| 988 | eof_bllp_pwr << 12 | traffic_mode << 8 |
| 989 | | dst_format << 4 | 0x0, DSI_VIDEO_MODE_CTRL); |
| 990 | } else { |
| 991 | writel(1 << 28 | 1 << 24 | 1 << 20 | low_pwr_stop_mode << 16 | |
| 992 | eof_bllp_pwr << 12 | traffic_mode << 8 |
| 993 | | dst_format << 4 | 0x0, DSI_VIDEO_MODE_CTRL); |
| 994 | } |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 995 | |
Chandan Uddaraju | eb1decb | 2013-04-23 14:27:49 -0700 | [diff] [blame] | 996 | writel(0x3fd08, DSI_HS_TIMER_CTRL); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 997 | writel(0x67, DSI_CAL_STRENGTH_CTRL); |
| 998 | writel(0x80006711, DSI_CAL_CTRL); |
| 999 | writel(0x00010100, DSI_MISR_VIDEO_CTRL); |
| 1000 | |
| 1001 | writel(0x00010100, DSI_INT_CTRL); |
| 1002 | writel(0x02010202, DSI_INT_CTRL); |
| 1003 | writel(0x02030303, DSI_INT_CTRL); |
| 1004 | |
| 1005 | writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4 |
| 1006 | | 0x103, DSI_CTRL); |
| 1007 | |
| 1008 | return status; |
| 1009 | } |
| 1010 | |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 1011 | int mdss_dsi_cmd_mode_config(uint16_t disp_width, |
| 1012 | uint16_t disp_height, |
| 1013 | uint16_t img_width, |
| 1014 | uint16_t img_height, |
| 1015 | uint16_t dst_format, |
| 1016 | uint16_t traffic_mode) |
| 1017 | { |
| 1018 | uint8_t DST_FORMAT; |
| 1019 | uint8_t TRAFIC_MODE; |
| 1020 | uint8_t DLNx_EN; |
| 1021 | // video mode data ctrl |
| 1022 | int status = 0; |
| 1023 | uint8_t interleav = 0; |
| 1024 | uint8_t ystride = 0x03; |
| 1025 | // disable mdp first |
| 1026 | |
| 1027 | writel(0x00000000, DSI_CLK_CTRL); |
| 1028 | writel(0x00000000, DSI_CLK_CTRL); |
| 1029 | writel(0x00000000, DSI_CLK_CTRL); |
| 1030 | writel(0x00000000, DSI_CLK_CTRL); |
| 1031 | writel(0x00000002, DSI_CLK_CTRL); |
| 1032 | writel(0x00000006, DSI_CLK_CTRL); |
| 1033 | writel(0x0000000e, DSI_CLK_CTRL); |
| 1034 | writel(0x0000001e, DSI_CLK_CTRL); |
| 1035 | writel(0x0000023f, DSI_CLK_CTRL); |
| 1036 | |
| 1037 | writel(0, DSI_CTRL); |
| 1038 | |
| 1039 | writel(0, DSI_ERR_INT_MASK0); |
| 1040 | |
| 1041 | writel(0x02020202, DSI_INT_CTRL); |
| 1042 | |
| 1043 | DST_FORMAT = 8; // RGB888 |
| 1044 | dprintf(SPEW, "DSI_Cmd_Mode - Dst Format: RGB888\n"); |
| 1045 | |
| 1046 | DLNx_EN = 0xf; // 4 lane with clk programming |
| 1047 | dprintf(SPEW, "Data Lane: 4 lane\n"); |
| 1048 | |
| 1049 | TRAFIC_MODE = 0; // non burst mode with sync pulses |
| 1050 | dprintf(SPEW, "Traffic mode: non burst mode with sync pulses\n"); |
| 1051 | |
| 1052 | writel(DST_FORMAT, DSI_COMMAND_MODE_MDP_CTRL); |
| 1053 | writel((img_width * ystride + 1) << 16 | 0x0039, |
| 1054 | DSI_COMMAND_MODE_MDP_STREAM0_CTRL); |
| 1055 | writel((img_width * ystride + 1) << 16 | 0x0039, |
| 1056 | DSI_COMMAND_MODE_MDP_STREAM1_CTRL); |
| 1057 | writel(img_height << 16 | img_width, |
| 1058 | DSI_COMMAND_MODE_MDP_STREAM0_TOTAL); |
| 1059 | writel(img_height << 16 | img_width, |
| 1060 | DSI_COMMAND_MODE_MDP_STREAM1_TOTAL); |
| 1061 | writel(0x13c2c, DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL); |
| 1062 | writel(interleav << 30 | 0 << 24 | 0 << 20 | DLNx_EN << 4 | 0x105, |
| 1063 | DSI_CTRL); |
| 1064 | writel(0x10000000, DSI_COMMAND_MODE_DMA_CTRL); |
| 1065 | writel(0x10000000, DSI_MISR_CMD_CTRL); |
| 1066 | |
| 1067 | return NO_ERROR; |
| 1068 | } |
| 1069 | |
Channagoud Kadabi | 10189fd | 2012-05-25 13:33:39 +0530 | [diff] [blame] | 1070 | int mipi_dsi_cmd_mode_config(unsigned short disp_width, |
| 1071 | unsigned short disp_height, |
| 1072 | unsigned short img_width, |
| 1073 | unsigned short img_height, |
| 1074 | unsigned short dst_format, |
| 1075 | unsigned short traffic_mode) |
| 1076 | { |
| 1077 | unsigned char DST_FORMAT; |
| 1078 | unsigned char TRAFIC_MODE; |
| 1079 | unsigned char DLNx_EN; |
| 1080 | // video mode data ctrl |
| 1081 | int status = 0; |
| 1082 | unsigned char interleav = 0; |
| 1083 | unsigned char ystride = 0x03; |
| 1084 | // disable mdp first |
| 1085 | |
| 1086 | writel(0x00000000, DSI_CLK_CTRL); |
| 1087 | writel(0x00000000, DSI_CLK_CTRL); |
| 1088 | writel(0x00000000, DSI_CLK_CTRL); |
| 1089 | writel(0x00000000, DSI_CLK_CTRL); |
| 1090 | writel(0x00000002, DSI_CLK_CTRL); |
| 1091 | writel(0x00000006, DSI_CLK_CTRL); |
| 1092 | writel(0x0000000e, DSI_CLK_CTRL); |
| 1093 | writel(0x0000001e, DSI_CLK_CTRL); |
| 1094 | writel(0x0000003e, DSI_CLK_CTRL); |
| 1095 | |
| 1096 | writel(0x10000000, DSI_ERR_INT_MASK0); |
| 1097 | |
| 1098 | |
| 1099 | DST_FORMAT = 8; // RGB888 |
| 1100 | dprintf(SPEW, "DSI_Cmd_Mode - Dst Format: RGB888\n"); |
| 1101 | |
| 1102 | DLNx_EN = 3; // 2 lane with clk programming |
| 1103 | dprintf(SPEW, "Data Lane: 2 lane\n"); |
| 1104 | |
| 1105 | TRAFIC_MODE = 0; // non burst mode with sync pulses |
| 1106 | dprintf(SPEW, "Traffic mode: non burst mode with sync pulses\n"); |
| 1107 | |
| 1108 | writel(0x02020202, DSI_INT_CTRL); |
| 1109 | |
| 1110 | writel(0x00100000 | DST_FORMAT, DSI_COMMAND_MODE_MDP_CTRL); |
| 1111 | writel((img_width * ystride + 1) << 16 | 0x0039, |
| 1112 | DSI_COMMAND_MODE_MDP_STREAM0_CTRL); |
| 1113 | writel((img_width * ystride + 1) << 16 | 0x0039, |
| 1114 | DSI_COMMAND_MODE_MDP_STREAM1_CTRL); |
| 1115 | writel(img_height << 16 | img_width, |
| 1116 | DSI_COMMAND_MODE_MDP_STREAM0_TOTAL); |
| 1117 | writel(img_height << 16 | img_width, |
| 1118 | DSI_COMMAND_MODE_MDP_STREAM1_TOTAL); |
| 1119 | writel(0xEE, DSI_CAL_STRENGTH_CTRL); |
| 1120 | writel(0x80000000, DSI_CAL_CTRL); |
| 1121 | writel(0x40, DSI_TRIG_CTRL); |
| 1122 | writel(0x13c2c, DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL); |
| 1123 | writel(interleav << 30 | 0 << 24 | 0 << 20 | DLNx_EN << 4 | 0x105, |
| 1124 | DSI_CTRL); |
| 1125 | writel(0x10000000, DSI_COMMAND_MODE_DMA_CTRL); |
| 1126 | writel(0x10000000, DSI_MISR_CMD_CTRL); |
| 1127 | writel(0x00000040, DSI_ERR_INT_MASK0); |
| 1128 | writel(0x1, DSI_EOT_PACKET_CTRL); |
| 1129 | |
| 1130 | return NO_ERROR; |
| 1131 | } |
| 1132 | |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 1133 | int mipi_dsi_on() |
| 1134 | { |
| 1135 | int ret = NO_ERROR; |
| 1136 | unsigned long ReadValue; |
| 1137 | unsigned long count = 0; |
| 1138 | |
| 1139 | ReadValue = readl(DSI_INT_CTRL) & 0x00010000; |
| 1140 | |
| 1141 | mdelay(10); |
| 1142 | |
| 1143 | while (ReadValue != 0x00010000) { |
| 1144 | ReadValue = readl(DSI_INT_CTRL) & 0x00010000; |
| 1145 | count++; |
| 1146 | if (count > 0xffff) { |
| 1147 | dprintf(CRITICAL, "Video lane test failed\n"); |
| 1148 | return ERROR; |
| 1149 | } |
| 1150 | } |
| 1151 | |
Amir Samuelov | 2d4ba16 | 2012-07-22 11:53:14 +0300 | [diff] [blame] | 1152 | dprintf(INFO, "Video lane tested successfully\n"); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 1153 | return ret; |
| 1154 | } |
| 1155 | |
| 1156 | int mipi_dsi_off() |
| 1157 | { |
Amol Jadi | 6834f1a | 2012-06-29 14:42:59 -0700 | [diff] [blame] | 1158 | if(!target_cont_splash_screen()) |
| 1159 | { |
| 1160 | writel(0, DSI_CLK_CTRL); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 1161 | writel(0x1F1, DSI_CTRL); |
| 1162 | writel(0x00000001, DSIPHY_SW_RESET); |
| 1163 | writel(0x00000000, DSIPHY_SW_RESET); |
| 1164 | mdelay(10); |
| 1165 | writel(0x0001, DSI_SOFT_RESET); |
| 1166 | writel(0x0000, DSI_SOFT_RESET); |
Siddhartha Agrawal | e0033a1 | 2013-02-23 15:37:42 -0800 | [diff] [blame] | 1167 | writel(0x1115501, DSI_INT_CTRL); |
Amol Jadi | 6834f1a | 2012-06-29 14:42:59 -0700 | [diff] [blame] | 1168 | writel(0, DSI_CTRL); |
Siddhartha Agrawal | e0033a1 | 2013-02-23 15:37:42 -0800 | [diff] [blame] | 1169 | } |
| 1170 | |
| 1171 | writel(0x1115501, DSI_INT_CTRL); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 1172 | |
| 1173 | return NO_ERROR; |
| 1174 | } |
Channagoud Kadabi | 10189fd | 2012-05-25 13:33:39 +0530 | [diff] [blame] | 1175 | |
| 1176 | int mipi_cmd_trigger() |
| 1177 | { |
| 1178 | writel(0x1, DSI_CMD_MODE_MDP_SW_TRIGGER); |
| 1179 | |
| 1180 | return NO_ERROR; |
| 1181 | } |