Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2008, Google Inc. |
| 3 | * All rights reserved. |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 4 | * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved. |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 5 | * |
| 6 | * Redistribution and use in source and binary forms, with or without |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 7 | * modification, are permitted provided that the following conditions are |
| 8 | * met: |
| 9 | * * Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer. |
| 11 | * * Redistributions in binary form must reproduce the above |
| 12 | * copyright notice, this list of conditions and the following |
| 13 | * disclaimer in the documentation and/or other materials provided |
| 14 | * with the distribution. |
| 15 | * * Neither the name of The Linux Foundation nor the names of its |
| 16 | * contributors may be used to endorse or promote products derived |
| 17 | * from this software without specific prior written permission. |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 18 | * |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 19 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 20 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 23 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 26 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 27 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 28 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 29 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 30 | */ |
| 31 | |
| 32 | #include <stdint.h> |
| 33 | #include <kernel/thread.h> |
| 34 | #include <platform/iomap.h> |
| 35 | #include <reg.h> |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 36 | #include <smem.h> |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 37 | #include <debug.h> |
| 38 | #include <mmc.h> |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 39 | |
| 40 | #define ARRAY_SIZE(x) (sizeof(x)/sizeof((x)[0])) |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 41 | #define BIT(x) (1 << (x)) |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 42 | |
| 43 | #define A11S_CLK_CNTL_ADDR (MSM_CSR_BASE + 0x100) |
| 44 | #define A11S_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104) |
| 45 | #define VDD_SVS_PLEVEL_ADDR (MSM_CSR_BASE + 0x124) |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 46 | |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 47 | #define PLL2_MODE_ADDR (MSM_CLK_CTL_BASE + 0x338) |
| 48 | #define PLL4_MODE_ADDR (MSM_CLK_CTL_BASE + 0x374) |
| 49 | |
| 50 | #define PLL_RESET_N BIT(2) |
| 51 | #define PLL_BYPASSNL BIT(1) |
| 52 | #define PLL_OUTCTRL BIT(0) |
| 53 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 54 | #define SRC_SEL_TCX0 0 /* TCXO */ |
| 55 | #define SRC_SEL_PLL1 1 /* PLL1: modem_pll */ |
| 56 | #define SRC_SEL_PLL2 2 /* PLL2: backup_pll_0 */ |
| 57 | #define SRC_SEL_PLL3 3 /* PLL3: backup_pll_1 */ |
| 58 | #define SRC_SEL_PLL4 6 /* PLL4: sparrow_pll */ |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 59 | |
| 60 | #define DIV_1 0 |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 61 | #define DIV_2 1 |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 62 | #define DIV_3 2 |
| 63 | #define DIV_4 3 |
| 64 | #define DIV_5 4 |
| 65 | #define DIV_6 5 |
| 66 | #define DIV_7 6 |
| 67 | #define DIV_8 7 |
| 68 | #define DIV_9 8 |
| 69 | #define DIV_10 9 |
| 70 | #define DIV_11 10 |
| 71 | #define DIV_12 11 |
| 72 | #define DIV_13 12 |
| 73 | #define DIV_14 13 |
| 74 | #define DIV_15 14 |
| 75 | #define DIV_16 15 |
| 76 | |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 77 | #define WAIT_CNT 100 |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 78 | #define MIN_AXI_HZ 120000000 |
| 79 | #define ACPU_800MHZ 41 |
| 80 | |
Channagoud Kadabi | c0b0a36 | 2012-04-19 13:37:25 +0530 | [diff] [blame] | 81 | #define A11S_CLK_SEL_MASK 0x1 /* bits 2:0 */ |
Shashank Mittal | 302a633 | 2011-05-04 10:32:48 -0700 | [diff] [blame] | 82 | |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 83 | /* The stepping frequencies have been choosen to make sure the step |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 84 | * is <= 256 MHz for both 7x27a and 7x25a targets. The |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 85 | * table also assumes the ACPU is running at TCXO freq and AHB div is |
| 86 | * set to DIV_1. |
| 87 | * |
| 88 | * To use the tables: |
| 89 | * - Start at location 0/1 depending on clock source sel bit. |
| 90 | * - Set values till end of table skipping every other entry. |
| 91 | * - When you reach the end of the table, you are done scaling. |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 92 | */ |
| 93 | |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 94 | uint32_t const clk_cntl_reg_val_7627A[] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 95 | (WAIT_CNT << 16) | (SRC_SEL_PLL2 << 4) | DIV_16, |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 96 | (WAIT_CNT << 16) | (SRC_SEL_PLL2 << 12) | (DIV_8 << 8), |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 97 | (WAIT_CNT << 16) | (SRC_SEL_PLL2 << 4) | DIV_4, |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 98 | (WAIT_CNT << 16) | (SRC_SEL_PLL2 << 12) | (DIV_2 << 8), |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 99 | |
| 100 | /* TODO: Fix it for 800MHz */ |
| 101 | #if 0 |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 102 | (WAIT_CNT << 16) | (SRC_SEL_PLL4 << 4) | DIV_1, |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 103 | #endif |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 104 | }; |
| 105 | |
Channagoud Kadabi | 3acfb74 | 2011-11-15 18:19:32 +0530 | [diff] [blame] | 106 | /* |
| 107 | * Use PLL4 to run acpu @ 1.2 GHZ |
| 108 | */ |
| 109 | uint32_t const clk_cntl_reg_val_8X25[] = { |
| 110 | (WAIT_CNT << 16) | (SRC_SEL_PLL4 << 4) | DIV_2, |
| 111 | (WAIT_CNT << 16) | (SRC_SEL_PLL4 << 12) | (DIV_1 << 8), |
| 112 | }; |
| 113 | |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 114 | uint32_t const clk_cntl_reg_val_7625A[] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 115 | (WAIT_CNT << 16) | (SRC_SEL_PLL2 << 4) | DIV_16, |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 116 | (WAIT_CNT << 16) | (SRC_SEL_PLL2 << 12) | (DIV_8 << 8), |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 117 | (WAIT_CNT << 16) | (SRC_SEL_PLL2 << 4) | DIV_4, |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 118 | (WAIT_CNT << 16) | (SRC_SEL_PLL2 << 12) | (DIV_2 << 8), |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 119 | }; |
| 120 | |
Shashank Mittal | 302a633 | 2011-05-04 10:32:48 -0700 | [diff] [blame] | 121 | /* Using DIV_1 for all cases to avoid worrying about turbo vs. normal |
| 122 | * mode. Able to use DIV_1 for all steps because it's the largest AND |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 123 | * the final value. */ |
| 124 | uint32_t const clk_sel_reg_val[] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 125 | DIV_1 << 1 | 1, /* Switch to src1 */ |
| 126 | DIV_1 << 1 | 0, /* Switch to src0 */ |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 127 | }; |
| 128 | |
| 129 | /* |
| 130 | * Mask to make sure current selected src frequency doesn't change. |
| 131 | */ |
| 132 | uint32_t const clk_cntl_mask[] = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 133 | 0x0000FF00, /* Mask to read src0 */ |
| 134 | 0x000000FF /* Mask to read src1 */ |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 135 | }; |
| 136 | |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 137 | /* enum for SDC CLK IDs */ |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 138 | enum { |
| 139 | SDC1_CLK = 19, |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 140 | SDC1_PCLK = 20, |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 141 | SDC2_CLK = 21, |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 142 | SDC2_PCLK = 22, |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 143 | SDC3_CLK = 23, |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 144 | SDC3_PCLK = 24, |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 145 | SDC4_CLK = 25, |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 146 | SDC4_PCLK = 26 |
| 147 | }; |
| 148 | |
| 149 | /* Zero'th entry is dummy */ |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 150 | static uint8_t sdc_clk[] = { 0, SDC1_CLK, SDC2_CLK, SDC3_CLK, SDC4_CLK }; |
| 151 | static uint8_t sdc_pclk[] = { 0, SDC1_PCLK, SDC2_PCLK, SDC3_PCLK, SDC4_PCLK }; |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 152 | |
Aparna Mallavarapu | c1eb99b | 2012-09-24 20:13:42 +0530 | [diff] [blame] | 153 | /* VDD_PLEVEL */ |
| 154 | unsigned vdd_plevel = 0; |
| 155 | |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 156 | void mdelay(unsigned msecs); |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 157 | unsigned board_msm_id(void); |
Aparna Mallavarapu | c1eb99b | 2012-09-24 20:13:42 +0530 | [diff] [blame] | 158 | unsigned board_msm_version(void); |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 159 | |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 160 | void pll_enable(void *pll_mode_addr) |
| 161 | { |
| 162 | /* TODO: Need to add spin-lock to avoid race conditions */ |
| 163 | |
| 164 | uint32_t nVal; |
| 165 | /* Check status */ |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 166 | nVal = readl(pll_mode_addr); |
| 167 | if (nVal & PLL_OUTCTRL) |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 168 | return; |
| 169 | |
| 170 | /* Put the PLL in reset mode */ |
| 171 | nVal = 0; |
| 172 | nVal &= ~PLL_RESET_N; |
| 173 | nVal &= ~PLL_BYPASSNL; |
| 174 | nVal &= ~PLL_OUTCTRL; |
| 175 | writel(nVal, pll_mode_addr); |
| 176 | |
| 177 | /* Put the PLL in warm-up mode */ |
| 178 | nVal |= PLL_RESET_N; |
| 179 | nVal |= PLL_BYPASSNL; |
| 180 | writel(nVal, pll_mode_addr); |
| 181 | |
| 182 | /* Wait for the PLL warm-up time */ |
| 183 | udelay(50); |
| 184 | |
| 185 | /* Put the PLL in active mode */ |
| 186 | nVal |= PLL_RESET_N; |
| 187 | nVal |= PLL_BYPASSNL; |
| 188 | nVal |= PLL_OUTCTRL; |
| 189 | writel(nVal, pll_mode_addr); |
| 190 | } |
| 191 | |
| 192 | void pll_request(unsigned pll, unsigned enable) |
| 193 | { |
| 194 | int val = 0; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 195 | if (!enable) { |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 196 | /* Disable not supported */ |
| 197 | return; |
| 198 | } |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 199 | switch (pll) { |
| 200 | case 2: |
| 201 | pll_enable(PLL2_MODE_ADDR); |
| 202 | return; |
| 203 | case 4: |
| 204 | pll_enable(PLL4_MODE_ADDR); |
| 205 | return; |
| 206 | default: |
| 207 | return; |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 208 | }; |
| 209 | } |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 210 | |
| 211 | void acpu_clock_init(void) |
| 212 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 213 | uint32_t i, clk; |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 214 | uint32_t val; |
| 215 | uint32_t *clk_cntl_reg_val, size; |
Aparna Mallavarapu | c1eb99b | 2012-09-24 20:13:42 +0530 | [diff] [blame] | 216 | unsigned msm_id, msm_version; |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 217 | |
Aparna Mallavarapu | c1eb99b | 2012-09-24 20:13:42 +0530 | [diff] [blame] | 218 | msm_version = board_msm_version(); |
| 219 | if (msm_version == 2) |
| 220 | vdd_plevel = 4; |
| 221 | else |
| 222 | vdd_plevel = 6; |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 223 | |
Aparna Mallavarapu | c1eb99b | 2012-09-24 20:13:42 +0530 | [diff] [blame] | 224 | /* Set VDD plevel */ |
| 225 | writel((1 << 7) | (vdd_plevel << 3), VDD_SVS_PLEVEL_ADDR); |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 226 | #if (!ENABLE_NANDWRITE) |
| 227 | thread_sleep(1); |
| 228 | #else |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 229 | mdelay(1); |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 230 | #endif |
| 231 | |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 232 | msm_id = board_msm_id(); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 233 | switch (msm_id) { |
| 234 | case MSM7227A: |
| 235 | case MSM7627A: |
| 236 | case ESM7227A: |
| 237 | clk_cntl_reg_val = clk_cntl_reg_val_7627A; |
| 238 | size = ARRAY_SIZE(clk_cntl_reg_val_7627A); |
| 239 | pll_request(2, 1); |
Shashank Mittal | 5d564b6 | 2011-05-12 10:51:07 -0700 | [diff] [blame] | 240 | |
| 241 | /* TODO: Enable this PLL while switching to 800MHz */ |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 242 | #if 0 |
| 243 | pll_request(4, 1); |
| 244 | #endif |
| 245 | break; |
Channagoud Kadabi | 3acfb74 | 2011-11-15 18:19:32 +0530 | [diff] [blame] | 246 | case MSM8625: |
| 247 | /* Fix me: Will move to PLL4 later */ |
| 248 | clk_cntl_reg_val = clk_cntl_reg_val_7627A; |
| 249 | size = ARRAY_SIZE(clk_cntl_reg_val_7627A); |
| 250 | pll_request(2, 1); |
| 251 | break; |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 252 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 253 | case MSM7225A: |
| 254 | case MSM7625A: |
| 255 | default: |
| 256 | clk_cntl_reg_val = clk_cntl_reg_val_7625A; |
| 257 | size = ARRAY_SIZE(clk_cntl_reg_val_7625A); |
| 258 | pll_request(2, 1); |
| 259 | break; |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 260 | }; |
| 261 | |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 262 | /* Read clock source select bit. */ |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 263 | val = readl(A11S_CLK_SEL_ADDR); |
| 264 | i = val & 1; |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 265 | |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 266 | /* Jump into table and set every entry. */ |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 267 | for (; i < size; i++) { |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 268 | |
Channagoud Kadabi | c0b0a36 | 2012-04-19 13:37:25 +0530 | [diff] [blame] | 269 | val = readl(A11S_CLK_SEL_ADDR); |
| 270 | val |= BIT(1) | BIT(2); |
| 271 | writel(val, A11S_CLK_SEL_ADDR); |
| 272 | |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 273 | val = readl(A11S_CLK_CNTL_ADDR); |
| 274 | |
| 275 | /* Make sure not to disturb already used src */ |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 276 | val &= clk_cntl_mask[i % 2]; |
Shashank Mittal | 8397844 | 2011-04-01 19:41:22 -0700 | [diff] [blame] | 277 | val += clk_cntl_reg_val[i]; |
| 278 | writel(val, A11S_CLK_CNTL_ADDR); |
| 279 | |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 280 | /* Would need a dmb() here but the whole address space is |
| 281 | * strongly ordered, so it should be fine. |
| 282 | */ |
Shashank Mittal | 302a633 | 2011-05-04 10:32:48 -0700 | [diff] [blame] | 283 | val = readl(A11S_CLK_SEL_ADDR); |
| 284 | val &= ~(A11S_CLK_SEL_MASK); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 285 | val |= (A11S_CLK_SEL_MASK & clk_sel_reg_val[i % 2]); |
Shashank Mittal | 302a633 | 2011-05-04 10:32:48 -0700 | [diff] [blame] | 286 | writel(val, A11S_CLK_SEL_ADDR); |
| 287 | |
Shashank Mittal | 246f8d0 | 2011-01-21 17:12:27 -0800 | [diff] [blame] | 288 | #if (!ENABLE_NANDWRITE) |
| 289 | thread_sleep(1); |
| 290 | #else |
| 291 | mdelay(1); |
| 292 | #endif |
| 293 | } |
| 294 | } |
Shashank Mittal | ef32541 | 2011-04-01 13:48:26 -0700 | [diff] [blame] | 295 | |
| 296 | void hsusb_clock_init(void) |
| 297 | { |
| 298 | /* USB local clock control not enabled; use proc comm */ |
| 299 | usb_clock_init(); |
| 300 | } |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 301 | |
| 302 | /* Configure MMC clock */ |
| 303 | void clock_config_mmc(uint32_t interface, uint32_t freq) |
| 304 | { |
| 305 | uint32_t reg = 0; |
| 306 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 307 | if (mmc_clock_set_rate(sdc_clk[interface], freq) < 0) { |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 308 | dprintf(CRITICAL, "Failure setting clock rate for MCLK - " |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 309 | "clk_rate: %d\n!", freq); |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 310 | ASSERT(0); |
| 311 | } |
| 312 | |
| 313 | /* enable clock */ |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 314 | if (mmc_clock_enable_disable(sdc_clk[interface], MMC_CLK_ENABLE) < 0) { |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 315 | dprintf(CRITICAL, "Failure enabling MMC Clock!\n"); |
| 316 | ASSERT(0); |
| 317 | } |
| 318 | |
| 319 | reg |= MMC_BOOT_MCI_CLK_ENABLE; |
| 320 | reg |= MMC_BOOT_MCI_CLK_ENA_FLOW; |
| 321 | reg |= MMC_BOOT_MCI_CLK_IN_FEEDBACK; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 322 | writel(reg, MMC_BOOT_MCI_CLK); |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 323 | |
| 324 | /* Wait for the MMC_BOOT_MCI_CLK write to go through. */ |
| 325 | mmc_mclk_reg_wr_delay(); |
| 326 | |
| 327 | /* Wait 1 ms to provide the free running SD CLK to the card. */ |
| 328 | mdelay(1); |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 329 | } |
| 330 | |
| 331 | /* Intialize MMC clock */ |
| 332 | void clock_init_mmc(uint32_t interface) |
| 333 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 334 | if (mmc_clock_enable_disable(sdc_pclk[interface], MMC_CLK_ENABLE) < 0) { |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 335 | dprintf(CRITICAL, "Failure enabling PCLK!\n"); |
| 336 | ASSERT(0); |
| 337 | } |
| 338 | } |