vijay kumar | 7d06bbb | 2015-11-24 13:04:55 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. |
Joonwoo Park | e586c2e | 2014-04-02 11:04:10 -0700 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <debug.h> |
| 30 | #include <board.h> |
| 31 | #include <platform.h> |
| 32 | #include <target.h> |
| 33 | #include <smem.h> |
| 34 | #include <baseband.h> |
| 35 | #include <lib/ptable.h> |
| 36 | #include <qpic_nand.h> |
Sridhar Parasuram | dbe91a4 | 2014-12-29 13:45:30 -0800 | [diff] [blame] | 37 | #include <malloc.h> |
Joonwoo Park | e586c2e | 2014-04-02 11:04:10 -0700 | [diff] [blame] | 38 | #include <ctype.h> |
| 39 | #include <string.h> |
| 40 | #include <pm8x41.h> |
| 41 | #include <reg.h> |
| 42 | #include <hsusb.h> |
| 43 | #include <mmc.h> |
| 44 | #include <platform/timer.h> |
| 45 | #include <platform/irqs.h> |
| 46 | #include <platform/gpio.h> |
| 47 | #include <platform/clock.h> |
| 48 | #include <qmp_phy.h> |
Joonwoo Park | 39aed06 | 2014-06-09 17:00:07 -0700 | [diff] [blame] | 49 | #include <qusb2_phy.h> |
anisha agarwal | ffb78ab | 2014-11-18 15:20:31 -0800 | [diff] [blame] | 50 | #include <rpm-smd.h> |
| 51 | #include <scm.h> |
Sridhar Parasuram | dbe91a4 | 2014-12-29 13:45:30 -0800 | [diff] [blame] | 52 | #include <spmi.h> |
| 53 | #include <partition_parser.h> |
| 54 | #include <sdhci_msm.h> |
| 55 | #include <uart_dm.h> |
| 56 | #include <boot_device.h> |
Channagoud Kadabi | fdfee23 | 2015-10-07 11:55:47 -0700 | [diff] [blame] | 57 | #include <qmp_phy.h> |
vijay kumar | 7d06bbb | 2015-11-24 13:04:55 +0530 | [diff] [blame] | 58 | #include <crypto5_wrapper.h> |
Joonwoo Park | e586c2e | 2014-04-02 11:04:10 -0700 | [diff] [blame] | 59 | |
| 60 | extern void smem_ptable_init(void); |
| 61 | extern void smem_add_modem_partitions(struct ptable *flash_ptable); |
| 62 | void target_sdc_init(); |
| 63 | |
| 64 | static struct ptable flash_ptable; |
| 65 | |
| 66 | /* PMIC config data */ |
| 67 | #define PMIC_ARB_CHANNEL_NUM 0 |
| 68 | #define PMIC_ARB_OWNER_ID 0 |
| 69 | |
| 70 | /* NANDc BAM pipe numbers */ |
| 71 | #define DATA_CONSUMER_PIPE 0 |
| 72 | #define DATA_PRODUCER_PIPE 1 |
| 73 | #define CMD_PIPE 2 |
| 74 | |
| 75 | /* NANDc BAM pipe groups */ |
| 76 | #define DATA_PRODUCER_PIPE_GRP 0 |
| 77 | #define DATA_CONSUMER_PIPE_GRP 0 |
| 78 | #define CMD_PIPE_GRP 1 |
| 79 | |
| 80 | /* NANDc EE */ |
| 81 | #define QPIC_NAND_EE 0 |
| 82 | |
| 83 | /* NANDc max desc length. */ |
| 84 | #define QPIC_NAND_MAX_DESC_LEN 0x7FFF |
| 85 | |
| 86 | #define LAST_NAND_PTN_LEN_PATTERN 0xFFFFFFFF |
| 87 | |
Smita Ghosh | 50a53ac | 2015-02-11 12:33:30 -0800 | [diff] [blame] | 88 | #define EXT4_CMDLINE " rootwait rootfstype=ext4 root=/dev/mmcblk0p" |
anisha agarwal | 11df23e | 2015-06-12 14:37:34 -0700 | [diff] [blame] | 89 | #define UBI_CMDLINE " rootfstype=ubifs rootflags=bulk_read" |
anisha agarwal | ce363dd | 2014-08-26 15:17:09 -0700 | [diff] [blame] | 90 | |
vijay kumar | 7d06bbb | 2015-11-24 13:04:55 +0530 | [diff] [blame] | 91 | #define CE1_INSTANCE 1 |
| 92 | #define CE_EE 1 |
| 93 | #define CE_FIFO_SIZE 64 |
| 94 | #define CE_READ_PIPE 3 |
| 95 | #define CE_WRITE_PIPE 2 |
| 96 | #define CE_READ_PIPE_LOCK_GRP 0 |
| 97 | #define CE_WRITE_PIPE_LOCK_GRP 0 |
| 98 | #define CE_ARRAY_SIZE 20 |
| 99 | #define SUB_TYPE_SKUT 0x0A |
| 100 | |
Joonwoo Park | e586c2e | 2014-04-02 11:04:10 -0700 | [diff] [blame] | 101 | struct qpic_nand_init_config config; |
| 102 | |
| 103 | void update_ptable_names(void) |
| 104 | { |
| 105 | uint32_t ptn_index; |
| 106 | struct ptentry *ptentry_ptr = flash_ptable.parts; |
Joonwoo Park | e586c2e | 2014-04-02 11:04:10 -0700 | [diff] [blame] | 107 | unsigned i; |
| 108 | uint32_t len; |
| 109 | |
| 110 | /* Change all names to lower case. */ |
| 111 | for (ptn_index = 0; ptn_index != (uint32_t)flash_ptable.count; ptn_index++) |
| 112 | { |
| 113 | len = strlen(ptentry_ptr[ptn_index].name); |
| 114 | |
| 115 | for (i = 0; i < len; i++) |
| 116 | { |
| 117 | if (isupper(ptentry_ptr[ptn_index].name[i])) |
| 118 | { |
| 119 | ptentry_ptr[ptn_index].name[i] = tolower(ptentry_ptr[ptn_index].name[i]); |
| 120 | } |
| 121 | } |
| 122 | |
| 123 | /* SBL fills in the last partition length as 0xFFFFFFFF. |
| 124 | * Update the length field based on the number of blocks on the flash. |
| 125 | */ |
| 126 | if ((uint32_t)(ptentry_ptr[ptn_index].length) == LAST_NAND_PTN_LEN_PATTERN) |
| 127 | { |
| 128 | ptentry_ptr[ptn_index].length = flash_num_blocks() - ptentry_ptr[ptn_index].start; |
| 129 | } |
| 130 | } |
| 131 | } |
| 132 | |
| 133 | void target_early_init(void) |
| 134 | { |
| 135 | #if WITH_DEBUG_UART |
Channagoud Kadabi | 1b69e48 | 2014-09-23 15:20:22 -0700 | [diff] [blame] | 136 | uart_dm_init(3, 0, BLSP1_UART2_BASE); |
Joonwoo Park | e586c2e | 2014-04-02 11:04:10 -0700 | [diff] [blame] | 137 | #endif |
| 138 | } |
| 139 | |
| 140 | int target_is_emmc_boot(void) |
| 141 | { |
| 142 | return platform_boot_dev_isemmc(); |
| 143 | } |
| 144 | |
| 145 | /* init */ |
| 146 | void target_init(void) |
| 147 | { |
| 148 | dprintf(INFO, "target_init()\n"); |
| 149 | |
Sridhar Parasuram | 9ed91f3 | 2015-07-07 15:37:44 -0700 | [diff] [blame] | 150 | pmic_info_populate(); |
| 151 | |
Joonwoo Park | e586c2e | 2014-04-02 11:04:10 -0700 | [diff] [blame] | 152 | spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID); |
vijay kumar | 7d06bbb | 2015-11-24 13:04:55 +0530 | [diff] [blame] | 153 | rpm_smd_init(); |
Joonwoo Park | e586c2e | 2014-04-02 11:04:10 -0700 | [diff] [blame] | 154 | |
Joonwoo Park | e586c2e | 2014-04-02 11:04:10 -0700 | [diff] [blame] | 155 | if (platform_boot_dev_isemmc()) { |
| 156 | target_sdc_init(); |
| 157 | if (partition_read_table()) { |
| 158 | dprintf(CRITICAL, "Error reading the partition table info\n"); |
| 159 | ASSERT(0); |
| 160 | } |
anisha agarwal | 70b8cd1 | 2015-02-02 11:44:46 -0800 | [diff] [blame] | 161 | /* Below setting is to enable EBI2 function selection in TLMM so |
| 162 | that GPIOs can be used for display */ |
| 163 | writel((readl(TLMM_EBI2_EMMC_GPIO_CFG) | EBI2_BOOT_SELECT), TLMM_EBI2_EMMC_GPIO_CFG); |
Joonwoo Park | e586c2e | 2014-04-02 11:04:10 -0700 | [diff] [blame] | 164 | } else { |
| 165 | config.pipes.read_pipe = DATA_PRODUCER_PIPE; |
| 166 | config.pipes.write_pipe = DATA_CONSUMER_PIPE; |
| 167 | config.pipes.cmd_pipe = CMD_PIPE; |
| 168 | |
| 169 | config.pipes.read_pipe_grp = DATA_PRODUCER_PIPE_GRP; |
| 170 | config.pipes.write_pipe_grp = DATA_CONSUMER_PIPE_GRP; |
| 171 | config.pipes.cmd_pipe_grp = CMD_PIPE_GRP; |
| 172 | |
| 173 | config.bam_base = MSM_NAND_BAM_BASE; |
| 174 | config.nand_base = MSM_NAND_BASE; |
| 175 | config.ee = QPIC_NAND_EE; |
| 176 | config.max_desc_len = QPIC_NAND_MAX_DESC_LEN; |
| 177 | |
| 178 | qpic_nand_init(&config); |
| 179 | |
| 180 | ptable_init(&flash_ptable); |
| 181 | smem_ptable_init(); |
| 182 | smem_add_modem_partitions(&flash_ptable); |
| 183 | |
| 184 | update_ptable_names(); |
| 185 | flash_set_ptable(&flash_ptable); |
| 186 | } |
vijay kumar | 7d06bbb | 2015-11-24 13:04:55 +0530 | [diff] [blame] | 187 | |
| 188 | if (target_use_signed_kernel()) |
| 189 | target_crypto_init_params(); |
Joonwoo Park | e586c2e | 2014-04-02 11:04:10 -0700 | [diff] [blame] | 190 | } |
| 191 | |
| 192 | /* reboot */ |
| 193 | void reboot_device(unsigned reboot_reason) |
| 194 | { |
| 195 | /* Write the reboot reason */ |
| 196 | writel(reboot_reason, RESTART_REASON_ADDR); |
| 197 | |
| 198 | /* Configure PMIC for warm reset */ |
| 199 | /* PM 8019 v1 aligns with PM8941 v2. |
| 200 | * This call should be based on the pmic version |
| 201 | * when PM8019 v2 is available. |
| 202 | */ |
Channagoud Kadabi | a85ed6e | 2015-03-23 14:35:16 -0700 | [diff] [blame] | 203 | if (reboot_reason) |
| 204 | pm8x41_v2_reset_configure(PON_PSHOLD_WARM_RESET); |
| 205 | else |
| 206 | pm8x41_v2_reset_configure(PON_PSHOLD_HARD_RESET); |
Joonwoo Park | e586c2e | 2014-04-02 11:04:10 -0700 | [diff] [blame] | 207 | |
| 208 | /* Drop PS_HOLD for MSM */ |
| 209 | writel(0x00, MPM2_MPM_PS_HOLD); |
| 210 | |
| 211 | mdelay(5000); |
| 212 | |
| 213 | dprintf(CRITICAL, "Rebooting failed\n"); |
| 214 | return; |
| 215 | } |
| 216 | |
| 217 | /* Identify the current target */ |
| 218 | void target_detect(struct board_data *board) |
| 219 | { |
| 220 | /* This property is filled as part of board.c */ |
| 221 | } |
| 222 | |
| 223 | unsigned board_machtype(void) |
| 224 | { |
| 225 | return LINUX_MACHTYPE_UNKNOWN; |
| 226 | } |
| 227 | |
| 228 | /* Identify the baseband being used */ |
| 229 | void target_baseband_detect(struct board_data *board) |
| 230 | { |
| 231 | board->baseband = BASEBAND_MSM; |
| 232 | } |
| 233 | |
Sridhar Parasuram | 1d8c422 | 2014-10-22 13:43:00 -0700 | [diff] [blame] | 234 | void target_serialno(unsigned char *buf) |
| 235 | { |
| 236 | uint32_t serialno; |
| 237 | serialno = board_chip_serial(); |
| 238 | snprintf((char *)buf, 13, "%x", serialno); |
| 239 | } |
| 240 | |
Joonwoo Park | e586c2e | 2014-04-02 11:04:10 -0700 | [diff] [blame] | 241 | unsigned check_reboot_mode(void) |
| 242 | { |
| 243 | unsigned restart_reason = 0; |
| 244 | |
| 245 | /* Read reboot reason and scrub it */ |
| 246 | restart_reason = readl(RESTART_REASON_ADDR); |
| 247 | |
| 248 | writel(0x00, RESTART_REASON_ADDR); |
| 249 | |
| 250 | return restart_reason; |
| 251 | } |
| 252 | |
vijay kumar | ff36c31 | 2015-08-31 17:12:33 +0530 | [diff] [blame] | 253 | int get_target_boot_params(const char *cmdline, const char *part, char **buf) |
Joonwoo Park | e586c2e | 2014-04-02 11:04:10 -0700 | [diff] [blame] | 254 | { |
| 255 | struct ptable *ptable; |
| 256 | int system_ptn_index = -1; |
vijay kumar | ff36c31 | 2015-08-31 17:12:33 +0530 | [diff] [blame] | 257 | uint32_t buflen; |
Channagoud Kadabi | fdfee23 | 2015-10-07 11:55:47 -0700 | [diff] [blame] | 258 | int ret = -1; |
Joonwoo Park | e586c2e | 2014-04-02 11:04:10 -0700 | [diff] [blame] | 259 | |
vijay kumar | ff36c31 | 2015-08-31 17:12:33 +0530 | [diff] [blame] | 260 | if (!cmdline || !part ) { |
anisha agarwal | ce363dd | 2014-08-26 15:17:09 -0700 | [diff] [blame] | 261 | dprintf(CRITICAL, "WARN: Invalid input param\n"); |
| 262 | return -1; |
Joonwoo Park | e586c2e | 2014-04-02 11:04:10 -0700 | [diff] [blame] | 263 | } |
| 264 | |
anisha agarwal | ce363dd | 2014-08-26 15:17:09 -0700 | [diff] [blame] | 265 | if (!strstr(cmdline, "root=/dev/ram")) /* This check is to handle kdev boot */ |
| 266 | { |
| 267 | if (!target_is_emmc_boot()) { |
vijay kumar | ff36c31 | 2015-08-31 17:12:33 +0530 | [diff] [blame] | 268 | |
| 269 | buflen = strlen(UBI_CMDLINE) + strlen(" root=ubi0:rootfs ubi.mtd=") + sizeof(int) + 1; |
| 270 | *buf = (char *)malloc(buflen); |
| 271 | if(!(*buf)) { |
| 272 | dprintf(CRITICAL,"Unable to allocate memory for boot params\n"); |
| 273 | return -1; |
| 274 | } |
anisha agarwal | ce363dd | 2014-08-26 15:17:09 -0700 | [diff] [blame] | 275 | /* Below is for NAND boot */ |
| 276 | ptable = flash_get_ptable(); |
| 277 | if (!ptable) { |
| 278 | dprintf(CRITICAL, |
| 279 | "WARN: Cannot get flash partition table\n"); |
vijay kumar | ff36c31 | 2015-08-31 17:12:33 +0530 | [diff] [blame] | 280 | free(*buf); |
anisha agarwal | ce363dd | 2014-08-26 15:17:09 -0700 | [diff] [blame] | 281 | return -1; |
| 282 | } |
| 283 | |
| 284 | system_ptn_index = ptable_get_index(ptable, part); |
| 285 | if (system_ptn_index < 0) { |
| 286 | dprintf(CRITICAL, |
| 287 | "WARN: Cannot get partition index for %s\n", part); |
vijay kumar | ff36c31 | 2015-08-31 17:12:33 +0530 | [diff] [blame] | 288 | free(*buf); |
anisha agarwal | ce363dd | 2014-08-26 15:17:09 -0700 | [diff] [blame] | 289 | return -1; |
| 290 | } |
| 291 | /* Adding command line parameters according to target boot type */ |
vijay kumar | ff36c31 | 2015-08-31 17:12:33 +0530 | [diff] [blame] | 292 | snprintf(*buf, buflen, UBI_CMDLINE); |
| 293 | snprintf(*buf+strlen(*buf), buflen, " root=ubi0:rootfs ubi.mtd=%d", system_ptn_index); |
Channagoud Kadabi | fdfee23 | 2015-10-07 11:55:47 -0700 | [diff] [blame] | 294 | ret = 0; |
anisha agarwal | ce363dd | 2014-08-26 15:17:09 -0700 | [diff] [blame] | 295 | } |
| 296 | else { |
Channagoud Kadabi | 9d9b521 | 2015-10-20 17:29:50 -0700 | [diff] [blame] | 297 | buflen = strlen(EXT4_CMDLINE) + sizeof(int) +1; |
vijay kumar | ff36c31 | 2015-08-31 17:12:33 +0530 | [diff] [blame] | 298 | *buf = (char *)malloc(buflen); |
| 299 | if(!(*buf)) { |
| 300 | dprintf(CRITICAL,"Unable to allocate memory for boot params\n"); |
| 301 | return -1; |
| 302 | } |
anisha agarwal | ce363dd | 2014-08-26 15:17:09 -0700 | [diff] [blame] | 303 | /* Below is for emmc boot */ |
anisha agarwal | c49a325 | 2014-10-15 17:37:40 -0700 | [diff] [blame] | 304 | system_ptn_index = partition_get_index(part) + 1; /* Adding +1 as offsets for eMMC start at 1 and NAND at 0 */ |
anisha agarwal | ce363dd | 2014-08-26 15:17:09 -0700 | [diff] [blame] | 305 | if (system_ptn_index < 0) { |
| 306 | dprintf(CRITICAL, |
| 307 | "WARN: Cannot get partition index for %s\n", part); |
vijay kumar | ff36c31 | 2015-08-31 17:12:33 +0530 | [diff] [blame] | 308 | free(*buf); |
anisha agarwal | ce363dd | 2014-08-26 15:17:09 -0700 | [diff] [blame] | 309 | return -1; |
| 310 | } |
vijay kumar | ff36c31 | 2015-08-31 17:12:33 +0530 | [diff] [blame] | 311 | snprintf(*buf, buflen, EXT4_CMDLINE"%d", system_ptn_index); |
Channagoud Kadabi | fdfee23 | 2015-10-07 11:55:47 -0700 | [diff] [blame] | 312 | ret = 0; |
anisha agarwal | ce363dd | 2014-08-26 15:17:09 -0700 | [diff] [blame] | 313 | } |
anisha agarwal | ce363dd | 2014-08-26 15:17:09 -0700 | [diff] [blame] | 314 | } |
vijay kumar | ff36c31 | 2015-08-31 17:12:33 +0530 | [diff] [blame] | 315 | /*in success case buf will be freed in the calling function of this*/ |
Channagoud Kadabi | fdfee23 | 2015-10-07 11:55:47 -0700 | [diff] [blame] | 316 | return ret; |
Joonwoo Park | e586c2e | 2014-04-02 11:04:10 -0700 | [diff] [blame] | 317 | } |
| 318 | |
| 319 | const char * target_usb_controller() |
| 320 | { |
| 321 | return "dwc"; |
| 322 | } |
| 323 | |
| 324 | static void set_sdc_power_ctrl() |
| 325 | { |
| 326 | /* Drive strength configs for sdc pins */ |
| 327 | struct tlmm_cfgs sdc1_hdrv_cfg[] = |
| 328 | { |
Sridhar Parasuram | dbe91a4 | 2014-12-29 13:45:30 -0800 | [diff] [blame] | 329 | { SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK, 0 }, |
| 330 | { SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, 0 }, |
| 331 | { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_6MA, TLMM_HDRV_MASK, 0 }, |
Joonwoo Park | e586c2e | 2014-04-02 11:04:10 -0700 | [diff] [blame] | 332 | }; |
| 333 | |
| 334 | /* Pull configs for sdc pins */ |
| 335 | struct tlmm_cfgs sdc1_pull_cfg[] = |
| 336 | { |
Sridhar Parasuram | dbe91a4 | 2014-12-29 13:45:30 -0800 | [diff] [blame] | 337 | { SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK, 0 }, |
| 338 | { SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, 0 }, |
| 339 | { SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, 0 }, |
Joonwoo Park | e586c2e | 2014-04-02 11:04:10 -0700 | [diff] [blame] | 340 | }; |
| 341 | |
| 342 | /* Set the drive strength & pull control values */ |
| 343 | tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg)); |
| 344 | tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg)); |
| 345 | } |
| 346 | |
| 347 | static struct mmc_device *dev; |
| 348 | |
| 349 | void *target_mmc_device() |
| 350 | { |
| 351 | return (void *) dev; |
| 352 | } |
| 353 | |
| 354 | void target_sdc_init() |
| 355 | { |
| 356 | struct mmc_config_data config; |
| 357 | |
| 358 | /* Set drive strength & pull ctrl values */ |
| 359 | set_sdc_power_ctrl(); |
| 360 | |
| 361 | config.slot = 1; |
Channagoud Kadabi | de17ba8 | 2014-11-12 13:05:57 -0800 | [diff] [blame] | 362 | config.bus_width = DATA_BUS_WIDTH_8BIT; |
Channagoud Kadabi | 6608d02 | 2015-04-20 11:31:56 -0700 | [diff] [blame] | 363 | config.max_clk_rate = MMC_CLK_171MHZ; |
Joonwoo Park | e586c2e | 2014-04-02 11:04:10 -0700 | [diff] [blame] | 364 | config.sdhc_base = MSM_SDC1_SDHCI_BASE; |
| 365 | config.pwrctl_base = MSM_SDC1_BASE; |
| 366 | config.pwr_irq = SDCC1_PWRCTL_IRQ; |
| 367 | config.hs400_support = 0; |
Channagoud Kadabi | de17ba8 | 2014-11-12 13:05:57 -0800 | [diff] [blame] | 368 | config.hs200_support = 0; |
Channagoud Kadabi | d23379d | 2014-10-13 11:33:50 -0700 | [diff] [blame] | 369 | config.use_io_switch = 1; |
Joonwoo Park | e586c2e | 2014-04-02 11:04:10 -0700 | [diff] [blame] | 370 | |
| 371 | if (!(dev = mmc_init(&config))) { |
| 372 | dprintf(CRITICAL, "mmc init failed!"); |
| 373 | ASSERT(0); |
| 374 | } |
| 375 | } |
| 376 | |
anisha agarwal | 0fc661d | 2014-11-26 11:54:32 -0800 | [diff] [blame] | 377 | int target_cont_splash_screen() |
| 378 | { |
| 379 | /* FOR OEMs - Set cont_splash_screen to keep the splash enable after LK.*/ |
anisha agarwal | 58d25cf | 2014-11-26 12:09:23 -0800 | [diff] [blame] | 380 | return false; |
anisha agarwal | 0fc661d | 2014-11-26 11:54:32 -0800 | [diff] [blame] | 381 | } |
| 382 | |
Joonwoo Park | e586c2e | 2014-04-02 11:04:10 -0700 | [diff] [blame] | 383 | void target_uninit(void) |
| 384 | { |
| 385 | if (platform_boot_dev_isemmc()) |
| 386 | { |
| 387 | mmc_put_card_to_sleep(dev); |
| 388 | sdhci_mode_disable(&dev->host); |
| 389 | } |
vijay kumar | 7d06bbb | 2015-11-24 13:04:55 +0530 | [diff] [blame] | 390 | |
| 391 | if (crypto_initialized()) |
| 392 | crypto_eng_cleanup(); |
| 393 | |
| 394 | rpm_smd_uninit(); |
Joonwoo Park | e586c2e | 2014-04-02 11:04:10 -0700 | [diff] [blame] | 395 | } |
| 396 | |
Joonwoo Park | 39aed06 | 2014-06-09 17:00:07 -0700 | [diff] [blame] | 397 | void target_usb_phy_reset(void) |
| 398 | { |
Channagoud Kadabi | fdfee23 | 2015-10-07 11:55:47 -0700 | [diff] [blame] | 399 | /* Reset sequence for californium is different from 9x40, use the reset sequence |
| 400 | * from clock driver |
| 401 | */ |
| 402 | if (platform_is_mdmcalifornium()) |
| 403 | clock_reset_usb_phy(); |
| 404 | else |
| 405 | usb30_qmp_phy_reset(); |
| 406 | |
Channagoud Kadabi | 1b69e48 | 2014-09-23 15:20:22 -0700 | [diff] [blame] | 407 | qusb2_phy_reset(); |
Joonwoo Park | 39aed06 | 2014-06-09 17:00:07 -0700 | [diff] [blame] | 408 | } |
| 409 | |
Joonwoo Park | e586c2e | 2014-04-02 11:04:10 -0700 | [diff] [blame] | 410 | target_usb_iface_t* target_usb30_init() |
| 411 | { |
| 412 | target_usb_iface_t *t_usb_iface; |
| 413 | |
Sridhar Parasuram | dbe91a4 | 2014-12-29 13:45:30 -0800 | [diff] [blame] | 414 | t_usb_iface = (target_usb_iface_t *) calloc(1, sizeof(target_usb_iface_t)); |
Joonwoo Park | e586c2e | 2014-04-02 11:04:10 -0700 | [diff] [blame] | 415 | ASSERT(t_usb_iface); |
| 416 | |
| 417 | t_usb_iface->mux_config = NULL; |
| 418 | t_usb_iface->phy_init = usb30_qmp_phy_init; |
Joonwoo Park | 39aed06 | 2014-06-09 17:00:07 -0700 | [diff] [blame] | 419 | t_usb_iface->phy_reset = target_usb_phy_reset; |
Joonwoo Park | e586c2e | 2014-04-02 11:04:10 -0700 | [diff] [blame] | 420 | t_usb_iface->clock_init = clock_usb30_init; |
| 421 | t_usb_iface->vbus_override = 1; |
| 422 | |
| 423 | return t_usb_iface; |
| 424 | } |
Channagoud Kadabi | 1b69e48 | 2014-09-23 15:20:22 -0700 | [diff] [blame] | 425 | |
| 426 | uint32_t target_override_pll() |
| 427 | { |
Channagoud Kadabi | fdfee23 | 2015-10-07 11:55:47 -0700 | [diff] [blame] | 428 | if (platform_is_mdmcalifornium()) |
| 429 | return 0; |
| 430 | else |
| 431 | return 1; |
Channagoud Kadabi | 1b69e48 | 2014-09-23 15:20:22 -0700 | [diff] [blame] | 432 | } |
Channagoud Kadabi | d23379d | 2014-10-13 11:33:50 -0700 | [diff] [blame] | 433 | |
| 434 | uint32_t target_get_hlos_subtype() |
| 435 | { |
| 436 | return board_hlos_subtype(); |
| 437 | } |
Channagoud Kadabi | fdfee23 | 2015-10-07 11:55:47 -0700 | [diff] [blame] | 438 | |
| 439 | /* QMP settings are different from californium when compared to v2.0/v1.0 hardware. |
| 440 | * Use the QMP settings from target code to keep the common driver clean |
| 441 | */ |
| 442 | struct qmp_reg qmp_settings[] = |
| 443 | { |
| 444 | {0x804, 0x01}, /*USB3PHY_PCIE_USB3_PCS_POWER_DOWN_CONTROL */ |
| 445 | {0xAC, 0x14}, /* QSERDES_COM_SYSCLK_EN_SEL */ |
| 446 | {0x34, 0x08}, /* QSERDES_COM_BIAS_EN_CLKBUFLR_EN */ |
| 447 | {0x174, 0x30}, /* QSERDES_COM_CLK_SELECT */ |
| 448 | {0x3C, 0x06}, /* QSERDES_COM_SYS_CLK_CTRL */ |
| 449 | {0xB4, 0x00}, /* QSERDES_COM_RESETSM_CNTRL */ |
| 450 | {0xB8, 0x08}, /* QSERDES_COM_RESETSM_CNTRL2 */ |
| 451 | {0x194, 0x06}, /* QSERDES_COM_CMN_CONFIG */ |
| 452 | {0x19c, 0x01}, /* QSERDES_COM_SVS_MODE_CLK_SEL */ |
| 453 | {0x178, 0x00}, /* QSERDES_COM_HSCLK_SEL */ |
| 454 | {0xd0, 0x82}, /* QSERDES_COM_DEC_START_MODE0 */ |
| 455 | {0xdc, 0x55}, /* QSERDES_COM_DIV_FRAC_START1_MODE0 */ |
| 456 | {0xe0, 0x55}, /* QSERDES_COM_DIV_FRAC_START2_MODE0 */ |
| 457 | {0xe4, 0x03}, /* QSERDES_COM_DIV_FRAC_START3_MODE0 */ |
| 458 | {0x78, 0x0b}, /* QSERDES_COM_CP_CTRL_MODE0 */ |
| 459 | {0x84, 0x16}, /* QSERDES_COM_PLL_RCTRL_MODE0 */ |
| 460 | {0x90, 0x28}, /* QSERDES_COM_PLL_CCTRL_MODE0 */ |
| 461 | {0x108, 0x80}, /* QSERDES_COM_INTEGLOOP_GAIN0_MODE0 */ |
| 462 | {0x10C, 0x00}, /* QSERDES_COM_INTEGLOOP_GAIN1_MODE0 */ |
| 463 | {0x184, 0x0A}, /* QSERDES_COM_CORECLK_DIV */ |
| 464 | {0x4c, 0x15}, /* QSERDES_COM_LOCK_CMP1_MODE0 */ |
| 465 | {0x50, 0x34}, /* QSERDES_COM_LOCK_CMP2_MODE0 */ |
| 466 | {0x54, 0x00}, /* QSERDES_COM_LOCK_CMP3_MODE0 */ |
| 467 | {0xC8, 0x00}, /* QSERDES_COM_LOCK_CMP_EN */ |
| 468 | {0x18c, 0x00}, /* QSERDES_COM_CORE_CLK_EN */ |
| 469 | {0xcc, 0x00}, /* QSERDES_COM_LOCK_CMP_CFG */ |
| 470 | {0x128, 0x00}, /* QSERDES_COM_VCO_TUNE_MAP */ |
| 471 | {0x0C, 0x0A}, /* QSERDES_COM_BG_TIMER */ |
| 472 | {0x10, 0x01}, /* QSERDES_COM_SSC_EN_CENTER */ |
| 473 | {0x1c, 0x31}, /* QSERDES_COM_SSC_PER1 */ |
| 474 | {0x20, 0x01}, /* QSERDES_COM_SSC_PER2 */ |
| 475 | {0x14, 0x00}, /* QSERDES_COM_SSC_ADJ_PER1 */ |
| 476 | {0x18, 0x00}, /* QSERDES_COM_SSC_ADJ_PER2 */ |
| 477 | {0x24, 0xde}, /* QSERDES_COM_SSC_STEP_SIZE1 */ |
| 478 | {0x28, 0x07}, /* QSERDES_COM_SSC_STEP_SIZE2 */ |
| 479 | {0x48, 0x0F}, /* USB3PHY_QSERDES_COM_PLL_IVCO */ |
| 480 | {0x70, 0x0F}, /* USB3PHY_QSERDES_COM_BG_TRIM */ |
| 481 | {0x100, 0x80}, /* QSERDES_COM_INTEGLOOP_INITVAL */ |
| 482 | |
| 483 | /* Rx Settings */ |
| 484 | {0x440, 0x0b}, /* QSERDES_RX_UCDR_FASTLOCK_FO_GAIN */ |
| 485 | {0x4d8, 0x02}, /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 */ |
| 486 | {0x4dc, 0x6c}, /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 */ |
| 487 | {0x4e0, 0xbb}, /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 */ |
| 488 | {0x508, 0x77}, /* QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 */ |
| 489 | {0x50c, 0x80}, /* QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 */ |
| 490 | {0x514, 0x03}, /* QSERDES_RX_SIGDET_CNTRL */ |
| 491 | {0x51c, 0x16}, /* QSERDES_RX_SIGDET_DEGLITCH_CNTRL */ |
| 492 | {0x448, 0x75}, /* QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE */ |
| 493 | {0x450, 0x00}, /* QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW */ |
| 494 | {0x454, 0x00}, /* QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH */ |
| 495 | {0x40C, 0x0a}, /* QSERDES_RX_UCDR_FO_GAIN */ |
| 496 | {0x41C, 0x06}, /* QSERDES_RX_UCDR_SO_GAIN */ |
| 497 | {0x510, 0x00}, /*QSERDES_RX_SIGDET_ENABLES */ |
| 498 | |
| 499 | /* Tx settings */ |
| 500 | {0x268, 0x45}, /* QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN */ |
| 501 | {0x2ac, 0x12}, /* QSERDES_TX_RCV_DETECT_LVL_2 */ |
| 502 | {0x294, 0x06}, /* QSERDES_TX_LANE_MODE */ |
| 503 | {0x254, 0x00}, /* QSERDES_TX_RES_CODE_LANE_OFFSET */ |
| 504 | |
| 505 | /* FLL settings */ |
| 506 | {0x8c8, 0x83}, /* PCIE_USB3_PCS_FLL_CNTRL2 */ |
| 507 | {0x8c4, 0x02}, /* PCIE_USB3_PCS_FLL_CNTRL1 */ |
| 508 | {0x8cc, 0x09}, /* PCIE_USB3_PCS_FLL_CNT_VAL_L */ |
| 509 | {0x8D0, 0xA2}, /* PCIE_USB3_PCS_FLL_CNT_VAL_H_TOL */ |
| 510 | {0x8D4, 0x85}, /* PCIE_USB3_PCS_FLL_MAN_CODE */ |
| 511 | |
| 512 | /* PCS Settings */ |
| 513 | {0x880, 0xD1}, /* PCIE_USB3_PCS_LOCK_DETECT_CONFIG1 */ |
| 514 | {0x884, 0x1F}, /* PCIE_USB3_PCS_LOCK_DETECT_CONFIG2 */ |
| 515 | {0x888, 0x47}, /* PCIE_USB3_PCS_LOCK_DETECT_CONFIG3 */ |
| 516 | {0x80C, 0x9F}, /* PCIE_USB3_PCS_TXMGN_V0 */ |
| 517 | {0x824, 0x17}, /* PCIE_USB3_PCS_TXDEEMPH_M6DB_V0 */ |
| 518 | {0x828, 0x0F}, /* PCIE_USB3_PCS_TXDEEMPH_M3P5DB_V0 */ |
| 519 | {0x8B8, 0x75}, /* PCIE_USB3_PCS_RXEQTRAINING_WAIT_TIME */ |
| 520 | {0x8BC, 0x13}, /* PCIE_USB3_PCS_RXEQTRAINING_RUN_TIME */ |
| 521 | {0x8B0, 0x86}, /* PCIE_USB3_PCS_LFPS_TX_ECSTART_EQTLOCK */ |
| 522 | {0x8A0, 0x04}, /* PCIE_USB3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK */ |
| 523 | {0x88C, 0x44}, /* PCIE_USB3_PCS_TSYNC_RSYNC_TIME */ |
| 524 | {0x870, 0xE7}, /* PCIE_USB3_PCS_RCVR_DTCT_DLY_P1U2_L */ |
| 525 | {0x874, 0x03}, /* PCIE_USB3_PCS_RCVR_DTCT_DLY_P1U2_H */ |
| 526 | {0x878, 0x40}, /* PCIE_USB3_PCS_RCVR_DTCT_DLY_U3_L */ |
| 527 | {0x87c, 0x00}, /* PCIE_USB3_PCS_RCVR_DTCT_DLY_U3_H */ |
| 528 | {0x9D8, 0x88}, /* PCIE_USB3_PCS_RX_SIGDET_LVL */ |
| 529 | {0x808, 0x03}, /* PCIE_USB3_PCS_START_CONTROL */ |
| 530 | {0x800, 0x00}, /* PCIE_USB3_PCS_SW_RESET */ |
| 531 | }; |
| 532 | |
| 533 | struct qmp_reg *target_get_qmp_settings() |
| 534 | { |
| 535 | if (platform_is_mdmcalifornium()) |
| 536 | return qmp_settings; |
| 537 | else |
| 538 | return NULL; |
| 539 | } |
| 540 | |
| 541 | int target_get_qmp_regsize() |
| 542 | { |
| 543 | if (platform_is_mdmcalifornium()) |
| 544 | return ARRAY_SIZE(qmp_settings); |
| 545 | else |
| 546 | return 0; |
| 547 | } |
vijay kumar | 7d06bbb | 2015-11-24 13:04:55 +0530 | [diff] [blame] | 548 | |
| 549 | crypto_engine_type board_ce_type(void) |
| 550 | { |
| 551 | return CRYPTO_ENGINE_TYPE_HW; |
| 552 | } |
| 553 | |
| 554 | /* Set up params for h/w CE. */ |
| 555 | void target_crypto_init_params() |
| 556 | { |
| 557 | struct crypto_init_params ce_params; |
| 558 | |
| 559 | /* Set up base addresses and instance. */ |
| 560 | ce_params.crypto_instance = CE1_INSTANCE; |
| 561 | ce_params.crypto_base = MSM_CE1_BASE; |
| 562 | ce_params.bam_base = MSM_CE1_BAM_BASE; |
| 563 | |
| 564 | /* Set up BAM config. */ |
| 565 | ce_params.bam_ee = CE_EE; |
| 566 | ce_params.pipes.read_pipe = CE_READ_PIPE; |
| 567 | ce_params.pipes.write_pipe = CE_WRITE_PIPE; |
| 568 | ce_params.pipes.read_pipe_grp = CE_READ_PIPE_LOCK_GRP; |
| 569 | ce_params.pipes.write_pipe_grp = CE_WRITE_PIPE_LOCK_GRP; |
| 570 | |
| 571 | /* Assign buffer sizes. */ |
| 572 | ce_params.num_ce = CE_ARRAY_SIZE; |
| 573 | ce_params.read_fifo_size = CE_FIFO_SIZE; |
| 574 | ce_params.write_fifo_size = CE_FIFO_SIZE; |
| 575 | |
| 576 | /* BAM is initialized by TZ for this platform. |
| 577 | * Do not do it again as the initialization address space |
| 578 | * is locked. |
| 579 | */ |
| 580 | ce_params.do_bam_init = 0; |
| 581 | crypto_init_params(&ce_params); |
| 582 | } |