Padmanabhan Komanduru | bd8268a | 2018-04-30 17:05:56 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2012-2015, 2018, The Linux Foundation. All rights reserved. |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 12 | * * Neither the name of The Linux Foundation nor the names of its |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | * |
| 28 | */ |
| 29 | #include <debug.h> |
| 30 | #include <reg.h> |
| 31 | #include <mipi_dsi.h> |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 32 | #include <mdp5.h> |
| 33 | #include <platform/timer.h> |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 34 | #include <platform/iomap.h> |
Prashant Nukala | 33715aa | 2015-06-15 21:32:43 +0530 | [diff] [blame] | 35 | #include <target/display.h> |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 36 | #include <arch/defines.h> |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 37 | |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 38 | #if (DISPLAY_TYPE_MDSS == 0) |
| 39 | #define MIPI_DSI0_BASE MIPI_DSI_BASE |
| 40 | #define MIPI_DSI1_BASE MIPI_DSI_BASE |
| 41 | #endif |
| 42 | |
Dhaval Patel | ee8c9b3 | 2014-08-12 16:18:50 -0700 | [diff] [blame] | 43 | #define MMSS_DSI_CLKOUT_TIMING_CTRL 0x0c4 |
| 44 | #define MMSS_DSI_PHY_TIMING_CTRL_0 0x0140 |
| 45 | #define MMSS_DSI_PHY_CTRL_0 0x0170 |
| 46 | #define MMSS_DSI_PHY_CTRL_1 0x0174 |
| 47 | #define MMSS_DSI_PHY_CTRL_2 0x0178 |
| 48 | #define MMSS_DSI_PHY_STRENGTH_CTRL_0 0x0184 |
| 49 | #define MMSS_DSI_PHY_STRENGTH_CTRL_1 0x0188 |
| 50 | #define MMSS_DSI_PHY_BIST_CTRL_0 0x01b4 |
| 51 | #define MMSS_DSI_PHY_GLBL_TEST_CTRL 0x01d4 |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame] | 52 | #define MDSS_DSI_DSIPHY_REGULATOR_CTRL_0 0x00 |
| 53 | #define MDSS_DSI_DSIPHY_REGULATOR_CTRL_1 0x04 |
| 54 | #define MDSS_DSI_DSIPHY_REGULATOR_CTRL_2 0x08 |
| 55 | #define MDSS_DSI_DSIPHY_REGULATOR_CTRL_3 0x0c |
| 56 | #define MDSS_DSI_DSIPHY_REGULATOR_CTRL_4 0x10 |
| 57 | #define MDSS_DSI_DSIPHY_REGULATOR_CAL_PWR_CFG 0x18 |
Dhaval Patel | ee8c9b3 | 2014-08-12 16:18:50 -0700 | [diff] [blame] | 58 | #define MMSS_DSI_PHY_LDO_CTRL 0x01dc |
| 59 | |
| 60 | #define TOTAL_TIMING_CTRL_CONFIG 12 |
| 61 | #define TOTAL_BIST_CTRL_CONFIG 6 |
| 62 | /* 4 data lanes and 1 clock lanes */ |
| 63 | #define TOTAL_LANE_COUNT 5 |
| 64 | #define CONFIG_REG_FOR_EACH_LANE 9 |
| 65 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 66 | static void mipi_dsi_calibration(uint32_t ctl_base) |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 67 | { |
| 68 | uint32_t i = 0; |
| 69 | uint32_t term_cnt = 5000; |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 70 | int32_t cal_busy = readl(ctl_base + 0x550); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 71 | |
| 72 | /* DSI1_DSIPHY_REGULATOR_CAL_PWR_CFG */ |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 73 | writel(0x01, ctl_base + 0x0518); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 74 | |
| 75 | /* DSI1_DSIPHY_CAL_SW_CFG2 */ |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 76 | writel(0x0, ctl_base + 0x0534); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 77 | /* DSI1_DSIPHY_CAL_HW_CFG1 */ |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 78 | writel(0x5a, ctl_base + 0x053c); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 79 | /* DSI1_DSIPHY_CAL_HW_CFG3 */ |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 80 | writel(0x10, ctl_base + 0x0544); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 81 | /* DSI1_DSIPHY_CAL_HW_CFG4 */ |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 82 | writel(0x01, ctl_base + 0x0548); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 83 | /* DSI1_DSIPHY_CAL_HW_CFG0 */ |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 84 | writel(0x01, ctl_base + 0x0538); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 85 | |
| 86 | /* DSI1_DSIPHY_CAL_HW_TRIGGER */ |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 87 | writel(0x01, ctl_base + 0x0528); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 88 | |
| 89 | /* DSI1_DSIPHY_CAL_HW_TRIGGER */ |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 90 | writel(0x00, ctl_base + 0x0528); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 91 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 92 | cal_busy = readl(ctl_base + 0x550); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 93 | while (cal_busy & 0x10) { |
| 94 | i++; |
| 95 | if (i > term_cnt) { |
| 96 | dprintf(CRITICAL, "DSI1 PHY REGULATOR NOT READY," |
| 97 | "exceeded polling TIMEOUT!\n"); |
| 98 | break; |
| 99 | } |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 100 | cal_busy = readl(ctl_base + 0x550); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 101 | } |
| 102 | } |
| 103 | |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 104 | #if (DISPLAY_TYPE_MDSS == 0) |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 105 | int mipi_dsi_phy_init(struct mipi_dsi_panel_config *pinfo) |
| 106 | { |
| 107 | struct mipi_dsi_phy_ctrl *pd; |
| 108 | uint32_t i, off = 0; |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 109 | int mdp_rev; |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 110 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 111 | mdp_rev = mdp_get_revision(); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 112 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 113 | if (MDP_REV_303 == mdp_rev || MDP_REV_41 == mdp_rev) { |
| 114 | writel(0x00000001, DSIPHY_SW_RESET); |
| 115 | writel(0x00000000, DSIPHY_SW_RESET); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 116 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 117 | pd = (pinfo->dsi_phy_config); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 118 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 119 | off = 0x02cc; /* regulator ctrl 0 */ |
| 120 | for (i = 0; i < 4; i++) { |
| 121 | writel(pd->regulator[i], MIPI_DSI_BASE + off); |
| 122 | off += 4; |
| 123 | } |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 124 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 125 | off = 0x0260; /* phy timig ctrl 0 */ |
| 126 | for (i = 0; i < 11; i++) { |
| 127 | writel(pd->timing[i], MIPI_DSI_BASE + off); |
| 128 | off += 4; |
| 129 | } |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 130 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 131 | /* T_CLK_POST, T_CLK_PRE for CLK lane P/N HS 200 mV timing |
| 132 | length should > data lane HS timing length */ |
| 133 | writel(0xa1e, DSI_CLKOUT_TIMING_CTRL); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 134 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 135 | off = 0x0290; /* ctrl 0 */ |
| 136 | for (i = 0; i < 4; i++) { |
| 137 | writel(pd->ctrl[i], MIPI_DSI_BASE + off); |
| 138 | off += 4; |
| 139 | } |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 140 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 141 | off = 0x02a0; /* strength 0 */ |
| 142 | for (i = 0; i < 4; i++) { |
| 143 | writel(pd->strength[i], MIPI_DSI_BASE + off); |
| 144 | off += 4; |
| 145 | } |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 146 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 147 | if (1 == pinfo->num_of_lanes) |
| 148 | pd->pll[10] |= 0x8; |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 149 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 150 | off = 0x0204; /* pll ctrl 1, skip 0 */ |
| 151 | for (i = 1; i < 21; i++) { |
| 152 | writel(pd->pll[i], MIPI_DSI_BASE + off); |
| 153 | off += 4; |
| 154 | } |
| 155 | |
| 156 | /* pll ctrl 0 */ |
| 157 | writel(pd->pll[0], MIPI_DSI_BASE + 0x200); |
| 158 | writel((pd->pll[0] | 0x01), MIPI_DSI_BASE + 0x200); |
| 159 | /* lane swp ctrol */ |
| 160 | if (pinfo->lane_swap) |
| 161 | writel(pinfo->lane_swap, MIPI_DSI_BASE + 0xac); |
| 162 | } else { |
| 163 | writel(0x0001, MIPI_DSI_BASE + 0x128); /* start phy sw reset */ |
| 164 | writel(0x0000, MIPI_DSI_BASE + 0x128); /* end phy w reset */ |
| 165 | writel(0x0003, MIPI_DSI_BASE + 0x500); /* regulator_ctrl_0 */ |
| 166 | writel(0x0001, MIPI_DSI_BASE + 0x504); /* regulator_ctrl_1 */ |
| 167 | writel(0x0001, MIPI_DSI_BASE + 0x508); /* regulator_ctrl_2 */ |
| 168 | writel(0x0000, MIPI_DSI_BASE + 0x50c); /* regulator_ctrl_3 */ |
| 169 | writel(0x0100, MIPI_DSI_BASE + 0x510); /* regulator_ctrl_4 */ |
| 170 | |
| 171 | pd = (pinfo->dsi_phy_config); |
| 172 | |
| 173 | off = 0x0480; /* strength 0 - 2 */ |
| 174 | for (i = 0; i < 3; i++) { |
| 175 | writel(pd->strength[i], MIPI_DSI_BASE + off); |
| 176 | off += 4; |
| 177 | } |
| 178 | |
| 179 | off = 0x0470; /* ctrl 0 - 3 */ |
| 180 | for (i = 0; i < 4; i++) { |
| 181 | writel(pd->ctrl[i], MIPI_DSI_BASE + off); |
| 182 | off += 4; |
| 183 | } |
| 184 | |
| 185 | off = 0x0500; /* regulator ctrl 0 - 4 */ |
| 186 | for (i = 0; i < 5; i++) { |
| 187 | writel(pd->regulator[i], MIPI_DSI_BASE + off); |
| 188 | off += 4; |
| 189 | } |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 190 | mipi_dsi_calibration(MIPI_DSI_BASE); |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 191 | |
| 192 | off = 0x0204; /* pll ctrl 1 - 19, skip 0 */ |
| 193 | for (i = 1; i < 20; i++) { |
| 194 | writel(pd->pll[i], MIPI_DSI_BASE + off); |
| 195 | off += 4; |
| 196 | } |
| 197 | |
| 198 | /* pll ctrl 0 */ |
| 199 | writel(pd->pll[0], MIPI_DSI_BASE + 0x200); |
| 200 | writel((pd->pll[0] | 0x01), MIPI_DSI_BASE + 0x200); |
| 201 | |
| 202 | /* Check that PHY is ready */ |
| 203 | while (!(readl(DSIPHY_PLL_RDY) & 0x01)) |
| 204 | udelay(1); |
| 205 | |
| 206 | writel(0x202D, DSI_CLKOUT_TIMING_CTRL); |
| 207 | |
| 208 | off = 0x0440; /* phy timing ctrl 0 - 11 */ |
| 209 | for (i = 0; i < 12; i++) { |
| 210 | writel(pd->timing[i], MIPI_DSI_BASE + off); |
| 211 | off += 4; |
| 212 | } |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 213 | } |
| 214 | return 0; |
| 215 | } |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 216 | #endif |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 217 | |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 218 | void mdss_dsi_phy_sw_reset(uint32_t ctl_base) |
Chandan Uddaraju | 932723b | 2013-02-21 18:36:20 -0800 | [diff] [blame] | 219 | { |
| 220 | /* start phy sw reset */ |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 221 | writel(0x0001, ctl_base + 0x012c); |
Chandan Uddaraju | 932723b | 2013-02-21 18:36:20 -0800 | [diff] [blame] | 222 | udelay(1000); |
Dhaval Patel | 8b9a582 | 2015-03-16 13:01:26 -0700 | [diff] [blame] | 223 | dmb(); |
Chandan Uddaraju | 932723b | 2013-02-21 18:36:20 -0800 | [diff] [blame] | 224 | |
| 225 | /* end phy sw reset */ |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 226 | writel(0x0000, ctl_base + 0x012c); |
Chandan Uddaraju | 932723b | 2013-02-21 18:36:20 -0800 | [diff] [blame] | 227 | udelay(100); |
Dhaval Patel | 8b9a582 | 2015-03-16 13:01:26 -0700 | [diff] [blame] | 228 | dmb(); |
Chandan Uddaraju | 932723b | 2013-02-21 18:36:20 -0800 | [diff] [blame] | 229 | } |
| 230 | |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame] | 231 | static void mdss_dsi_20nm_phy_regulator_init(struct mdss_dsi_phy_ctrl *pd, |
| 232 | uint32_t phy_base, uint32_t reg_base) |
Jeevan Shriram | a0623d5 | 2014-12-14 14:25:48 -0800 | [diff] [blame] | 233 | { |
| 234 | /* DSI0 and DSI1 have a common regulator */ |
Jeevan Shriram | a0623d5 | 2014-12-14 14:25:48 -0800 | [diff] [blame] | 235 | if (pd->regulator_mode == DSI_PHY_REGULATOR_LDO_MODE) { |
| 236 | /* LDO ctrl */ |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame] | 237 | writel(0x1d, phy_base + MMSS_DSI_PHY_LDO_CTRL); |
Jeevan Shriram | a0623d5 | 2014-12-14 14:25:48 -0800 | [diff] [blame] | 238 | } else { |
| 239 | /* Regulator ctrl 1 */ |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame] | 240 | writel(pd->regulator[1], reg_base + MDSS_DSI_DSIPHY_REGULATOR_CTRL_1); |
Jeevan Shriram | a0623d5 | 2014-12-14 14:25:48 -0800 | [diff] [blame] | 241 | /* Regulator ctrl 2 */ |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame] | 242 | writel(pd->regulator[2], reg_base + MDSS_DSI_DSIPHY_REGULATOR_CTRL_2); |
Jeevan Shriram | a0623d5 | 2014-12-14 14:25:48 -0800 | [diff] [blame] | 243 | /* Regulator ctrl 3 */ |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame] | 244 | writel(pd->regulator[3], reg_base + MDSS_DSI_DSIPHY_REGULATOR_CTRL_3); |
Jeevan Shriram | a0623d5 | 2014-12-14 14:25:48 -0800 | [diff] [blame] | 245 | /* Regulator ctrl 4 */ |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame] | 246 | writel(pd->regulator[4], reg_base + MDSS_DSI_DSIPHY_REGULATOR_CTRL_4); |
Jeevan Shriram | a0623d5 | 2014-12-14 14:25:48 -0800 | [diff] [blame] | 247 | /* Regulator ctrl - CAL_PWR_CFG */ |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame] | 248 | writel(pd->regulator[6], reg_base + MDSS_DSI_DSIPHY_REGULATOR_CAL_PWR_CFG); |
Jeevan Shriram | a0623d5 | 2014-12-14 14:25:48 -0800 | [diff] [blame] | 249 | /* LDO ctrl */ |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame] | 250 | writel(0x00, phy_base + MMSS_DSI_PHY_LDO_CTRL); |
Jeevan Shriram | a0623d5 | 2014-12-14 14:25:48 -0800 | [diff] [blame] | 251 | /* Regulator ctrl 0 */ |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame] | 252 | writel(pd->regulator[0], reg_base + MDSS_DSI_DSIPHY_REGULATOR_CTRL_0); |
Jeevan Shriram | a0623d5 | 2014-12-14 14:25:48 -0800 | [diff] [blame] | 253 | dmb(); |
| 254 | } |
| 255 | } |
| 256 | |
Prashant Nukala | 33715aa | 2015-06-15 21:32:43 +0530 | [diff] [blame] | 257 | static void mdss_dsi_phy_regulator_init(struct mdss_dsi_phy_ctrl *pd, uint32_t ctl_base, |
| 258 | uint32_t phy_base, uint32_t reg_base) |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 259 | { |
| 260 | /* DSI0 and DSI1 have a common regulator */ |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 261 | |
Padmanabhan Komanduru | 2232c14 | 2014-10-29 00:06:24 +0530 | [diff] [blame] | 262 | if (pd->regulator_mode == DSI_PHY_REGULATOR_LDO_MODE) { |
| 263 | /* Regulator ctrl 0 */ |
Prashant Nukala | 33715aa | 2015-06-15 21:32:43 +0530 | [diff] [blame] | 264 | writel(0x00, reg_base + (4 * 0)); |
Padmanabhan Komanduru | 2232c14 | 2014-10-29 00:06:24 +0530 | [diff] [blame] | 265 | /* Regulator ctrl - CAL_PWD_CFG */ |
Prashant Nukala | 33715aa | 2015-06-15 21:32:43 +0530 | [diff] [blame] | 266 | writel(pd->regulator[6], reg_base + (4 * 6)); |
Padmanabhan Komanduru | 2232c14 | 2014-10-29 00:06:24 +0530 | [diff] [blame] | 267 | /* Add h/w recommended delay */ |
| 268 | udelay(1000); |
| 269 | /* Regulator ctrl - TEST */ |
Prashant Nukala | 33715aa | 2015-06-15 21:32:43 +0530 | [diff] [blame] | 270 | writel(pd->regulator[5], reg_base + (4 * 5)); |
Padmanabhan Komanduru | 2232c14 | 2014-10-29 00:06:24 +0530 | [diff] [blame] | 271 | /* Regulator ctrl 3 */ |
Prashant Nukala | 33715aa | 2015-06-15 21:32:43 +0530 | [diff] [blame] | 272 | writel(pd->regulator[3], reg_base + (4 * 3)); |
Padmanabhan Komanduru | 2232c14 | 2014-10-29 00:06:24 +0530 | [diff] [blame] | 273 | /* Regulator ctrl 2 */ |
Prashant Nukala | 33715aa | 2015-06-15 21:32:43 +0530 | [diff] [blame] | 274 | writel(pd->regulator[2], reg_base + (4 * 2)); |
Padmanabhan Komanduru | 2232c14 | 2014-10-29 00:06:24 +0530 | [diff] [blame] | 275 | /* Regulator ctrl 1 */ |
Prashant Nukala | 33715aa | 2015-06-15 21:32:43 +0530 | [diff] [blame] | 276 | writel(pd->regulator[1], reg_base + (4 * 1)); |
Padmanabhan Komanduru | 2232c14 | 2014-10-29 00:06:24 +0530 | [diff] [blame] | 277 | /* Regulator ctrl 4 */ |
Prashant Nukala | 33715aa | 2015-06-15 21:32:43 +0530 | [diff] [blame] | 278 | writel(pd->regulator[4], reg_base + (4 * 4)); |
Padmanabhan Komanduru | 2232c14 | 2014-10-29 00:06:24 +0530 | [diff] [blame] | 279 | /* LDO ctrl */ |
Prashant Nukala | 33715aa | 2015-06-15 21:32:43 +0530 | [diff] [blame] | 280 | if ((readl(ctl_base) == DSI_HW_REV_103_1) || |
| 281 | (readl(ctl_base) == DSI_HW_REV_104_2)) /* 8916/8939/8952/8956 */ |
Padmanabhan Komanduru | 2232c14 | 2014-10-29 00:06:24 +0530 | [diff] [blame] | 282 | writel(0x05, phy_base + 0x01dc); |
Padmanabhan Komanduru | 2232c14 | 2014-10-29 00:06:24 +0530 | [diff] [blame] | 283 | else |
| 284 | writel(0x0d, phy_base + 0x01dc); |
| 285 | dmb(); |
| 286 | } else { |
| 287 | /* Regulator ctrl 0 */ |
Prashant Nukala | 33715aa | 2015-06-15 21:32:43 +0530 | [diff] [blame] | 288 | writel(0x00, reg_base + (4 * 0)); |
Padmanabhan Komanduru | 2232c14 | 2014-10-29 00:06:24 +0530 | [diff] [blame] | 289 | /* Regulator ctrl - CAL_PWD_CFG */ |
Prashant Nukala | 33715aa | 2015-06-15 21:32:43 +0530 | [diff] [blame] | 290 | writel(pd->regulator[6], reg_base + (4 * 6)); |
Padmanabhan Komanduru | 2232c14 | 2014-10-29 00:06:24 +0530 | [diff] [blame] | 291 | /* Add h/w recommended delay */ |
| 292 | udelay(1000); |
| 293 | /* Regulator ctrl 1 */ |
Prashant Nukala | 33715aa | 2015-06-15 21:32:43 +0530 | [diff] [blame] | 294 | writel(pd->regulator[1], reg_base + (4 * 1)); |
Padmanabhan Komanduru | 2232c14 | 2014-10-29 00:06:24 +0530 | [diff] [blame] | 295 | /* Regulator ctrl 2 */ |
Prashant Nukala | 33715aa | 2015-06-15 21:32:43 +0530 | [diff] [blame] | 296 | writel(pd->regulator[2], reg_base + (4 * 2)); |
Padmanabhan Komanduru | 2232c14 | 2014-10-29 00:06:24 +0530 | [diff] [blame] | 297 | /* Regulator ctrl 3 */ |
Prashant Nukala | 33715aa | 2015-06-15 21:32:43 +0530 | [diff] [blame] | 298 | writel(pd->regulator[3], reg_base + (4 * 3)); |
Padmanabhan Komanduru | 2232c14 | 2014-10-29 00:06:24 +0530 | [diff] [blame] | 299 | /* Regulator ctrl 4 */ |
Prashant Nukala | 33715aa | 2015-06-15 21:32:43 +0530 | [diff] [blame] | 300 | writel(pd->regulator[4], reg_base + (4 * 4)); |
Padmanabhan Komanduru | 2232c14 | 2014-10-29 00:06:24 +0530 | [diff] [blame] | 301 | /* LDO ctrl */ |
| 302 | writel(0x00, phy_base + 0x01dc); |
| 303 | /* Regulator ctrl 0 */ |
Prashant Nukala | 33715aa | 2015-06-15 21:32:43 +0530 | [diff] [blame] | 304 | writel(pd->regulator[0], reg_base + (4 * 0)); |
Padmanabhan Komanduru | 2232c14 | 2014-10-29 00:06:24 +0530 | [diff] [blame] | 305 | dmb(); |
| 306 | } |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 307 | } |
| 308 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 309 | int mdss_dsi_v2_phy_init(struct mipi_panel_info *mipi, uint32_t ctl_base) |
Terence Hampson | f49ff4e | 2013-06-18 15:11:31 -0400 | [diff] [blame] | 310 | { |
| 311 | struct mdss_dsi_phy_ctrl *pd; |
| 312 | uint32_t i, ln, off = 0, offset; |
| 313 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 314 | pd = mipi->mdss_dsi_phy_db; |
Terence Hampson | f49ff4e | 2013-06-18 15:11:31 -0400 | [diff] [blame] | 315 | /* DSI PHY configuration */ |
| 316 | off = 0x480; |
| 317 | writel(pd->strength[0], ctl_base + off + (4 * 0)); |
| 318 | writel(pd->strength[1], ctl_base + off + (4 * 2)); |
| 319 | |
| 320 | off = 0x470; |
| 321 | writel(0x10, ctl_base + off + (4 * 3)); |
| 322 | writel(0x5F, ctl_base + off + (4 * 0)); |
| 323 | |
| 324 | off = 0x500; |
Xiaoming Zhou | 7c9e1ee | 2013-07-18 10:51:41 -0400 | [diff] [blame] | 325 | /* use LDO mode */ |
| 326 | writel(0x25, ctl_base + 0x4B0); |
Terence Hampson | f49ff4e | 2013-06-18 15:11:31 -0400 | [diff] [blame] | 327 | for (i = 0; i < 5; i++) |
| 328 | writel(pd->regulator[i], ctl_base + off + (4 * i)); |
| 329 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 330 | mipi_dsi_calibration(ctl_base); |
Terence Hampson | f49ff4e | 2013-06-18 15:11:31 -0400 | [diff] [blame] | 331 | |
| 332 | /* 4 lanes + clk lane configuration */ |
| 333 | /* lane config n * (0 - 4) & DataPath setup */ |
| 334 | for (ln = 0; ln < 5; ln++) { |
| 335 | off = 0x0300 + (ln * 0x40); |
| 336 | for (i = 0; i < 9; i++) { |
| 337 | offset = i + (ln * 9); |
| 338 | writel(pd->laneCfg[offset], ctl_base + off); |
| 339 | dmb(); |
| 340 | off += 4; |
| 341 | } |
| 342 | } |
| 343 | |
| 344 | off = 0x440; |
| 345 | for (i = 0; i < 12; i++) |
| 346 | writel(pd->timing[i], ctl_base + off + (4 * i)); |
| 347 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 348 | if (1 == mipi->num_of_lanes) |
Terence Hampson | f49ff4e | 2013-06-18 15:11:31 -0400 | [diff] [blame] | 349 | writel(0x8, ctl_base + 0x200 + (4 * 11)); |
| 350 | |
| 351 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 352 | if (mipi->lane_swap) |
| 353 | writel(mipi->lane_swap, ctl_base + 0x0ac); |
Terence Hampson | f49ff4e | 2013-06-18 15:11:31 -0400 | [diff] [blame] | 354 | |
| 355 | /* T_CLK_POST, T_CLK_PRE for CLK lane P/N HS 200 mV timing |
| 356 | length should > data lane HS timing length */ |
| 357 | writel(0x41b, ctl_base + 0x0c0); |
| 358 | return 0; |
| 359 | } |
| 360 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 361 | static int mdss_dsi_phy_28nm_init(struct mipi_panel_info *mipi, |
Prashant Nukala | 33715aa | 2015-06-15 21:32:43 +0530 | [diff] [blame] | 362 | uint32_t ctl_base, uint32_t phy_base, uint32_t reg_base) |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 363 | { |
| 364 | struct mdss_dsi_phy_ctrl *pd; |
Prashant Nukala | 33715aa | 2015-06-15 21:32:43 +0530 | [diff] [blame] | 365 | uint32_t i, off = 0, ln, offset, dsi0_phy_base; |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 366 | |
Terence Hampson | f49ff4e | 2013-06-18 15:11:31 -0400 | [diff] [blame] | 367 | if (mdp_get_revision() == MDP_REV_304) |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 368 | return mdss_dsi_v2_phy_init(mipi, ctl_base); |
Terence Hampson | f49ff4e | 2013-06-18 15:11:31 -0400 | [diff] [blame] | 369 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 370 | pd = (mipi->mdss_dsi_phy_db); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 371 | |
Padmanabhan Komanduru | 0a74989 | 2015-06-15 15:38:59 +0530 | [diff] [blame] | 372 | /* PHY_CTRL_0 */ |
| 373 | writel(0x5b, phy_base + 0x0170); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 374 | /* Strength ctrl 0 */ |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 375 | writel(pd->strength[0], phy_base + 0x0184); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 376 | |
Prashant Nukala | 33715aa | 2015-06-15 21:32:43 +0530 | [diff] [blame] | 377 | mdss_dsi_phy_regulator_init(pd, ctl_base, phy_base, reg_base); |
Chandan Uddaraju | 932723b | 2013-02-21 18:36:20 -0800 | [diff] [blame] | 378 | |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 379 | off = 0x0140; /* phy timing ctrl 0 - 11 */ |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 380 | for (i = 0; i < 12; i++) { |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 381 | writel(pd->timing[i], phy_base + off); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 382 | dmb(); |
| 383 | off += 4; |
| 384 | } |
| 385 | |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 386 | /* 4 lanes + clk lane configuration */ |
| 387 | /* lane config n * (0 - 4) & DataPath setup */ |
| 388 | for (ln = 0; ln < 5; ln++) { |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 389 | off = (ln * 0x40); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 390 | for (i = 0; i < 9; i++) { |
| 391 | offset = i + (ln * 9); |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 392 | writel(pd->laneCfg[offset], phy_base + off); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 393 | dmb(); |
| 394 | off += 4; |
| 395 | } |
| 396 | } |
| 397 | |
Padmanabhan Komanduru | 0a74989 | 2015-06-15 15:38:59 +0530 | [diff] [blame] | 398 | /* MMSS_DSI_0_PHY_DSIPHY_CTRL_4 */ |
| 399 | writel(0x0a, phy_base + 0x0180); |
| 400 | dmb(); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 401 | |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 402 | /* DSI_PHY_DSIPHY_GLBL_TEST_CTRL */ |
Sandeep Panda | b066d7c | 2015-07-31 16:45:09 +0530 | [diff] [blame] | 403 | if (mipi->dual_dsi) { |
| 404 | dsi0_phy_base = DSI0_PHY_BASE + |
| 405 | target_display_get_base_offset(DSI0_PHY_BASE); |
| 406 | if ((phy_base == dsi0_phy_base) || |
| 407 | (readl(mipi->ctl_base) == DSI_HW_REV_103_1)) |
| 408 | writel(0x01, phy_base + 0x01d4); |
| 409 | else |
| 410 | writel(0x00, phy_base + 0x01d4); |
| 411 | } else { |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 412 | writel(0x01, phy_base + 0x01d4); |
Sandeep Panda | b066d7c | 2015-07-31 16:45:09 +0530 | [diff] [blame] | 413 | } |
| 414 | dmb(); |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 415 | |
Padmanabhan Komanduru | 0a74989 | 2015-06-15 15:38:59 +0530 | [diff] [blame] | 416 | /* MMSS_DSI_0_PHY_DSIPHY_CTRL_0 */ |
| 417 | writel(0x5f, phy_base + 0x0170); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 418 | dmb(); |
| 419 | |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 420 | off = 0x01b4; /* phy BIST ctrl 0 - 5 */ |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 421 | for (i = 0; i < 6; i++) { |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 422 | writel(pd->bistCtrl[i], phy_base + off); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 423 | off += 4; |
| 424 | } |
| 425 | dmb(); |
| 426 | |
| 427 | /* DSI_0_CLKOUT_TIMING_CTRL */ |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 428 | writel(0x41b, ctl_base + 0x0c4); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 429 | dmb(); |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 430 | return 0; |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 431 | |
| 432 | } |
Xiaoming Zhou | 03fd48b | 2014-07-31 15:24:41 -0400 | [diff] [blame] | 433 | |
| 434 | void mdss_dsi_phy_contention_detection( |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 435 | struct mipi_panel_info *mipi, |
Xiaoming Zhou | 03fd48b | 2014-07-31 15:24:41 -0400 | [diff] [blame] | 436 | uint32_t phy_base) |
| 437 | { |
| 438 | struct mdss_dsi_phy_ctrl *pd; |
| 439 | |
Dhaval Patel | 8b9a582 | 2015-03-16 13:01:26 -0700 | [diff] [blame] | 440 | if ((mipi->mdss_dsi_phy_db->pll_type == DSI_PLL_TYPE_THULIUM) || |
Padmanabhan Komanduru | bd8268a | 2018-04-30 17:05:56 +0530 | [diff] [blame] | 441 | (mipi->mdss_dsi_phy_db->pll_type == DSI_PLL_TYPE_12NM) || |
Dhaval Patel | 8b9a582 | 2015-03-16 13:01:26 -0700 | [diff] [blame] | 442 | (mdp_get_revision() == MDP_REV_304)) |
Xiaoming Zhou | 03fd48b | 2014-07-31 15:24:41 -0400 | [diff] [blame] | 443 | return; |
| 444 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 445 | pd = (mipi->mdss_dsi_phy_db); |
Aravind Venkateswaran | 51e5755 | 2014-12-09 13:23:19 -0800 | [diff] [blame] | 446 | writel(pd->strength[1], phy_base + MMSS_DSI_PHY_STRENGTH_CTRL_1); |
Xiaoming Zhou | 03fd48b | 2014-07-31 15:24:41 -0400 | [diff] [blame] | 447 | dmb(); |
| 448 | } |
| 449 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 450 | static int mdss_dsi_phy_20nm_init(struct mipi_panel_info *mipi, |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame] | 451 | uint32_t ctl_base, uint32_t phy_base, uint32_t reg_base) |
Dhaval Patel | ee8c9b3 | 2014-08-12 16:18:50 -0700 | [diff] [blame] | 452 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 453 | struct mdss_dsi_phy_ctrl *pd = mipi->mdss_dsi_phy_db; |
Dhaval Patel | ee8c9b3 | 2014-08-12 16:18:50 -0700 | [diff] [blame] | 454 | uint32_t i, off = 0, ln, offset; |
| 455 | |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame] | 456 | mdss_dsi_20nm_phy_regulator_init(pd, phy_base, reg_base); |
Jeevan Shriram | a0623d5 | 2014-12-14 14:25:48 -0800 | [diff] [blame] | 457 | |
Dhaval Patel | ee8c9b3 | 2014-08-12 16:18:50 -0700 | [diff] [blame] | 458 | /* Strength ctrl 0 */ |
| 459 | writel(pd->strength[0], phy_base + MMSS_DSI_PHY_STRENGTH_CTRL_0); |
| 460 | |
Jeevan Shriram | a0623d5 | 2014-12-14 14:25:48 -0800 | [diff] [blame] | 461 | writel(0x00, phy_base + MMSS_DSI_PHY_GLBL_TEST_CTRL); |
Dhaval Patel | ee8c9b3 | 2014-08-12 16:18:50 -0700 | [diff] [blame] | 462 | |
Dhaval Patel | ee8c9b3 | 2014-08-12 16:18:50 -0700 | [diff] [blame] | 463 | for (ln = 0; ln < TOTAL_LANE_COUNT; ln++) { |
| 464 | off = (ln * 0x40); |
| 465 | for (i = 0; i < CONFIG_REG_FOR_EACH_LANE; i++, off += 4) { |
| 466 | offset = i + (ln * CONFIG_REG_FOR_EACH_LANE); |
| 467 | writel(pd->laneCfg[offset], phy_base + off); |
| 468 | dmb(); |
| 469 | } |
| 470 | } |
| 471 | |
Jeevan Shriram | a0623d5 | 2014-12-14 14:25:48 -0800 | [diff] [blame] | 472 | off = MMSS_DSI_PHY_TIMING_CTRL_0; |
| 473 | for (i = 0; i < TOTAL_TIMING_CTRL_CONFIG; i++, off += 4) { |
| 474 | writel(pd->timing[i], phy_base + off); |
| 475 | dmb(); |
Dhaval Patel | ee8c9b3 | 2014-08-12 16:18:50 -0700 | [diff] [blame] | 476 | } |
Dhaval Patel | ee8c9b3 | 2014-08-12 16:18:50 -0700 | [diff] [blame] | 477 | |
Jeevan Shriram | a0623d5 | 2014-12-14 14:25:48 -0800 | [diff] [blame] | 478 | writel(0x00, phy_base + MMSS_DSI_PHY_CTRL_1); |
| 479 | dmb(); |
| 480 | writel(0x7f, phy_base + MMSS_DSI_PHY_CTRL_0); |
Dhaval Patel | ee8c9b3 | 2014-08-12 16:18:50 -0700 | [diff] [blame] | 481 | dmb(); |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 482 | return 0; |
Dhaval Patel | ee8c9b3 | 2014-08-12 16:18:50 -0700 | [diff] [blame] | 483 | } |
| 484 | |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame] | 485 | int mdss_dsi_phy_init(struct mipi_panel_info *mipi) |
Dhaval Patel | ee8c9b3 | 2014-08-12 16:18:50 -0700 | [diff] [blame] | 486 | { |
Dhaval Patel | 8b9a582 | 2015-03-16 13:01:26 -0700 | [diff] [blame] | 487 | int ret = 0; |
Dhaval Patel | ee8c9b3 | 2014-08-12 16:18:50 -0700 | [diff] [blame] | 488 | |
Dhaval Patel | 8b9a582 | 2015-03-16 13:01:26 -0700 | [diff] [blame] | 489 | /* 8994 and 8992 target */ |
| 490 | switch (mipi->mdss_dsi_phy_db->pll_type) { |
| 491 | case DSI_PLL_TYPE_20NM: |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame] | 492 | ret = mdss_dsi_phy_20nm_init(mipi, mipi->ctl_base, |
| 493 | mipi->phy_base, mipi->reg_base); |
| 494 | if (mipi->dual_dsi) |
| 495 | ret = mdss_dsi_phy_20nm_init(mipi, mipi->sctl_base, |
| 496 | mipi->sphy_base, mipi->reg_base); |
Dhaval Patel | 8b9a582 | 2015-03-16 13:01:26 -0700 | [diff] [blame] | 497 | break; |
| 498 | case DSI_PLL_TYPE_THULIUM: |
Padmanabhan Komanduru | bd8268a | 2018-04-30 17:05:56 +0530 | [diff] [blame] | 499 | case DSI_PLL_TYPE_12NM: |
Dhaval Patel | 8b9a582 | 2015-03-16 13:01:26 -0700 | [diff] [blame] | 500 | dprintf(SPEW, "phy is configured with PLL driver\n"); |
| 501 | break; |
| 502 | case DSI_PLL_TYPE_28NM: |
| 503 | default: |
Prashant Nukala | 33715aa | 2015-06-15 21:32:43 +0530 | [diff] [blame] | 504 | ret = mdss_dsi_phy_28nm_init(mipi, mipi->ctl_base, |
| 505 | mipi->phy_base, mipi->reg_base); |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame] | 506 | if (mipi->dual_dsi) |
| 507 | ret = mdss_dsi_phy_28nm_init(mipi, mipi->sctl_base, |
Prashant Nukala | 33715aa | 2015-06-15 21:32:43 +0530 | [diff] [blame] | 508 | mipi->sphy_base, mipi->reg_base); |
Dhaval Patel | 8b9a582 | 2015-03-16 13:01:26 -0700 | [diff] [blame] | 509 | break; |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame] | 510 | } |
Dhaval Patel | ee8c9b3 | 2014-08-12 16:18:50 -0700 | [diff] [blame] | 511 | |
| 512 | return ret; |
| 513 | } |