Ashish Garg | 9cfd6ca | 2016-12-20 01:41:54 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions |
| 5 | * are met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer in |
| 10 | * the documentation and/or other materials provided with the |
| 11 | * distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 19 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 20 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 22 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
| 23 | * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
| 24 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 25 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 26 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 27 | * SUCH DAMAGE. |
| 28 | */ |
| 29 | |
| 30 | #include <debug.h> |
| 31 | #include <string.h> |
| 32 | #include <smem.h> |
| 33 | #include <err.h> |
| 34 | #include <msm_panel.h> |
| 35 | #include <mipi_dsi.h> |
| 36 | #include <pm8x41.h> |
| 37 | #include <pm8x41_wled.h> |
| 38 | #include <qpnp_wled.h> |
| 39 | #include <board.h> |
| 40 | #include <mdp5.h> |
| 41 | #include <scm.h> |
| 42 | #include <regulator.h> |
| 43 | #include <platform/clock.h> |
| 44 | #include <platform/gpio.h> |
| 45 | #include <platform/iomap.h> |
| 46 | #include <target/display.h> |
| 47 | #include <qtimer.h> |
Padmanabhan Komanduru | 3cb0766 | 2015-06-08 17:13:33 +0530 | [diff] [blame] | 48 | #include <platform.h> |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 49 | |
| 50 | #include "include/panel.h" |
| 51 | #include "include/display_resource.h" |
| 52 | #include "gcdb_display.h" |
| 53 | |
Ashish Garg | 9cfd6ca | 2016-12-20 01:41:54 +0530 | [diff] [blame] | 54 | #define TRULY_720P_VID_PANEL "truly_720p_video" |
| 55 | #define TRULY_720P_CMD_PANEL "truly_720p_cmd" |
| 56 | |
| 57 | #define HDMI_ADV_PANEL_STRING "1:dsi:0:qcom,mdss_dsi_adv7533_1080p:1:none:cfg:single_dsi" |
| 58 | #define TRULY_VID_PANEL_STRING "1:dsi:0:qcom,mdss_dsi_truly_720p_video:1:none:cfg:single_dsi" |
| 59 | #define TRULY_CMD_PANEL_STRING "1:dsi:0:qcom,mdss_dsi_truly_720p_cmd:1:none:cfg:single_dsi" |
| 60 | |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 61 | /*---------------------------------------------------------------------------*/ |
| 62 | /* GPIO configuration */ |
| 63 | /*---------------------------------------------------------------------------*/ |
| 64 | static struct gpio_pin reset_gpio = { |
| 65 | "msmgpio", 0, 3, 1, 0, 1 |
| 66 | }; |
| 67 | |
| 68 | static struct gpio_pin enable_gpio = { |
| 69 | "msmgpio", 90, 3, 1, 0, 1 |
| 70 | }; |
| 71 | |
| 72 | static struct gpio_pin bkl_gpio = { |
| 73 | "msmgpio", 91, 3, 1, 0, 1 |
| 74 | }; |
| 75 | |
Padmanabhan Komanduru | 3cb0766 | 2015-06-08 17:13:33 +0530 | [diff] [blame] | 76 | static struct gpio_pin lcd_mode_gpio = { |
| 77 | "msmgpio", 107, 3, 1, 0, 1 |
| 78 | }; |
| 79 | |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 80 | #define VCO_DELAY_USEC 1000 |
| 81 | #define GPIO_STATE_LOW 0 |
| 82 | #define GPIO_STATE_HIGH 2 |
| 83 | #define RESET_GPIO_SEQ_LEN 3 |
| 84 | #define PMIC_WLED_SLAVE_ID 3 |
| 85 | |
Padmanabhan Komanduru | b338193 | 2015-06-15 22:14:02 +0530 | [diff] [blame] | 86 | #define DSI0_BASE_ADJUST -0x4000 |
| 87 | #define DSI0_PHY_BASE_ADJUST -0x4100 |
| 88 | #define DSI0_PHY_PLL_BASE_ADJUST -0x3900 |
| 89 | #define DSI0_PHY_REGULATOR_BASE_ADJUST -0x3C00 |
| 90 | |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 91 | static void mdss_dsi_uniphy_pll_sw_reset_8952(uint32_t pll_base) |
| 92 | { |
| 93 | writel(0x01, pll_base + 0x0068); /* PLL TEST CFG */ |
| 94 | mdelay(1); |
| 95 | writel(0x00, pll_base + 0x0068); /* PLL TEST CFG */ |
| 96 | mdelay(1); |
| 97 | } |
| 98 | |
| 99 | static void dsi_pll_toggle_lock_detect_8952(uint32_t pll_base) |
| 100 | { |
| 101 | writel(0x04, pll_base + 0x0064); /* LKDetect CFG2 */ |
| 102 | udelay(1); |
| 103 | writel(0x05, pll_base + 0x0064); /* LKDetect CFG2 */ |
| 104 | udelay(512); |
| 105 | } |
| 106 | |
| 107 | static void dsi_pll_sw_reset_8952(uint32_t pll_base) |
| 108 | { |
| 109 | writel(0x01, pll_base + 0x0068); /* PLL TEST CFG */ |
| 110 | udelay(1); |
| 111 | writel(0x00, pll_base + 0x0068); /* PLL TEST CFG */ |
Padmanabhan Komanduru | 6cf6352 | 2015-06-08 14:48:00 +0530 | [diff] [blame] | 112 | udelay(1); |
| 113 | } |
| 114 | |
| 115 | static uint32_t dsi_pll_lock_status_8956(uint32_t pll_base) |
| 116 | { |
| 117 | uint32_t counter, status; |
| 118 | |
| 119 | status = readl(pll_base + 0x00c0) & 0x01; |
| 120 | for (counter = 0; counter < 5 && !status; counter++) { |
| 121 | udelay(100); |
| 122 | status = readl(pll_base + 0x00c0) & 0x01; |
| 123 | } |
| 124 | |
| 125 | return status; |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 126 | } |
| 127 | |
| 128 | static uint32_t gf_1_dsi_pll_enable_sequence_8952(uint32_t pll_base) |
| 129 | { |
| 130 | uint32_t rc; |
| 131 | |
| 132 | dsi_pll_sw_reset_8952(pll_base); |
| 133 | |
| 134 | /* |
| 135 | * Add hardware recommended delays between register writes for |
| 136 | * the updates to take effect. These delays are necessary for the |
| 137 | * PLL to successfully lock |
| 138 | */ |
| 139 | writel(0x14, pll_base + 0x0070); /* CAL CFG1*/ |
| 140 | writel(0x01, pll_base + 0x0020); /* GLB CFG */ |
| 141 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
| 142 | udelay(3); |
| 143 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
| 144 | udelay(500); |
| 145 | |
| 146 | dsi_pll_toggle_lock_detect_8952(pll_base); |
| 147 | rc = readl(pll_base + 0x00c0) & 0x01; |
| 148 | |
| 149 | return rc; |
| 150 | } |
| 151 | |
| 152 | static uint32_t gf_2_dsi_pll_enable_sequence_8952(uint32_t pll_base) |
| 153 | { |
| 154 | uint32_t rc; |
| 155 | |
| 156 | dsi_pll_sw_reset_8952(pll_base); |
| 157 | |
| 158 | /* |
| 159 | * Add hardware recommended delays between register writes for |
| 160 | * the updates to take effect. These delays are necessary for the |
| 161 | * PLL to successfully lock |
| 162 | */ |
| 163 | writel(0x04, pll_base + 0x0070); /* CAL CFG1*/ |
| 164 | writel(0x01, pll_base + 0x0020); /* GLB CFG */ |
| 165 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
| 166 | udelay(3); |
| 167 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
| 168 | udelay(500); |
| 169 | |
| 170 | dsi_pll_toggle_lock_detect_8952(pll_base); |
| 171 | rc = readl(pll_base + 0x00c0) & 0x01; |
| 172 | |
| 173 | return rc; |
| 174 | } |
| 175 | |
| 176 | static uint32_t tsmc_dsi_pll_enable_sequence_8952(uint32_t pll_base) |
| 177 | { |
| 178 | uint32_t rc; |
| 179 | |
| 180 | dsi_pll_sw_reset_8952(pll_base); |
| 181 | /* |
| 182 | * Add hardware recommended delays between register writes for |
| 183 | * the updates to take effect. These delays are necessary for the |
| 184 | * PLL to successfully lock |
| 185 | */ |
| 186 | |
| 187 | writel(0x34, pll_base + 0x0070); /* CAL CFG1*/ |
| 188 | writel(0x01, pll_base + 0x0020); /* GLB CFG */ |
| 189 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
| 190 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
| 191 | udelay(500); |
| 192 | |
| 193 | dsi_pll_toggle_lock_detect_8952(pll_base); |
| 194 | rc = readl(pll_base + 0x00c0) & 0x01; |
| 195 | |
| 196 | return rc; |
| 197 | } |
| 198 | |
| 199 | |
| 200 | static uint32_t dsi_pll_enable_seq_8952(uint32_t pll_base) |
| 201 | { |
| 202 | uint32_t pll_locked = 0; |
| 203 | uint32_t counter = 0; |
| 204 | |
| 205 | do { |
| 206 | pll_locked = tsmc_dsi_pll_enable_sequence_8952(pll_base); |
| 207 | |
| 208 | dprintf(SPEW, "TSMC pll locked status is %d\n", pll_locked); |
| 209 | ++counter; |
| 210 | } while (!pll_locked && (counter < 3)); |
| 211 | |
| 212 | if(!pll_locked) { |
| 213 | counter = 0; |
| 214 | do { |
| 215 | pll_locked = gf_1_dsi_pll_enable_sequence_8952(pll_base); |
| 216 | |
| 217 | dprintf(SPEW, "GF P1 pll locked status is %d\n", pll_locked); |
| 218 | ++counter; |
| 219 | } while (!pll_locked && (counter < 3)); |
| 220 | } |
| 221 | |
| 222 | if(!pll_locked) { |
| 223 | counter = 0; |
| 224 | do { |
| 225 | pll_locked = gf_2_dsi_pll_enable_sequence_8952(pll_base); |
| 226 | |
| 227 | dprintf(SPEW, "GF P2 pll locked status is %d\n", pll_locked); |
| 228 | ++counter; |
| 229 | } while (!pll_locked && (counter < 3)); |
| 230 | } |
| 231 | |
| 232 | return pll_locked; |
| 233 | } |
| 234 | |
Padmanabhan Komanduru | 6cf6352 | 2015-06-08 14:48:00 +0530 | [diff] [blame] | 235 | static uint32_t dsi_pll_enable_seq_8956(uint32_t pll_base) |
| 236 | { |
| 237 | /* |
| 238 | * PLL power up sequence |
| 239 | * Add necessary delays recommended by h/w team |
| 240 | */ |
| 241 | |
| 242 | /* Lock Detect setting */ |
| 243 | writel(0x0d, pll_base + 0x0064); /* LKDetect CFG2 */ |
| 244 | writel(0x34, pll_base + 0x0070); /* PLL CAL_CFG1 */ |
| 245 | writel(0x10, pll_base + 0x005c); /* LKDetect CFG0 */ |
| 246 | writel(0x1a, pll_base + 0x0060); /* LKDetect CFG1 */ |
| 247 | |
| 248 | writel(0x01, pll_base + 0x0020); /* GLB CFG */ |
| 249 | udelay(300); |
| 250 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
| 251 | udelay(300); |
| 252 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
| 253 | udelay(300); |
| 254 | writel(0x07, pll_base + 0x0020); /* GLB CFG */ |
| 255 | udelay(300); |
| 256 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
| 257 | udelay(1000); |
| 258 | |
| 259 | return dsi_pll_lock_status_8956(pll_base); |
| 260 | } |
| 261 | |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 262 | static int msm8952_wled_backlight_ctrl(uint8_t enable) |
| 263 | { |
| 264 | uint8_t slave_id = PMIC_WLED_SLAVE_ID; /* pmi */ |
| 265 | |
| 266 | pm8x41_wled_config_slave_id(slave_id); |
| 267 | qpnp_wled_enable_backlight(enable); |
| 268 | qpnp_ibb_enable(enable); |
| 269 | return NO_ERROR; |
| 270 | } |
| 271 | |
| 272 | int target_backlight_ctrl(struct backlight *bl, uint8_t enable) |
| 273 | { |
| 274 | uint32_t ret = NO_ERROR; |
| 275 | |
| 276 | if (bl->bl_interface_type == BL_DCS) |
| 277 | return ret; |
| 278 | |
| 279 | ret = msm8952_wled_backlight_ctrl(enable); |
| 280 | |
| 281 | return ret; |
| 282 | } |
| 283 | |
Padmanabhan Komanduru | 77a979a | 2015-06-15 15:03:23 +0530 | [diff] [blame] | 284 | static int32_t mdss_dsi_pll_config(uint32_t pll_base, uint32_t ctl_base, |
| 285 | struct mdss_dsi_pll_config *pll_data) |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 286 | { |
| 287 | int32_t ret = 0; |
Padmanabhan Komanduru | 77a979a | 2015-06-15 15:03:23 +0530 | [diff] [blame] | 288 | if (!platform_is_msm8956()) |
| 289 | mdss_dsi_uniphy_pll_sw_reset_8952(pll_base); |
| 290 | else |
| 291 | dsi_pll_sw_reset_8952(pll_base); |
| 292 | mdss_dsi_auto_pll_config(pll_base, ctl_base, pll_data); |
| 293 | if (platform_is_msm8956()) |
| 294 | ret = dsi_pll_enable_seq_8956(pll_base); |
| 295 | else |
| 296 | ret = dsi_pll_enable_seq_8952(pll_base); |
| 297 | |
| 298 | return ret; |
| 299 | } |
| 300 | |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 301 | int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo) |
| 302 | { |
Padmanabhan Komanduru | 82ae713 | 2015-06-08 15:46:33 +0530 | [diff] [blame] | 303 | int32_t ret = 0, flags; |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 304 | struct mdss_dsi_pll_config *pll_data; |
| 305 | dprintf(SPEW, "target_panel_clock\n"); |
| 306 | |
Padmanabhan Komanduru | 82ae713 | 2015-06-08 15:46:33 +0530 | [diff] [blame] | 307 | if (pinfo->dest == DISPLAY_2) { |
| 308 | flags = MMSS_DSI_CLKS_FLAG_DSI1; |
| 309 | if (pinfo->mipi.dual_dsi) |
| 310 | flags |= MMSS_DSI_CLKS_FLAG_DSI0; |
| 311 | } else { |
| 312 | flags = MMSS_DSI_CLKS_FLAG_DSI0; |
| 313 | if (pinfo->mipi.dual_dsi) |
| 314 | flags |= MMSS_DSI_CLKS_FLAG_DSI1; |
| 315 | } |
| 316 | |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 317 | pll_data = pinfo->mipi.dsi_pll_config; |
| 318 | pll_data->vco_delay = VCO_DELAY_USEC; |
| 319 | |
Padmanabhan Komanduru | f68f51b | 2015-12-21 18:32:12 +0530 | [diff] [blame] | 320 | /* SSC parameters */ |
Parth Dixit | 05f3c9f | 2016-03-18 17:14:57 +0530 | [diff] [blame] | 321 | if (platform_is_msm8937() || platform_is_msm8917()) { |
Padmanabhan Komanduru | f68f51b | 2015-12-21 18:32:12 +0530 | [diff] [blame] | 322 | pll_data->ssc_en = true; |
| 323 | pll_data->is_center_spread = false; |
| 324 | pll_data->ssc_freq = 30000; |
| 325 | pll_data->ssc_ppm = 5000; |
| 326 | } |
| 327 | |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 328 | if (enable) { |
| 329 | mdp_gdsc_ctrl(enable); |
| 330 | mdss_bus_clocks_enable(); |
| 331 | mdp_clock_enable(); |
| 332 | ret = restore_secure_cfg(SECURE_DEVICE_MDSS); |
| 333 | if (ret) { |
| 334 | dprintf(CRITICAL, |
| 335 | "%s: Failed to restore MDP security configs", |
| 336 | __func__); |
| 337 | mdp_clock_disable(); |
| 338 | mdss_bus_clocks_disable(); |
| 339 | mdp_gdsc_ctrl(0); |
| 340 | return ret; |
| 341 | } |
Padmanabhan Komanduru | 77a979a | 2015-06-15 15:03:23 +0530 | [diff] [blame] | 342 | |
| 343 | ret = mdss_dsi_pll_config(pinfo->mipi.pll_base, |
| 344 | pinfo->mipi.ctl_base, pll_data); |
Padmanabhan Komanduru | 6cf6352 | 2015-06-08 14:48:00 +0530 | [diff] [blame] | 345 | if (!ret) |
Padmanabhan Komanduru | 77a979a | 2015-06-15 15:03:23 +0530 | [diff] [blame] | 346 | dprintf(CRITICAL, "Not able to enable master pll\n"); |
| 347 | |
Padmanabhan Komanduru | 2a6c345 | 2015-09-09 18:46:06 +0530 | [diff] [blame] | 348 | if (platform_is_msm8956() && pinfo->mipi.dual_dsi && |
| 349 | !platform_is_msm8976_v_1_1()) { |
Padmanabhan Komanduru | 77a979a | 2015-06-15 15:03:23 +0530 | [diff] [blame] | 350 | ret = mdss_dsi_pll_config(pinfo->mipi.spll_base, |
| 351 | pinfo->mipi.sctl_base, pll_data); |
| 352 | if (!ret) |
| 353 | dprintf(CRITICAL, "Not able to enable second pll\n"); |
| 354 | } |
| 355 | |
Padmanabhan Komanduru | 2a6c345 | 2015-09-09 18:46:06 +0530 | [diff] [blame] | 356 | gcc_dsi_clocks_enable(flags, pinfo->mipi.use_dsi1_pll, |
| 357 | pll_data->pclk_m, pll_data->pclk_n, pll_data->pclk_d); |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 358 | } else if(!target_cont_splash_screen()) { |
Padmanabhan Komanduru | 82ae713 | 2015-06-08 15:46:33 +0530 | [diff] [blame] | 359 | gcc_dsi_clocks_disable(flags); |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 360 | mdp_clock_disable(); |
| 361 | mdss_bus_clocks_disable(); |
| 362 | mdp_gdsc_ctrl(enable); |
| 363 | } |
| 364 | |
| 365 | return 0; |
| 366 | } |
| 367 | |
| 368 | int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq, |
| 369 | struct msm_panel_info *pinfo) |
| 370 | { |
| 371 | int ret = NO_ERROR; |
Sujeev Dias | 6bc9fa3 | 2015-08-03 23:13:44 -0700 | [diff] [blame] | 372 | uint32_t hw_id = board_hardware_id(); |
| 373 | uint32_t hw_subtype = board_hardware_subtype(); |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 374 | |
Padmanabhan Komanduru | 3cb0766 | 2015-06-08 17:13:33 +0530 | [diff] [blame] | 375 | if (platform_is_msm8956()) { |
| 376 | reset_gpio.pin_id = 25; |
| 377 | bkl_gpio.pin_id = 66; |
Padmanabhan Komanduru | b323132 | 2015-11-12 16:54:21 +0530 | [diff] [blame] | 378 | } else if (platform_is_msm8937()) { |
| 379 | reset_gpio.pin_id = 60; |
| 380 | bkl_gpio.pin_id = 98; |
| 381 | enable_gpio.pin_id = 99; |
Parth Dixit | 05f3c9f | 2016-03-18 17:14:57 +0530 | [diff] [blame] | 382 | } else if (platform_is_msm8917()) { |
Jayant Shekhar | 9c0533e | 2016-01-28 11:17:18 +0530 | [diff] [blame] | 383 | reset_gpio.pin_id = 60; |
| 384 | bkl_gpio.pin_id = 98; |
| 385 | pinfo->mipi.use_enable_gpio = 0; |
Sujeev Dias | 6bc9fa3 | 2015-08-03 23:13:44 -0700 | [diff] [blame] | 386 | } else if ((hw_id == HW_PLATFORM_QRD) && |
| 387 | (hw_subtype == HW_PLATFORM_SUBTYPE_POLARIS)) { |
| 388 | enable_gpio.pin_id = 19; |
Padmanabhan Komanduru | 3cb0766 | 2015-06-08 17:13:33 +0530 | [diff] [blame] | 389 | } |
| 390 | |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 391 | if (enable) { |
Padmanabhan Komanduru | 3cb0766 | 2015-06-08 17:13:33 +0530 | [diff] [blame] | 392 | if (pinfo->mipi.use_enable_gpio && !platform_is_msm8956()) { |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 393 | gpio_tlmm_config(enable_gpio.pin_id, 0, |
| 394 | enable_gpio.pin_direction, enable_gpio.pin_pull, |
| 395 | enable_gpio.pin_strength, |
| 396 | enable_gpio.pin_state); |
| 397 | |
| 398 | gpio_set_dir(enable_gpio.pin_id, 2); |
| 399 | } |
| 400 | |
| 401 | gpio_tlmm_config(bkl_gpio.pin_id, 0, |
| 402 | bkl_gpio.pin_direction, bkl_gpio.pin_pull, |
| 403 | bkl_gpio.pin_strength, bkl_gpio.pin_state); |
| 404 | |
| 405 | gpio_set_dir(bkl_gpio.pin_id, 2); |
| 406 | |
| 407 | gpio_tlmm_config(reset_gpio.pin_id, 0, |
| 408 | reset_gpio.pin_direction, reset_gpio.pin_pull, |
| 409 | reset_gpio.pin_strength, reset_gpio.pin_state); |
| 410 | |
| 411 | gpio_set_dir(reset_gpio.pin_id, 2); |
| 412 | |
| 413 | /* reset */ |
| 414 | for (int i = 0; i < RESET_GPIO_SEQ_LEN; i++) { |
| 415 | if (resetseq->pin_state[i] == GPIO_STATE_LOW) |
| 416 | gpio_set_dir(reset_gpio.pin_id, GPIO_STATE_LOW); |
| 417 | else |
| 418 | gpio_set_dir(reset_gpio.pin_id, GPIO_STATE_HIGH); |
| 419 | mdelay(resetseq->sleep[i]); |
| 420 | } |
Padmanabhan Komanduru | 3cb0766 | 2015-06-08 17:13:33 +0530 | [diff] [blame] | 421 | |
| 422 | if (platform_is_msm8956()) { |
| 423 | gpio_tlmm_config(lcd_mode_gpio.pin_id, 0, |
| 424 | lcd_mode_gpio.pin_direction, lcd_mode_gpio.pin_pull, |
| 425 | lcd_mode_gpio.pin_strength, lcd_mode_gpio.pin_state); |
| 426 | |
| 427 | if (pinfo->lcdc.split_display || pinfo->lcdc.dst_split) |
| 428 | gpio_set_dir(lcd_mode_gpio.pin_id, GPIO_STATE_LOW); |
| 429 | else |
| 430 | gpio_set_dir(lcd_mode_gpio.pin_id, GPIO_STATE_HIGH); |
| 431 | } |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 432 | } else if(!target_cont_splash_screen()) { |
| 433 | gpio_set_dir(reset_gpio.pin_id, 0); |
Padmanabhan Komanduru | 3cb0766 | 2015-06-08 17:13:33 +0530 | [diff] [blame] | 434 | if (pinfo->mipi.use_enable_gpio && !platform_is_msm8956()) |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 435 | gpio_set_dir(enable_gpio.pin_id, 0); |
Padmanabhan Komanduru | 3cb0766 | 2015-06-08 17:13:33 +0530 | [diff] [blame] | 436 | if (platform_is_msm8956()) |
| 437 | gpio_set_dir(lcd_mode_gpio.pin_id, 0); |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 438 | } |
| 439 | |
| 440 | return ret; |
| 441 | } |
| 442 | |
Sandeep Panda | aa4ea2f | 2016-07-05 13:52:25 +0530 | [diff] [blame] | 443 | static int wled_init(struct msm_panel_info *pinfo) |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 444 | { |
| 445 | struct qpnp_wled_config_data config = {0}; |
| 446 | struct labibb_desc *labibb; |
| 447 | int display_type = 0; |
Vishnuvardhan Prodduturi | 4aa8dc4 | 2015-10-20 21:20:43 +0530 | [diff] [blame] | 448 | bool swire_control = 0; |
| 449 | bool wled_avdd_control = 0; |
Sandeep Panda | aa4ea2f | 2016-07-05 13:52:25 +0530 | [diff] [blame] | 450 | int rc = NO_ERROR; |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 451 | |
| 452 | labibb = pinfo->labibb; |
| 453 | |
| 454 | if (labibb) |
| 455 | display_type = labibb->amoled_panel; |
| 456 | |
Vishnuvardhan Prodduturi | 4aa8dc4 | 2015-10-20 21:20:43 +0530 | [diff] [blame] | 457 | if (display_type) { |
| 458 | swire_control = labibb->swire_control; |
| 459 | wled_avdd_control = true; |
| 460 | } else { |
| 461 | swire_control = false; |
| 462 | wled_avdd_control = false; |
| 463 | } |
| 464 | |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 465 | config.display_type = display_type; |
| 466 | config.lab_init_volt = 4600000; /* fixed, see pmi register */ |
| 467 | config.ibb_init_volt = 1400000; /* fixed, see pmi register */ |
Vishnuvardhan Prodduturi | 4aa8dc4 | 2015-10-20 21:20:43 +0530 | [diff] [blame] | 468 | config.lab_ibb_swire_control = swire_control; |
| 469 | config.wled_avdd_control = wled_avdd_control; |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 470 | |
Vishnuvardhan Prodduturi | 4aa8dc4 | 2015-10-20 21:20:43 +0530 | [diff] [blame] | 471 | if(!swire_control) { |
| 472 | if (labibb && labibb->force_config) { |
| 473 | config.lab_min_volt = labibb->lab_min_volt; |
| 474 | config.lab_max_volt = labibb->lab_max_volt; |
| 475 | config.ibb_min_volt = labibb->ibb_min_volt; |
| 476 | config.ibb_max_volt = labibb->ibb_max_volt; |
| 477 | config.pwr_up_delay = labibb->pwr_up_delay; |
| 478 | config.pwr_down_delay = labibb->pwr_down_delay; |
| 479 | config.ibb_discharge_en = labibb->ibb_discharge_en; |
| 480 | } else { |
| 481 | /* default */ |
| 482 | config.pwr_up_delay = 3; |
| 483 | config.pwr_down_delay = 3; |
| 484 | config.ibb_discharge_en = 1; |
| 485 | if (display_type) { /* amoled */ |
| 486 | config.lab_min_volt = 4600000; |
| 487 | config.lab_max_volt = 4600000; |
| 488 | config.ibb_min_volt = 4000000; |
| 489 | config.ibb_max_volt = 4000000; |
| 490 | } else { /* lcd */ |
| 491 | config.lab_min_volt = 5500000; |
| 492 | config.lab_max_volt = 5500000; |
| 493 | config.ibb_min_volt = 5500000; |
| 494 | config.ibb_max_volt = 5500000; |
| 495 | } |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 496 | } |
| 497 | } |
| 498 | |
| 499 | dprintf(SPEW, "%s: %d %d %d %d %d %d %d %d %d %d\n", __func__, |
| 500 | config.display_type, |
| 501 | config.lab_min_volt, config.lab_max_volt, |
| 502 | config.ibb_min_volt, config.ibb_max_volt, |
| 503 | config.lab_init_volt, config.ibb_init_volt, |
| 504 | config.pwr_up_delay, config.pwr_down_delay, |
| 505 | config.ibb_discharge_en); |
| 506 | |
| 507 | /* QPNP WLED init for display backlight */ |
| 508 | pm8x41_wled_config_slave_id(PMIC_WLED_SLAVE_ID); |
| 509 | |
Sandeep Panda | aa4ea2f | 2016-07-05 13:52:25 +0530 | [diff] [blame] | 510 | rc = qpnp_wled_init(&config); |
| 511 | |
| 512 | return rc; |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 513 | } |
| 514 | |
Dhaval Patel | 7709c41 | 2015-05-12 10:09:41 -0700 | [diff] [blame] | 515 | int target_dsi_phy_config(struct mdss_dsi_phy_ctrl *phy_db) |
| 516 | { |
| 517 | memcpy(phy_db->regulator, panel_regulator_settings, REGULATOR_SIZE); |
| 518 | memcpy(phy_db->ctrl, panel_physical_ctrl, PHYSICAL_SIZE); |
| 519 | memcpy(phy_db->strength, panel_strength_ctrl, STRENGTH_SIZE); |
| 520 | memcpy(phy_db->bistCtrl, panel_bist_ctrl, BIST_SIZE); |
| 521 | memcpy(phy_db->laneCfg, panel_lane_config, LANE_SIZE); |
| 522 | return NO_ERROR; |
| 523 | } |
| 524 | |
Padmanabhan Komanduru | b338193 | 2015-06-15 22:14:02 +0530 | [diff] [blame] | 525 | int target_display_get_base_offset(uint32_t base) |
| 526 | { |
Jayant Shekhar | 9c0533e | 2016-01-28 11:17:18 +0530 | [diff] [blame] | 527 | if(platform_is_msm8956() || platform_is_msm8937() || |
Parth Dixit | 05f3c9f | 2016-03-18 17:14:57 +0530 | [diff] [blame] | 528 | platform_is_msm8917()) { |
Padmanabhan Komanduru | b338193 | 2015-06-15 22:14:02 +0530 | [diff] [blame] | 529 | if (base == MIPI_DSI0_BASE) |
| 530 | return DSI0_BASE_ADJUST; |
| 531 | else if (base == DSI0_PHY_BASE) |
| 532 | return DSI0_PHY_BASE_ADJUST; |
| 533 | else if (base == DSI0_PLL_BASE) |
| 534 | return DSI0_PHY_PLL_BASE_ADJUST; |
| 535 | else if (base == DSI0_REGULATOR_BASE) |
| 536 | return DSI0_PHY_REGULATOR_BASE_ADJUST; |
| 537 | } |
| 538 | |
| 539 | return 0; |
| 540 | } |
| 541 | |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 542 | int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo) |
| 543 | { |
Sandeep Panda | aa4ea2f | 2016-07-05 13:52:25 +0530 | [diff] [blame] | 544 | int rc = 0; |
Padmanabhan Komanduru | 3cb0766 | 2015-06-08 17:13:33 +0530 | [diff] [blame] | 545 | uint32_t ldo_num = REG_LDO6 | REG_LDO17; |
| 546 | |
| 547 | if (platform_is_msm8956()) |
| 548 | ldo_num |= REG_LDO1; |
| 549 | else |
| 550 | ldo_num |= REG_LDO2; |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 551 | |
| 552 | if (enable) { |
Padmanabhan Komanduru | 3cb0766 | 2015-06-08 17:13:33 +0530 | [diff] [blame] | 553 | regulator_enable(ldo_num); |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 554 | mdelay(10); |
Sandeep Panda | aa4ea2f | 2016-07-05 13:52:25 +0530 | [diff] [blame] | 555 | rc = wled_init(pinfo); |
| 556 | if (rc) { |
| 557 | dprintf(CRITICAL, "%s: wled init failed\n", __func__); |
| 558 | return rc; |
| 559 | } |
| 560 | rc = qpnp_ibb_enable(true); /*5V boost*/ |
| 561 | if (rc) { |
| 562 | dprintf(CRITICAL, "%s: qpnp_ibb failed\n", __func__); |
| 563 | return rc; |
| 564 | } |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 565 | mdelay(50); |
| 566 | } else { |
Padmanabhan Komanduru | fa2899b | 2015-06-30 16:25:33 +0530 | [diff] [blame] | 567 | /* |
| 568 | * LDO1, LDO2 and LDO6 are shared with other subsystems. |
| 569 | * Do not disable them. |
| 570 | */ |
| 571 | regulator_disable(REG_LDO17); |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 572 | } |
| 573 | |
| 574 | return NO_ERROR; |
| 575 | } |
| 576 | |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 577 | bool target_display_panel_node(char *pbuf, uint16_t buf_size) |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 578 | { |
Ashish Garg | 9cfd6ca | 2016-12-20 01:41:54 +0530 | [diff] [blame] | 579 | int prefix_string_len = strlen(DISPLAY_CMDLINE_PREFIX); |
| 580 | bool ret = true; |
| 581 | struct oem_panel_data oem = mdss_dsi_get_oem_data(); |
| 582 | uint32_t platform_subtype = board_hardware_subtype(); |
| 583 | |
| 584 | /* default to hdmi for apq iot */ |
Parth Dixit | acec6bf | 2017-02-27 19:06:39 +0530 | [diff] [blame] | 585 | if ((HW_PLATFORM_SUBTYPE_SAP == platform_subtype) || |
| 586 | (HW_PLATFORM_SUBTYPE_SAP_NOPMI == platform_subtype)) { |
Ashish Garg | 9cfd6ca | 2016-12-20 01:41:54 +0530 | [diff] [blame] | 587 | if (!strcmp(oem.panel, "")) { |
| 588 | if (buf_size < (prefix_string_len + |
| 589 | strlen(HDMI_ADV_PANEL_STRING))) { |
| 590 | dprintf(CRITICAL, "HDMI command line argument \ |
| 591 | is greater than buffer size\n"); |
| 592 | return false; |
| 593 | } |
| 594 | strlcpy(pbuf, DISPLAY_CMDLINE_PREFIX, buf_size); |
| 595 | buf_size -= prefix_string_len; |
| 596 | pbuf += prefix_string_len; |
| 597 | strlcpy(pbuf, HDMI_ADV_PANEL_STRING, buf_size); |
| 598 | } else if (!strcmp(oem.panel, TRULY_720P_VID_PANEL)) { |
| 599 | if (buf_size < (prefix_string_len + |
| 600 | strlen(TRULY_VID_PANEL_STRING))) { |
| 601 | dprintf(CRITICAL, "TRULY VIDEO command line \ |
| 602 | argument is greater than \ |
| 603 | buffer size\n"); |
| 604 | return false; |
| 605 | } |
| 606 | strlcpy(pbuf, DISPLAY_CMDLINE_PREFIX, buf_size); |
| 607 | buf_size -= prefix_string_len; |
| 608 | pbuf += prefix_string_len; |
| 609 | strlcpy(pbuf, TRULY_VID_PANEL_STRING, buf_size); |
| 610 | } else if (!strcmp(oem.panel, TRULY_720P_CMD_PANEL)) { |
| 611 | if (buf_size < (prefix_string_len + |
| 612 | strlen(TRULY_CMD_PANEL_STRING))) { |
| 613 | dprintf(CRITICAL, "TRULY CMD command line argument \ |
| 614 | argument is greater than \ |
| 615 | buffer size\n"); |
| 616 | return false; |
| 617 | } |
| 618 | strlcpy(pbuf, DISPLAY_CMDLINE_PREFIX, buf_size); |
| 619 | buf_size -= prefix_string_len; |
| 620 | pbuf += prefix_string_len; |
| 621 | strlcpy(pbuf, TRULY_CMD_PANEL_STRING, buf_size); |
| 622 | } |
| 623 | } else { |
| 624 | ret = gcdb_display_cmdline_arg(pbuf, buf_size); |
| 625 | } |
| 626 | |
| 627 | return ret; |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 628 | } |
| 629 | |
| 630 | void target_display_init(const char *panel_name) |
| 631 | { |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 632 | struct oem_panel_data oem; |
Ray Zhang | f95f5b9 | 2015-06-25 15:34:29 +0800 | [diff] [blame] | 633 | int32_t ret = 0; |
| 634 | uint32_t panel_loop = 0; |
Ashish Garg | 9cfd6ca | 2016-12-20 01:41:54 +0530 | [diff] [blame] | 635 | uint32_t platform_subtype = board_hardware_subtype(); |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 636 | |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 637 | set_panel_cmd_string(panel_name); |
| 638 | oem = mdss_dsi_get_oem_data(); |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 639 | |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 640 | if (!strcmp(oem.panel, NO_PANEL_CONFIG) |
| 641 | || !strcmp(oem.panel, SIM_VIDEO_PANEL) |
| 642 | || !strcmp(oem.panel, SIM_CMD_PANEL) |
| 643 | || oem.skip) { |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 644 | dprintf(INFO, "Selected panel: %s\nSkip panel configuration\n", |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 645 | oem.panel); |
Vishnuvardhan Prodduturi | 4cd5638 | 2017-08-22 21:46:38 +0530 | [diff] [blame] | 646 | oem.cont_splash = false; |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 647 | } |
| 648 | |
Parth Dixit | acec6bf | 2017-02-27 19:06:39 +0530 | [diff] [blame] | 649 | if ((HW_PLATFORM_SUBTYPE_SAP == platform_subtype) || |
| 650 | (HW_PLATFORM_SUBTYPE_SAP_NOPMI == platform_subtype)) { |
Ashish Garg | 9cfd6ca | 2016-12-20 01:41:54 +0530 | [diff] [blame] | 651 | dprintf(INFO, "%s: Platform subtype %d\n", |
| 652 | __func__, platform_subtype); |
| 653 | return; |
| 654 | } |
| 655 | |
Ray Zhang | f95f5b9 | 2015-06-25 15:34:29 +0800 | [diff] [blame] | 656 | do { |
| 657 | target_force_cont_splash_disable(false); |
| 658 | ret = gcdb_display_init(oem.panel, MDP_REV_50, (void *)MIPI_FB_ADDR); |
| 659 | if (!ret || ret == ERR_NOT_SUPPORTED) { |
| 660 | break; |
| 661 | } else { |
| 662 | target_force_cont_splash_disable(true); |
| 663 | msm_display_off(); |
| 664 | } |
| 665 | } while (++panel_loop <= oem_panel_max_auto_detect_panels()); |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 666 | |
Padmanabhan Komanduru | bccbcdc | 2015-06-30 16:19:24 +0530 | [diff] [blame] | 667 | if (!oem.cont_splash) { |
Padmanabhan Komanduru | 9d49f89 | 2015-04-10 12:58:46 -0700 | [diff] [blame] | 668 | dprintf(INFO, "Forcing continuous splash disable\n"); |
| 669 | target_force_cont_splash_disable(true); |
| 670 | } |
| 671 | } |
| 672 | |
| 673 | void target_display_shutdown(void) |
| 674 | { |
| 675 | gcdb_display_shutdown(); |
| 676 | } |