Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions |
| 5 | * are met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer in |
| 10 | * the documentation and/or other materials provided with the |
| 11 | * distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 19 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 20 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 22 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
| 23 | * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
| 24 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 25 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 26 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 27 | * SUCH DAMAGE. |
| 28 | */ |
| 29 | |
| 30 | #include <debug.h> |
| 31 | #include <smem.h> |
| 32 | #include <err.h> |
| 33 | #include <msm_panel.h> |
| 34 | #include <mipi_dsi.h> |
| 35 | #include <pm8x41.h> |
| 36 | #include <pm8x41_wled.h> |
| 37 | #include <board.h> |
| 38 | #include <mdp5.h> |
| 39 | #include <scm.h> |
| 40 | #include <platform/gpio.h> |
| 41 | #include <platform/iomap.h> |
| 42 | #include <target/display.h> |
| 43 | |
| 44 | #include "include/panel.h" |
| 45 | #include "include/display_resource.h" |
| 46 | |
Padmanabhan Komanduru | dc41582 | 2014-04-01 19:29:53 +0530 | [diff] [blame] | 47 | #define DDR_LDO_ID 2 |
| 48 | #define QFPROM_LDO_ID 6 |
| 49 | |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 50 | #define GPIO_STATE_LOW 0 |
| 51 | #define GPIO_STATE_HIGH 2 |
| 52 | #define RESET_GPIO_SEQ_LEN 3 |
| 53 | #define PWM_DUTY_US 13 |
| 54 | #define PWM_PERIOD_US 27 |
| 55 | |
| 56 | static uint32_t dsi_pll_enable_seq_m(uint32_t pll_base) |
| 57 | { |
| 58 | uint32_t i = 0; |
| 59 | uint32_t pll_locked = 0; |
| 60 | |
| 61 | mdss_dsi_uniphy_pll_sw_reset(pll_base); |
| 62 | |
| 63 | /* |
| 64 | * Add hardware recommended delays between register writes for |
| 65 | * the updates to take effect. These delays are necessary for the |
| 66 | * PLL to successfully lock |
| 67 | */ |
| 68 | writel(0x01, pll_base + 0x0020); /* GLB CFG */ |
| 69 | udelay(200); |
| 70 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
| 71 | udelay(200); |
| 72 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
| 73 | udelay(1000); |
| 74 | |
| 75 | mdss_dsi_uniphy_pll_lock_detect_setting(pll_base); |
| 76 | pll_locked = readl(pll_base + 0x00c0) & 0x01; |
| 77 | for (i = 0; (i < 4) && !pll_locked; i++) { |
| 78 | writel(0x07, pll_base + 0x0020); /* GLB CFG */ |
| 79 | if (i != 0) |
| 80 | writel(0x34, pll_base + 0x00070); /* CAL CFG1*/ |
| 81 | udelay(1); |
| 82 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
| 83 | udelay(1000); |
| 84 | mdss_dsi_uniphy_pll_lock_detect_setting(pll_base); |
| 85 | pll_locked = readl(pll_base + 0x00c0) & 0x01; |
| 86 | } |
| 87 | |
| 88 | return pll_locked; |
| 89 | } |
| 90 | |
| 91 | static uint32_t dsi_pll_enable_seq_d(uint32_t pll_base) |
| 92 | { |
| 93 | uint32_t pll_locked = 0; |
| 94 | |
| 95 | mdss_dsi_uniphy_pll_sw_reset(pll_base); |
| 96 | |
| 97 | /* |
| 98 | * Add hardware recommended delays between register writes for |
| 99 | * the updates to take effect. These delays are necessary for the |
| 100 | * PLL to successfully lock |
| 101 | */ |
| 102 | writel(0x01, pll_base + 0x0020); /* GLB CFG */ |
| 103 | udelay(200); |
| 104 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
| 105 | udelay(200); |
| 106 | writel(0x07, pll_base + 0x0020); /* GLB CFG */ |
| 107 | udelay(200); |
| 108 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
| 109 | udelay(200); |
| 110 | writel(0x07, pll_base + 0x0020); /* GLB CFG */ |
| 111 | udelay(200); |
| 112 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
| 113 | udelay(1000); |
| 114 | |
| 115 | mdss_dsi_uniphy_pll_lock_detect_setting(pll_base); |
| 116 | pll_locked = readl(pll_base + 0x00c0) & 0x01; |
| 117 | |
| 118 | return pll_locked; |
| 119 | } |
| 120 | |
| 121 | static uint32_t dsi_pll_enable_seq_f1(uint32_t pll_base) |
| 122 | { |
| 123 | uint32_t pll_locked = 0; |
| 124 | |
| 125 | mdss_dsi_uniphy_pll_sw_reset(pll_base); |
| 126 | |
| 127 | /* |
| 128 | * Add hardware recommended delays between register writes for |
| 129 | * the updates to take effect. These delays are necessary for the |
| 130 | * PLL to successfully lock |
| 131 | */ |
| 132 | writel(0x01, pll_base + 0x0020); /* GLB CFG */ |
| 133 | udelay(200); |
| 134 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
| 135 | udelay(200); |
| 136 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
| 137 | udelay(200); |
| 138 | writel(0x0d, pll_base + 0x0020); /* GLB CFG */ |
| 139 | udelay(200); |
| 140 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
| 141 | udelay(1000); |
| 142 | |
| 143 | mdss_dsi_uniphy_pll_lock_detect_setting(pll_base); |
| 144 | pll_locked = readl(pll_base + 0x00c0) & 0x01; |
| 145 | |
| 146 | return pll_locked; |
| 147 | } |
| 148 | |
| 149 | static uint32_t dsi_pll_enable_seq_c(uint32_t pll_base) |
| 150 | { |
| 151 | uint32_t pll_locked = 0; |
| 152 | |
| 153 | mdss_dsi_uniphy_pll_sw_reset(pll_base); |
| 154 | |
| 155 | /* |
| 156 | * Add hardware recommended delays between register writes for |
| 157 | * the updates to take effect. These delays are necessary for the |
| 158 | * PLL to successfully lock |
| 159 | */ |
| 160 | writel(0x01, pll_base + 0x0020); /* GLB CFG */ |
| 161 | udelay(200); |
| 162 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
| 163 | udelay(200); |
| 164 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
| 165 | udelay(1000); |
| 166 | |
| 167 | mdss_dsi_uniphy_pll_lock_detect_setting(pll_base); |
| 168 | pll_locked = readl(pll_base + 0x00c0) & 0x01; |
| 169 | |
| 170 | return pll_locked; |
| 171 | } |
| 172 | |
| 173 | static uint32_t dsi_pll_enable_seq_e(uint32_t pll_base) |
| 174 | { |
| 175 | uint32_t pll_locked = 0; |
| 176 | |
| 177 | mdss_dsi_uniphy_pll_sw_reset(pll_base); |
| 178 | |
| 179 | /* |
| 180 | * Add hardware recommended delays between register writes for |
| 181 | * the updates to take effect. These delays are necessary for the |
| 182 | * PLL to successfully lock |
| 183 | */ |
| 184 | writel(0x01, pll_base + 0x0020); /* GLB CFG */ |
| 185 | udelay(200); |
| 186 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
| 187 | udelay(200); |
| 188 | writel(0x0d, pll_base + 0x0020); /* GLB CFG */ |
| 189 | udelay(1); |
| 190 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
| 191 | udelay(1000); |
| 192 | |
| 193 | mdss_dsi_uniphy_pll_lock_detect_setting(pll_base); |
| 194 | pll_locked = readl(pll_base + 0x00c0) & 0x01; |
| 195 | |
| 196 | return pll_locked; |
| 197 | } |
| 198 | |
| 199 | int target_backlight_ctrl(struct backlight *bl, uint8_t enable) |
| 200 | { |
| 201 | struct pm8x41_mpp mpp; |
| 202 | int rc; |
| 203 | |
| 204 | mpp.base = PM8x41_MMP4_BASE; |
| 205 | mpp.vin = MPP_VIN0; |
| 206 | if (enable) { |
| 207 | pm_pwm_enable(false); |
| 208 | rc = pm_pwm_config(PWM_DUTY_US, PWM_PERIOD_US); |
| 209 | if (rc < 0) |
| 210 | mpp.mode = MPP_HIGH; |
| 211 | else { |
| 212 | mpp.mode = MPP_DTEST1; |
| 213 | pm_pwm_enable(true); |
| 214 | } |
| 215 | pm8x41_config_output_mpp(&mpp); |
| 216 | pm8x41_enable_mpp(&mpp, MPP_ENABLE); |
| 217 | } else { |
| 218 | pm_pwm_enable(false); |
| 219 | pm8x41_enable_mpp(&mpp, MPP_DISABLE); |
| 220 | } |
| 221 | mdelay(20); |
| 222 | return 0; |
| 223 | } |
| 224 | |
| 225 | static void dsi_pll_enable_seq(uint32_t pll_base) |
| 226 | { |
| 227 | if (dsi_pll_enable_seq_m(pll_base)) { |
| 228 | } else if (dsi_pll_enable_seq_d(pll_base)) { |
| 229 | } else if (dsi_pll_enable_seq_d(pll_base)) { |
| 230 | } else if (dsi_pll_enable_seq_f1(pll_base)) { |
| 231 | } else if (dsi_pll_enable_seq_c(pll_base)) { |
| 232 | } else if (dsi_pll_enable_seq_e(pll_base)) { |
| 233 | } else { |
| 234 | dprintf(CRITICAL, "Not able to enable the pll\n"); |
| 235 | } |
| 236 | } |
| 237 | |
| 238 | int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo) |
| 239 | { |
| 240 | int32_t ret = 0; |
| 241 | struct mdss_dsi_pll_config *pll_data; |
| 242 | dprintf(SPEW, "target_panel_clock\n"); |
| 243 | |
| 244 | pll_data = pinfo->mipi.dsi_pll_config; |
| 245 | |
| 246 | if (enable) { |
| 247 | mdp_gdsc_ctrl(enable); |
| 248 | mdss_bus_clocks_enable(); |
| 249 | mdp_clock_enable(); |
| 250 | ret = restore_secure_cfg(SECURE_DEVICE_MDSS); |
| 251 | if (ret) { |
| 252 | dprintf(CRITICAL, |
| 253 | "%s: Failed to restore MDP security configs", |
| 254 | __func__); |
| 255 | mdp_clock_disable(); |
| 256 | mdss_bus_clocks_disable(); |
| 257 | mdp_gdsc_ctrl(0); |
| 258 | return ret; |
| 259 | } |
| 260 | mdss_dsi_auto_pll_config(DSI0_PLL_BASE, |
| 261 | MIPI_DSI0_BASE, pll_data); |
| 262 | dsi_pll_enable_seq(DSI0_PLL_BASE); |
| 263 | gcc_dsi_clocks_enable(pll_data->pclk_m, |
| 264 | pll_data->pclk_n, |
| 265 | pll_data->pclk_d); |
| 266 | } else if(!target_cont_splash_screen()) { |
| 267 | gcc_dsi_clocks_disable(); |
| 268 | mdp_clock_disable(); |
| 269 | mdss_bus_clocks_disable(); |
| 270 | mdp_gdsc_ctrl(enable); |
| 271 | } |
| 272 | |
| 273 | return 0; |
| 274 | } |
| 275 | |
| 276 | int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq, |
| 277 | struct msm_panel_info *pinfo) |
| 278 | { |
| 279 | int ret = NO_ERROR; |
Mao Flynn | 8140947 | 2014-04-10 15:01:30 +0800 | [diff] [blame^] | 280 | uint32_t hw_id = board_hardware_id(); |
| 281 | uint32_t hw_subtype = board_hardware_subtype(); |
| 282 | |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 283 | if (enable) { |
| 284 | if (pinfo->mipi.use_enable_gpio) { |
| 285 | gpio_tlmm_config(enable_gpio.pin_id, 0, |
| 286 | enable_gpio.pin_direction, enable_gpio.pin_pull, |
| 287 | enable_gpio.pin_strength, |
| 288 | enable_gpio.pin_state); |
| 289 | |
| 290 | gpio_set_dir(enable_gpio.pin_id, 2); |
| 291 | } |
| 292 | |
Mao Flynn | 8140947 | 2014-04-10 15:01:30 +0800 | [diff] [blame^] | 293 | if(hw_id == HW_PLATFORM_QRD && |
| 294 | hw_subtype == HW_PLATFORM_SUBTYPE_SKUH) { |
| 295 | /* for tps65132 ENP */ |
| 296 | gpio_tlmm_config(enp_gpio.pin_id, 0, |
| 297 | enp_gpio.pin_direction, enp_gpio.pin_pull, |
| 298 | enp_gpio.pin_strength, |
| 299 | enp_gpio.pin_state); |
| 300 | gpio_set_dir(enp_gpio.pin_id, 2); |
| 301 | |
| 302 | /* for tps65132 ENN */ |
| 303 | gpio_tlmm_config(enn_gpio.pin_id, 0, |
| 304 | enn_gpio.pin_direction, enn_gpio.pin_pull, |
| 305 | enn_gpio.pin_strength, |
| 306 | enn_gpio.pin_state); |
| 307 | gpio_set_dir(enn_gpio.pin_id, 2); |
| 308 | } |
| 309 | |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 310 | gpio_tlmm_config(bkl_gpio.pin_id, 0, |
| 311 | bkl_gpio.pin_direction, bkl_gpio.pin_pull, |
| 312 | bkl_gpio.pin_strength, bkl_gpio.pin_state); |
| 313 | gpio_set_dir(bkl_gpio.pin_id, 2); |
| 314 | |
| 315 | gpio_tlmm_config(reset_gpio.pin_id, 0, |
| 316 | reset_gpio.pin_direction, reset_gpio.pin_pull, |
| 317 | reset_gpio.pin_strength, reset_gpio.pin_state); |
| 318 | |
| 319 | gpio_set_dir(reset_gpio.pin_id, 2); |
| 320 | |
| 321 | /* reset */ |
| 322 | for (int i = 0; i < RESET_GPIO_SEQ_LEN; i++) { |
| 323 | if (resetseq->pin_state[i] == GPIO_STATE_LOW) |
| 324 | gpio_set_dir(reset_gpio.pin_id, GPIO_STATE_LOW); |
| 325 | else |
| 326 | gpio_set_dir(reset_gpio.pin_id, GPIO_STATE_HIGH); |
| 327 | mdelay(resetseq->sleep[i]); |
| 328 | } |
| 329 | } else if(!target_cont_splash_screen()) { |
| 330 | gpio_set_dir(reset_gpio.pin_id, 0); |
| 331 | if (pinfo->mipi.use_enable_gpio) |
| 332 | gpio_set_dir(enable_gpio.pin_id, 0); |
Mao Flynn | 8140947 | 2014-04-10 15:01:30 +0800 | [diff] [blame^] | 333 | |
| 334 | if(hw_id == HW_PLATFORM_QRD && |
| 335 | hw_subtype == HW_PLATFORM_SUBTYPE_SKUH) { |
| 336 | gpio_set_dir(enp_gpio.pin_id, 0); /* ENP */ |
| 337 | gpio_set_dir(enn_gpio.pin_id, 0); /* ENN */ |
| 338 | } |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 339 | } |
| 340 | |
| 341 | return ret; |
| 342 | } |
| 343 | |
| 344 | int target_ldo_ctrl(uint8_t enable) |
| 345 | { |
| 346 | uint32_t ret = NO_ERROR; |
| 347 | uint32_t ldocounter = 0; |
| 348 | uint32_t pm8x41_ldo_base = 0x13F00; |
| 349 | |
| 350 | while (ldocounter < TOTAL_LDO_DEFINED) { |
| 351 | dprintf(SPEW, "Setting %i\n", |
| 352 | ldo_entry_array[ldocounter].ldo_id); |
| 353 | struct pm8x41_ldo ldo_entry = LDO((pm8x41_ldo_base + |
| 354 | 0x100 * ldo_entry_array[ldocounter].ldo_id), |
| 355 | ldo_entry_array[ldocounter].ldo_type); |
| 356 | |
| 357 | |
| 358 | /* Set voltage during power on */ |
| 359 | if (enable) { |
| 360 | /* TODO: Set the LDO voltage before enabling it */ |
| 361 | pm8x41_ldo_control(&ldo_entry, enable); |
| 362 | |
Padmanabhan Komanduru | dc41582 | 2014-04-01 19:29:53 +0530 | [diff] [blame] | 363 | } else if(!target_cont_splash_screen() && |
| 364 | ldo_entry_array[ldocounter].ldo_id != DDR_LDO_ID && |
| 365 | ldo_entry_array[ldocounter].ldo_id != QFPROM_LDO_ID) { |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 366 | pm8x41_ldo_control(&ldo_entry, enable); |
| 367 | } |
| 368 | ldocounter++; |
| 369 | } |
| 370 | |
| 371 | return ret; |
| 372 | } |
| 373 | |
| 374 | bool target_display_panel_node(char *panel_name, char *pbuf, uint16_t buf_size) |
| 375 | { |
| 376 | return gcdb_display_cmdline_arg(pbuf, buf_size); |
| 377 | } |
| 378 | |
| 379 | void target_display_init(const char *panel_name) |
| 380 | { |
Padmanabhan Komanduru | 1869a76 | 2014-04-01 20:12:05 +0530 | [diff] [blame] | 381 | uint32_t panel_loop = 0; |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 382 | uint32_t ret = 0; |
Padmanabhan Komanduru | 1869a76 | 2014-04-01 20:12:05 +0530 | [diff] [blame] | 383 | do { |
| 384 | ret = gcdb_display_init(panel_name, MDP_REV_50, MIPI_FB_ADDR); |
| 385 | if (!ret || ret == ERR_NOT_SUPPORTED) { |
| 386 | break; |
| 387 | } else { |
| 388 | target_force_cont_splash_disable(true); |
| 389 | msm_display_off(); |
| 390 | target_force_cont_splash_disable(false); |
| 391 | } |
| 392 | } while (++panel_loop <= oem_panel_max_auto_detect_panels()); |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 393 | } |
| 394 | |
| 395 | void target_display_shutdown(void) |
| 396 | { |
| 397 | gcdb_display_shutdown(); |
| 398 | } |