Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2011-2014, The Linux Foundation. All rights reserved. |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
Duy Truong | f3ac7b3 | 2013-02-13 01:07:28 -0800 | [diff] [blame] | 12 | * * Neither the name of The Linux Foundation nor the names of its |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | * |
| 28 | */ |
| 29 | #include <mdp4.h> |
| 30 | #include <debug.h> |
| 31 | #include <reg.h> |
| 32 | #include <target/display.h> |
| 33 | #include <platform/timer.h> |
| 34 | #include <platform/iomap.h> |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 35 | #include <dev/lcdc.h> |
| 36 | #include <dev/fbcon.h> |
| 37 | #include <bits.h> |
| 38 | #include <msm_panel.h> |
| 39 | #include <mipi_dsi.h> |
| 40 | #include <err.h> |
Amir Samuelov | 2d4ba16 | 2012-07-22 11:53:14 +0300 | [diff] [blame] | 41 | #include <clock.h> |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 42 | |
| 43 | static int mdp_rev; |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 44 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 45 | void |
| 46 | mdp_setup_dma_p_video_config(unsigned short pack_pattern, |
| 47 | unsigned short img_width, |
| 48 | unsigned short img_height, |
| 49 | unsigned long input_img_addr, |
| 50 | unsigned short img_width_full_size, |
| 51 | unsigned char ystride) |
| 52 | { |
| 53 | dprintf(SPEW, "MDP4.2 Setup for DSI Video Mode\n"); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 54 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 55 | // ----- programming MDP_AXI_RDMASTER_CONFIG -------- |
| 56 | /* MDP_AXI_RDMASTER_CONFIG set all master to read from AXI port 0, that's |
| 57 | the only port connected */ |
| 58 | //TODO: Seems to still work without this |
| 59 | writel(0x00290000, MDP_AXI_RDMASTER_CONFIG); |
| 60 | writel(0x00000004, MDP_AXI_WRMASTER_CONFIG); |
| 61 | writel(0x00007777, MDP_MAX_RD_PENDING_CMD_CONFIG); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 62 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 63 | /* Set up CMD_INTF_SEL, VIDEO_INTF_SEL, EXT_INTF_SEL, SEC_INTF_SEL, PRIM_INTF_SEL */ |
| 64 | writel(0x00000049, MDP_DISP_INTF_SEL); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 65 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 66 | /* DMA P */ |
| 67 | writel(0x0000000b, MDP_OVERLAYPROC0_CFG); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 68 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 69 | /* RGB 888 */ |
| 70 | writel(pack_pattern << 8 | 0xbf | (0 << 25), MDP_DMA_P_CONFIG); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 71 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 72 | writel(0x0, MDP_DMA_P_OUT_XY); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 73 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 74 | writel(img_height << 16 | img_width, MDP_DMA_P_SIZE); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 75 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 76 | writel(input_img_addr, MDP_DMA_P_BUF_ADDR); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 77 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 78 | writel(img_width_full_size * ystride, MDP_DMA_P_BUF_Y_STRIDE); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 79 | } |
| 80 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 81 | int |
| 82 | mdp_setup_dma_p_video_mode(unsigned short disp_width, |
| 83 | unsigned short disp_height, |
| 84 | unsigned short img_width, |
| 85 | unsigned short img_height, |
| 86 | unsigned short hsync_porch0_fp, |
| 87 | unsigned short hsync_porch0_bp, |
| 88 | unsigned short vsync_porch0_fp, |
| 89 | unsigned short vsync_porch0_bp, |
| 90 | unsigned short hsync_width, |
| 91 | unsigned short vsync_width, |
| 92 | unsigned long input_img_addr, |
| 93 | unsigned short img_width_full_size, |
| 94 | unsigned short pack_pattern, unsigned char ystride) |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 95 | { |
| 96 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 97 | // unsigned long mdp_intr_status; |
| 98 | int status = FAIL; |
| 99 | unsigned long hsync_period; |
| 100 | unsigned long vsync_period; |
| 101 | unsigned long vsync_period_intmd; |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 102 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 103 | dprintf(SPEW, "MDP4.1 for DSI Video Mode\n"); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 104 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 105 | hsync_period = img_width + hsync_porch0_fp + hsync_porch0_bp + 1; |
| 106 | vsync_period_intmd = img_height + vsync_porch0_fp + vsync_porch0_bp + 1; |
| 107 | vsync_period = vsync_period_intmd * hsync_period; |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 108 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 109 | // ----- programming MDP_AXI_RDMASTER_CONFIG -------- |
| 110 | /* MDP_AXI_RDMASTER_CONFIG set all master to read from AXI port 0, that's |
| 111 | the only port connected */ |
| 112 | writel(0x00290000, MDP_AXI_RDMASTER_CONFIG); |
| 113 | writel(0x00000004, MDP_AXI_WRMASTER_CONFIG); |
| 114 | writel(0x00007777, MDP_MAX_RD_PENDING_CMD_CONFIG); |
| 115 | /* sets PRIM_INTF_SEL to 0x1 and SEC_INTF_SEL to 0x2 and DSI_VIDEO_INTF_SEL */ |
| 116 | writel(0x00000049, MDP_DISP_INTF_SEL); |
| 117 | writel(0x0000000b, MDP_OVERLAYPROC0_CFG); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 118 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 119 | // ------------- programming MDP_DMA_P_CONFIG --------------------- |
| 120 | writel(pack_pattern << 8 | 0xbf | (0 << 25), MDP_DMA_P_CONFIG); // rgb888 |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 121 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 122 | writel(0x00000000, MDP_DMA_P_OUT_XY); |
| 123 | writel(img_height << 16 | img_width, MDP_DMA_P_SIZE); |
| 124 | writel(input_img_addr, MDP_DMA_P_BUF_ADDR); |
| 125 | writel(img_width_full_size * ystride, MDP_DMA_P_BUF_Y_STRIDE); |
| 126 | writel(0x00ff0000, MDP_DMA_P_OP_MODE); |
| 127 | writel(hsync_period << 16 | hsync_width, MDP_DSI_VIDEO_HSYNC_CTL); |
| 128 | writel(vsync_period, MDP_DSI_VIDEO_VSYNC_PERIOD); |
| 129 | writel(vsync_width * hsync_period, MDP_DSI_VIDEO_VSYNC_PULSE_WIDTH); |
| 130 | writel((img_width + hsync_porch0_bp - 1) << 16 | hsync_porch0_bp, |
| 131 | MDP_DSI_VIDEO_DISPLAY_HCTL); |
| 132 | writel(vsync_porch0_bp * hsync_period, MDP_DSI_VIDEO_DISPLAY_V_START); |
| 133 | writel((img_height + vsync_porch0_bp) * hsync_period, |
| 134 | MDP_DSI_VIDEO_DISPLAY_V_END); |
| 135 | writel(0x00ABCDEF, MDP_DSI_VIDEO_BORDER_CLR); |
| 136 | writel(0x00000000, MDP_DSI_VIDEO_HSYNC_SKEW); |
| 137 | writel(0x00000000, MDP_DSI_VIDEO_CTL_POLARITY); |
| 138 | // end of cmd mdp |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 139 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 140 | writel(0x00000001, MDP_DSI_VIDEO_EN); // MDP_DSI_EN ENABLE |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 141 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 142 | status = PASS; |
| 143 | return status; |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 144 | } |
| 145 | |
Channagoud Kadabi | 10189fd | 2012-05-25 13:33:39 +0530 | [diff] [blame] | 146 | int mdp_dsi_cmd_config(struct msm_panel_info *pinfo, |
| 147 | struct fbcon_config *fb) |
| 148 | { |
| 149 | |
| 150 | int ret = 0; |
| 151 | unsigned long input_img_addr = MIPI_FB_ADDR; |
| 152 | unsigned short image_wd = pinfo->xres; |
| 153 | unsigned short image_ht = pinfo->yres; |
| 154 | unsigned short pack_pattern = 0x12; |
| 155 | unsigned char ystride = 3; |
| 156 | |
| 157 | writel(0x03ffffff, MDP_INTR_ENABLE); |
| 158 | writel(0x0000000b, MDP_OVERLAYPROC0_CFG); |
| 159 | |
| 160 | // ------------- programming MDP_DMA_P_CONFIG --------------------- |
| 161 | writel(pack_pattern << 8 | 0x3f | (0 << 25), MDP_DMA_P_CONFIG); // rgb888 |
| 162 | |
| 163 | writel(0x00000000, MDP_DMA_P_OUT_XY); |
| 164 | writel(image_ht << 16 | image_wd, MDP_DMA_P_SIZE); |
| 165 | writel(input_img_addr, MDP_DMA_P_BUF_ADDR); |
| 166 | |
| 167 | writel(image_wd * ystride, MDP_DMA_P_BUF_Y_STRIDE); |
| 168 | |
| 169 | writel(0x00000000, MDP_DMA_P_OP_MODE); |
| 170 | |
| 171 | writel(0x10, MDP_DSI_CMD_MODE_ID_MAP); |
| 172 | writel(0x01, MDP_DSI_CMD_MODE_TRIGGER_EN); |
| 173 | |
| 174 | writel(0x0001a000, MDP_AXI_RDMASTER_CONFIG); |
| 175 | writel(0x00000004, MDP_AXI_WRMASTER_CONFIG); |
| 176 | writel(0x00007777, MDP_MAX_RD_PENDING_CMD_CONFIG); |
| 177 | writel(0x8a, MDP_DISP_INTF_SEL); |
| 178 | |
| 179 | return ret; |
| 180 | } |
| 181 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 182 | int |
| 183 | mipi_dsi_cmd_config(struct fbcon_config mipi_fb_cfg, |
| 184 | unsigned short num_of_lanes) |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 185 | { |
| 186 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 187 | int status = 0; |
| 188 | unsigned long input_img_addr = MIPI_FB_ADDR; |
| 189 | unsigned short image_wd = mipi_fb_cfg.width; |
| 190 | unsigned short image_ht = mipi_fb_cfg.height; |
| 191 | unsigned short pack_pattern = 0x12; |
| 192 | unsigned char ystride = 3; |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 193 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 194 | writel(0x03ffffff, MDP_INTR_ENABLE); |
| 195 | writel(0x0000000b, MDP_OVERLAYPROC0_CFG); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 196 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 197 | // ------------- programming MDP_DMA_P_CONFIG --------------------- |
| 198 | writel(pack_pattern << 8 | 0x3f | (0 << 25), MDP_DMA_P_CONFIG); // rgb888 |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 199 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 200 | writel(0x00000000, MDP_DMA_P_OUT_XY); |
| 201 | writel(image_ht << 16 | image_wd, MDP_DMA_P_SIZE); |
| 202 | writel(input_img_addr, MDP_DMA_P_BUF_ADDR); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 203 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 204 | writel(image_wd * ystride, MDP_DMA_P_BUF_Y_STRIDE); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 205 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 206 | writel(0x00000000, MDP_DMA_P_OP_MODE); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 207 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 208 | writel(0x10, MDP_DSI_CMD_MODE_ID_MAP); |
| 209 | writel(0x01, MDP_DSI_CMD_MODE_TRIGGER_EN); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 210 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 211 | writel(0x0001a000, MDP_AXI_RDMASTER_CONFIG); |
| 212 | writel(0x00000004, MDP_AXI_WRMASTER_CONFIG); |
| 213 | writel(0x00007777, MDP_MAX_RD_PENDING_CMD_CONFIG); |
| 214 | writel(0x8a, MDP_DISP_INTF_SEL); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 215 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 216 | return status; |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 217 | } |
| 218 | |
| 219 | void mdp_disable(void) |
| 220 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 221 | writel(0x00000000, MDP_DSI_VIDEO_EN); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 222 | } |
| 223 | |
| 224 | void mdp_shutdown(void) |
| 225 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 226 | mdp_disable(); |
| 227 | mdelay(60); |
| 228 | writel(0x00000000, MDP_INTR_ENABLE); |
| 229 | writel(0x00000003, MDP_OVERLAYPROC0_CFG); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 230 | } |
| 231 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 232 | int mdp_dma_on(struct msm_panel_info *pinfo) |
Channagoud Kadabi | 10189fd | 2012-05-25 13:33:39 +0530 | [diff] [blame] | 233 | { |
| 234 | int ret = 0; |
| 235 | |
| 236 | writel(0x00000001, MDP_DMA_P_START); |
| 237 | |
| 238 | return ret; |
| 239 | } |
| 240 | |
| 241 | int mdp_dma_off(void) |
| 242 | { |
| 243 | int ret = 0; |
| 244 | |
| 245 | writel(0x00000000, MDP_DMA_P_START); |
| 246 | |
| 247 | return ret; |
| 248 | } |
| 249 | |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 250 | void mdp_start_dma(void) |
| 251 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 252 | writel(0x00000001, MDP_DMA_P_START); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 253 | } |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 254 | |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 255 | |
| 256 | int mdp_dsi_video_config(struct msm_panel_info *pinfo, |
| 257 | struct fbcon_config *fb) |
| 258 | { |
| 259 | int ret = NO_ERROR; |
| 260 | int hsync_period, vsync_period; |
| 261 | int hsync_start_x, hsync_end_x; |
| 262 | int display_hctl, display_vstart, display_vend; |
| 263 | struct lcdc_panel_info *lcdc = NULL; |
| 264 | unsigned mdp_rgb_size; |
| 265 | |
| 266 | if (pinfo == NULL) |
| 267 | return ERR_INVALID_ARGS; |
| 268 | |
| 269 | lcdc = &(pinfo->lcdc); |
| 270 | if (lcdc == NULL) |
| 271 | return ERR_INVALID_ARGS; |
| 272 | |
| 273 | hsync_period = lcdc->h_pulse_width + |
| 274 | lcdc->h_back_porch + |
| 275 | pinfo->xres + lcdc->xres_pad + lcdc->h_front_porch; |
| 276 | vsync_period = (lcdc->v_pulse_width + |
| 277 | lcdc->v_back_porch + |
| 278 | pinfo->yres + lcdc->yres_pad + |
| 279 | lcdc->v_front_porch) * hsync_period; |
| 280 | hsync_start_x = |
| 281 | lcdc->h_pulse_width + |
| 282 | lcdc->h_back_porch; |
| 283 | hsync_end_x = |
| 284 | hsync_period - lcdc->h_front_porch - 1; |
| 285 | display_hctl = (hsync_end_x << 16) | hsync_start_x; |
| 286 | display_vstart = (lcdc->v_pulse_width + |
| 287 | lcdc->v_back_porch) |
| 288 | * hsync_period + lcdc->hsync_skew; |
| 289 | display_vend = vsync_period - |
| 290 | (lcdc->v_front_porch * hsync_period) |
| 291 | +lcdc->hsync_skew - 1; |
| 292 | |
| 293 | /* MDP_AXI_RDMASTER_CONFIG set all master to read from |
| 294 | AXI port 0, that's the only port connected */ |
| 295 | writel(0x00290000, MDP_AXI_RDMASTER_CONFIG); |
| 296 | writel(0x00000004, MDP_AXI_WRMASTER_CONFIG); |
| 297 | writel(0x00007777, MDP_MAX_RD_PENDING_CMD_CONFIG); |
| 298 | |
| 299 | /* Set up CMD_INTF_SEL, VIDEO_INTF_SEL, |
| 300 | EXT_INTF_SEL, SEC_INTF_SEL, PRIM_INTF_SEL */ |
| 301 | writel(0x00000049, MDP_DISP_INTF_SEL); |
| 302 | |
| 303 | /* DMA P */ |
| 304 | writel(0x0000000b, MDP_OVERLAYPROC0_CFG); |
| 305 | |
| 306 | /* write fb addr in MDP_DMA_P_BUF_ADDR */ |
| 307 | writel(fb->base, MDP_DMA_P_BUF_ADDR); |
| 308 | |
| 309 | /* write active region size*/ |
| 310 | mdp_rgb_size = (fb->height << 16) + fb->width; |
| 311 | writel(mdp_rgb_size, MDP_DMA_P_SIZE); |
| 312 | |
| 313 | /* set Y-stride value in bytes */ |
| 314 | /* Y-stride is defined as the number of bytes |
| 315 | in a line. |
| 316 | */ |
| 317 | writel((fb->stride * fb->bpp/8), MDP_DMA_P_BUF_Y_STRIDE); |
| 318 | |
| 319 | /* Start XY coordinates */ |
| 320 | writel(0, MDP_DMA_P_OUT_XY); |
| 321 | |
| 322 | if (fb->bpp == 16) { |
| 323 | writel(DMA_PACK_ALIGN_LSB | DMA_PACK_PATTERN_RGB | |
| 324 | DMA_DITHER_EN | DMA_OUT_SEL_LCDC | |
| 325 | DMA_IBUF_FORMAT_RGB565 | DMA_DSTC0G_8BITS | |
| 326 | DMA_DSTC1B_8BITS | DMA_DSTC2R_8BITS, |
| 327 | MDP_DMA_P_CONFIG); |
| 328 | } else if (fb->bpp == 24) { |
| 329 | writel(DMA_PACK_ALIGN_LSB | DMA_PACK_PATTERN_RGB | |
| 330 | DMA_DITHER_EN | DMA_OUT_SEL_LCDC | |
| 331 | DMA_IBUF_FORMAT_RGB888 | DMA_DSTC0G_8BITS | |
| 332 | DMA_DSTC1B_8BITS | DMA_DSTC2R_8BITS, |
| 333 | MDP_DMA_P_CONFIG); |
| 334 | } else { |
| 335 | dprintf(CRITICAL, "Unsupported bpp detected!\n"); |
| 336 | return ERR_INVALID_ARGS; |
| 337 | } |
| 338 | |
| 339 | writel(hsync_period << 16 | lcdc->h_pulse_width, |
| 340 | MDP_DSI_VIDEO_HSYNC_CTL); |
| 341 | writel(vsync_period, MDP_DSI_VIDEO_VSYNC_PERIOD); |
| 342 | writel(lcdc->v_pulse_width * hsync_period, |
| 343 | MDP_DSI_VIDEO_VSYNC_PULSE_WIDTH); |
| 344 | writel(display_hctl, |
| 345 | MDP_DSI_VIDEO_DISPLAY_HCTL); |
| 346 | writel(display_vstart, MDP_DSI_VIDEO_DISPLAY_V_START); |
| 347 | writel(display_vend, MDP_DSI_VIDEO_DISPLAY_V_END); |
| 348 | |
| 349 | if (lcdc->xres_pad) { |
| 350 | writel((1 << 31) | |
| 351 | (lcdc->h_back_porch + lcdc->h_pulse_width + |
| 352 | fb->width - 1) << 16 | lcdc->h_pulse_width + |
| 353 | lcdc->h_back_porch, MDP_DSI_VIDEO_ACTIVE_HCTL); |
| 354 | } |
| 355 | |
Amir Samuelov | 2d4ba16 | 2012-07-22 11:53:14 +0300 | [diff] [blame] | 356 | if (pinfo->mipi.force_clk_lane_hs) { |
| 357 | uint32_t tmp; |
| 358 | |
| 359 | tmp = readl_relaxed(MIPI_DSI_BASE + 0xA8); |
| 360 | tmp |= (1<<28); |
| 361 | writel_relaxed(tmp, MIPI_DSI_BASE + 0xA8); |
| 362 | } |
| 363 | |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 364 | return ret; |
| 365 | } |
| 366 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 367 | int mdp_dsi_video_on(struct msm_panel_info *pinfo) |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 368 | { |
| 369 | int ret = NO_ERROR; |
| 370 | |
| 371 | writel(0x00000001, MDP_DSI_VIDEO_EN); |
| 372 | |
| 373 | return ret; |
| 374 | } |
| 375 | |
| 376 | int mdp_dsi_video_off() |
| 377 | { |
Amol Jadi | 6834f1a | 2012-06-29 14:42:59 -0700 | [diff] [blame] | 378 | if(!target_cont_splash_screen()) |
| 379 | { |
| 380 | writel(0x00000000, MDP_DSI_VIDEO_EN); |
| 381 | mdelay(60); |
| 382 | writel(0x00000000, MDP_INTR_ENABLE); |
| 383 | writel(0x00000003, MDP_OVERLAYPROC0_CFG); |
| 384 | } |
| 385 | |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 386 | return NO_ERROR; |
| 387 | } |
| 388 | |
Channagoud Kadabi | 10189fd | 2012-05-25 13:33:39 +0530 | [diff] [blame] | 389 | int mdp_dsi_cmd_off() |
| 390 | { |
| 391 | mdp_dma_off(); |
| 392 | /* |
| 393 | * Allow sometime for the DMA channel to |
| 394 | * stop the data transfer |
| 395 | */ |
| 396 | mdelay(10); |
| 397 | writel(0x00000000, MDP_INTR_ENABLE); |
| 398 | writel(0x00000003, MDP_OVERLAYPROC0_CFG); |
| 399 | return NO_ERROR; |
| 400 | } |
| 401 | |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 402 | void mdp_set_revision(int rev) |
| 403 | { |
| 404 | mdp_rev = rev; |
| 405 | } |
| 406 | |
| 407 | int mdp_get_revision() |
| 408 | { |
| 409 | return mdp_rev; |
| 410 | } |
Asaf Penso | 6c58a6b | 2013-07-14 19:57:29 +0300 | [diff] [blame] | 411 | |
| 412 | int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb) |
| 413 | { |
| 414 | return NO_ERROR; |
| 415 | } |
| 416 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 417 | int mdp_edp_on(struct msm_panel_info *pinfo) |
Asaf Penso | 6c58a6b | 2013-07-14 19:57:29 +0300 | [diff] [blame] | 418 | { |
| 419 | return NO_ERROR; |
| 420 | } |
| 421 | |
| 422 | int mdp_edp_off(void) |
| 423 | { |
| 424 | return NO_ERROR; |
| 425 | } |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 426 | |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 427 | int mdss_hdmi_config(struct msm_panel_info *pinfo, struct fbcon_config *fb) |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 428 | { |
| 429 | return NO_ERROR; |
| 430 | } |
| 431 | |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 432 | int mdss_hdmi_on(struct msm_panel_info *pinfo) |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 433 | { |
| 434 | return NO_ERROR; |
| 435 | } |
| 436 | |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 437 | int mdss_hdmi_off(void) |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 438 | { |
| 439 | return NO_ERROR; |
| 440 | } |