Aparna Mallavarapu | fe1f3d1 | 2013-10-19 15:05:30 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2014, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <debug.h> |
| 30 | #include <platform/iomap.h> |
| 31 | #include <reg.h> |
| 32 | #include <target.h> |
| 33 | #include <platform.h> |
| 34 | #include <uart_dm.h> |
| 35 | #include <mmc.h> |
Aparna Mallavarapu | 7cc5a79 | 2014-02-27 21:49:59 -0800 | [diff] [blame] | 36 | #include <platform/gpio.h> |
| 37 | #include <dev/keys.h> |
| 38 | #include <spmi_v2.h> |
| 39 | #include <pm8x41.h> |
Aparna Mallavarapu | fe1f3d1 | 2013-10-19 15:05:30 +0530 | [diff] [blame] | 40 | #include <board.h> |
Aparna Mallavarapu | 7cc5a79 | 2014-02-27 21:49:59 -0800 | [diff] [blame] | 41 | #include <baseband.h> |
| 42 | #include <hsusb.h> |
Aparna Mallavarapu | acb6ede | 2014-03-21 19:22:00 +0530 | [diff] [blame] | 43 | #include <scm.h> |
Aparna Mallavarapu | 7cc5a79 | 2014-02-27 21:49:59 -0800 | [diff] [blame] | 44 | #include <platform/gpio.h> |
| 45 | #include <platform/gpio.h> |
| 46 | #include <platform/irqs.h> |
Aparna Mallavarapu | fe1f3d1 | 2013-10-19 15:05:30 +0530 | [diff] [blame] | 47 | |
| 48 | #define PMIC_ARB_CHANNEL_NUM 0 |
| 49 | #define PMIC_ARB_OWNER_ID 0 |
Aparna Mallavarapu | 7cc5a79 | 2014-02-27 21:49:59 -0800 | [diff] [blame] | 50 | #define TLMM_VOL_UP_BTN_GPIO 107 |
Aparna Mallavarapu | fe1f3d1 | 2013-10-19 15:05:30 +0530 | [diff] [blame] | 51 | |
Aparna Mallavarapu | acb6ede | 2014-03-21 19:22:00 +0530 | [diff] [blame] | 52 | #define FASTBOOT_MODE 0x77665500 |
| 53 | |
Aparna Mallavarapu | 7cc5a79 | 2014-02-27 21:49:59 -0800 | [diff] [blame] | 54 | static void set_sdc_power_ctrl(void); |
| 55 | |
| 56 | struct mmc_device *dev; |
| 57 | |
| 58 | static uint32_t mmc_pwrctl_base[] = |
Aparna Mallavarapu | fe1f3d1 | 2013-10-19 15:05:30 +0530 | [diff] [blame] | 59 | { MSM_SDC1_BASE, MSM_SDC2_BASE }; |
| 60 | |
Aparna Mallavarapu | 7cc5a79 | 2014-02-27 21:49:59 -0800 | [diff] [blame] | 61 | static uint32_t mmc_sdhci_base[] = |
| 62 | { MSM_SDC1_SDHCI_BASE, MSM_SDC2_SDHCI_BASE }; |
| 63 | |
| 64 | static uint32_t mmc_sdc_pwrctl_irq[] = |
| 65 | { SDCC1_PWRCTL_IRQ, SDCC2_PWRCTL_IRQ }; |
| 66 | |
Aparna Mallavarapu | fe1f3d1 | 2013-10-19 15:05:30 +0530 | [diff] [blame] | 67 | void target_early_init(void) |
| 68 | { |
| 69 | #if WITH_DEBUG_UART |
Aparna Mallavarapu | 7cc5a79 | 2014-02-27 21:49:59 -0800 | [diff] [blame] | 70 | uart_dm_init(2, 0, BLSP1_UART1_BASE); |
Aparna Mallavarapu | fe1f3d1 | 2013-10-19 15:05:30 +0530 | [diff] [blame] | 71 | #endif |
| 72 | } |
Aparna Mallavarapu | 7cc5a79 | 2014-02-27 21:49:59 -0800 | [diff] [blame] | 73 | |
| 74 | void target_sdc_init() |
Aparna Mallavarapu | fe1f3d1 | 2013-10-19 15:05:30 +0530 | [diff] [blame] | 75 | { |
Aparna Mallavarapu | 7cc5a79 | 2014-02-27 21:49:59 -0800 | [diff] [blame] | 76 | struct mmc_config_data config; |
| 77 | |
| 78 | /* Set drive strength & pull ctrl values */ |
| 79 | set_sdc_power_ctrl(); |
| 80 | |
| 81 | config.bus_width = DATA_BUS_WIDTH_8BIT; |
Aparna Mallavarapu | 53b0940 | 2014-03-26 14:46:43 +0530 | [diff] [blame] | 82 | config.max_clk_rate = MMC_CLK_177MHZ; |
Aparna Mallavarapu | 7cc5a79 | 2014-02-27 21:49:59 -0800 | [diff] [blame] | 83 | |
| 84 | /* Try slot 1*/ |
| 85 | config.slot = 1; |
| 86 | config.sdhc_base = mmc_sdhci_base[config.slot - 1]; |
| 87 | config.pwrctl_base = mmc_pwrctl_base[config.slot - 1]; |
| 88 | config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1]; |
| 89 | config.hs400_support = 0; |
| 90 | |
| 91 | if (!(dev = mmc_init(&config))) { |
| 92 | /* Try slot 2 */ |
| 93 | config.slot = 2; |
Aparna Mallavarapu | 53b0940 | 2014-03-26 14:46:43 +0530 | [diff] [blame] | 94 | config.max_clk_rate = MMC_CLK_200MHZ; |
Aparna Mallavarapu | 7cc5a79 | 2014-02-27 21:49:59 -0800 | [diff] [blame] | 95 | config.sdhc_base = mmc_sdhci_base[config.slot - 1]; |
| 96 | config.pwrctl_base = mmc_pwrctl_base[config.slot - 1]; |
| 97 | config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1]; |
| 98 | |
| 99 | if (!(dev = mmc_init(&config))) { |
| 100 | dprintf(CRITICAL, "mmc init failed!"); |
| 101 | ASSERT(0); |
| 102 | } |
| 103 | } |
Aparna Mallavarapu | fe1f3d1 | 2013-10-19 15:05:30 +0530 | [diff] [blame] | 104 | } |
Aparna Mallavarapu | 7cc5a79 | 2014-02-27 21:49:59 -0800 | [diff] [blame] | 105 | |
| 106 | void *target_mmc_device() |
| 107 | { |
| 108 | return (void *) dev; |
| 109 | } |
| 110 | |
| 111 | /* Return 1 if vol_up pressed */ |
| 112 | static int target_volume_up() |
| 113 | { |
| 114 | uint8_t status = 0; |
| 115 | |
| 116 | gpio_tlmm_config(TLMM_VOL_UP_BTN_GPIO, 0, GPIO_INPUT, GPIO_PULL_UP, GPIO_2MA, GPIO_ENABLE); |
| 117 | |
| 118 | /* Wait for the gpio config to take effect - debounce time */ |
| 119 | thread_sleep(10); |
| 120 | |
| 121 | /* Get status of GPIO */ |
| 122 | status = gpio_status(TLMM_VOL_UP_BTN_GPIO); |
| 123 | |
| 124 | /* Active low signal. */ |
| 125 | return !status; |
| 126 | } |
| 127 | |
| 128 | /* Return 1 if vol_down pressed */ |
| 129 | uint32_t target_volume_down() |
| 130 | { |
| 131 | /* Volume down button tied in with PMIC RESIN. */ |
| 132 | return pm8x41_resin_status(); |
| 133 | } |
| 134 | |
Aparna Mallavarapu | fe1f3d1 | 2013-10-19 15:05:30 +0530 | [diff] [blame] | 135 | static void target_keystatus() |
| 136 | { |
Aparna Mallavarapu | 7cc5a79 | 2014-02-27 21:49:59 -0800 | [diff] [blame] | 137 | keys_init(); |
| 138 | |
| 139 | if(target_volume_down()) |
| 140 | keys_post_event(KEY_VOLUMEDOWN, 1); |
| 141 | |
| 142 | if(target_volume_up()) |
| 143 | keys_post_event(KEY_VOLUMEUP, 1); |
Aparna Mallavarapu | fe1f3d1 | 2013-10-19 15:05:30 +0530 | [diff] [blame] | 144 | } |
| 145 | |
| 146 | void target_init(void) |
| 147 | { |
| 148 | uint32_t base_addr; |
| 149 | uint8_t slot; |
| 150 | |
| 151 | dprintf(INFO, "target_init()\n"); |
| 152 | |
| 153 | spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID); |
| 154 | |
| 155 | target_keystatus(); |
Aparna Mallavarapu | 7cc5a79 | 2014-02-27 21:49:59 -0800 | [diff] [blame] | 156 | set_sdc_power_ctrl(); |
Aparna Mallavarapu | fe1f3d1 | 2013-10-19 15:05:30 +0530 | [diff] [blame] | 157 | |
Aparna Mallavarapu | 7cc5a79 | 2014-02-27 21:49:59 -0800 | [diff] [blame] | 158 | target_sdc_init(); |
| 159 | if (partition_read_table()) |
Aparna Mallavarapu | fe1f3d1 | 2013-10-19 15:05:30 +0530 | [diff] [blame] | 160 | { |
Aparna Mallavarapu | 7cc5a79 | 2014-02-27 21:49:59 -0800 | [diff] [blame] | 161 | dprintf(CRITICAL, "Error reading the partition table info\n"); |
Aparna Mallavarapu | fe1f3d1 | 2013-10-19 15:05:30 +0530 | [diff] [blame] | 162 | ASSERT(0); |
| 163 | } |
Aparna Mallavarapu | fe1f3d1 | 2013-10-19 15:05:30 +0530 | [diff] [blame] | 164 | } |
| 165 | |
| 166 | void target_serialno(unsigned char *buf) |
| 167 | { |
| 168 | uint32_t serialno; |
| 169 | if (target_is_emmc_boot()) { |
| 170 | serialno = mmc_get_psn(); |
| 171 | snprintf((char *)buf, 13, "%x", serialno); |
| 172 | } |
| 173 | } |
| 174 | |
| 175 | unsigned board_machtype(void) |
| 176 | { |
Aparna Mallavarapu | 7cc5a79 | 2014-02-27 21:49:59 -0800 | [diff] [blame] | 177 | return LINUX_MACHTYPE_UNKNOWN; |
| 178 | } |
| 179 | |
| 180 | unsigned check_reboot_mode(void) |
| 181 | { |
| 182 | uint32_t restart_reason = 0; |
| 183 | |
| 184 | /* Read reboot reason and scrub it */ |
| 185 | restart_reason = readl(RESTART_REASON_ADDR); |
| 186 | writel(0x00, RESTART_REASON_ADDR); |
| 187 | |
| 188 | return restart_reason; |
| 189 | } |
| 190 | |
Aparna Mallavarapu | acb6ede | 2014-03-21 19:22:00 +0530 | [diff] [blame] | 191 | static int scm_dload_mode(int mode) |
| 192 | { |
| 193 | int ret = 0; |
| 194 | uint32_t dload_type; |
| 195 | |
| 196 | dprintf(SPEW, "DLOAD mode: %d\n", mode); |
| 197 | if (mode == NORMAL_DLOAD) |
| 198 | dload_type = SCM_DLOAD_MODE; |
| 199 | else if(mode == EMERGENCY_DLOAD) |
| 200 | dload_type = SCM_EDLOAD_MODE; |
| 201 | else |
| 202 | dload_type = 0; |
| 203 | |
| 204 | ret = scm_call_atomic2(SCM_SVC_BOOT, SCM_DLOAD_CMD, dload_type, 0); |
| 205 | if (ret) |
| 206 | dprintf(CRITICAL, "Failed to write to boot misc: %d\n", ret); |
| 207 | |
| 208 | ret = scm_call_atomic2(SCM_SVC_BOOT, WDOG_DEBUG_DISABLE, 1, 0); |
| 209 | if (ret) |
| 210 | dprintf(CRITICAL, "Failed to disable the wdog debug \n"); |
| 211 | |
| 212 | return ret; |
| 213 | } |
Aparna Mallavarapu | 7cc5a79 | 2014-02-27 21:49:59 -0800 | [diff] [blame] | 214 | void reboot_device(unsigned reboot_reason) |
| 215 | { |
Aparna Mallavarapu | acb6ede | 2014-03-21 19:22:00 +0530 | [diff] [blame] | 216 | uint8_t reset_type = 0; |
| 217 | uint32_t ret = 0; |
| 218 | |
| 219 | /* Need to clear the SW_RESET_ENTRY register and |
| 220 | * write to the BOOT_MISC_REG for known reset cases |
| 221 | */ |
| 222 | if(reboot_reason != DLOAD) |
| 223 | scm_dload_mode(NORMAL_MODE); |
| 224 | |
Aparna Mallavarapu | 7cc5a79 | 2014-02-27 21:49:59 -0800 | [diff] [blame] | 225 | writel(reboot_reason, RESTART_REASON_ADDR); |
| 226 | |
Aparna Mallavarapu | acb6ede | 2014-03-21 19:22:00 +0530 | [diff] [blame] | 227 | /* For Reboot-bootloader and Dload cases do a warm reset |
| 228 | * For Reboot cases do a hard reset |
| 229 | */ |
| 230 | if((reboot_reason == FASTBOOT_MODE) || (reboot_reason == DLOAD)) |
| 231 | reset_type = PON_PSHOLD_WARM_RESET; |
| 232 | else |
| 233 | reset_type = PON_PSHOLD_HARD_RESET; |
| 234 | |
| 235 | pm8x41_reset_configure(reset_type); |
| 236 | |
| 237 | ret = scm_halt_pmic_arbiter(); |
| 238 | if (ret) |
| 239 | dprintf(CRITICAL , "Failed to halt pmic arbiter: %d\n", ret); |
Aparna Mallavarapu | 7cc5a79 | 2014-02-27 21:49:59 -0800 | [diff] [blame] | 240 | |
| 241 | /* Drop PS_HOLD for MSM */ |
| 242 | writel(0x00, MPM2_MPM_PS_HOLD); |
| 243 | |
| 244 | mdelay(5000); |
| 245 | |
| 246 | dprintf(CRITICAL, "Rebooting failed\n"); |
| 247 | } |
| 248 | |
| 249 | /* Detect the target type */ |
| 250 | void target_detect(struct board_data *board) |
| 251 | { |
| 252 | /* |
| 253 | * already fill the board->target on board.c |
| 254 | */ |
| 255 | } |
| 256 | |
| 257 | void target_baseband_detect(struct board_data *board) |
| 258 | { |
| 259 | uint32_t platform; |
| 260 | |
| 261 | platform = board->platform; |
| 262 | switch(platform) |
| 263 | { |
| 264 | case MSM8916: |
| 265 | board->baseband = BASEBAND_MSM; |
| 266 | break; |
| 267 | default: |
| 268 | dprintf(CRITICAL, "Platform type: %u is not supported\n", platform); |
| 269 | ASSERT(0); |
| 270 | }; |
| 271 | } |
| 272 | |
| 273 | unsigned target_baseband() |
| 274 | { |
| 275 | return board_baseband(); |
| 276 | } |
| 277 | |
| 278 | int emmc_recovery_init(void) |
| 279 | { |
| 280 | return _emmc_recovery_init(); |
| 281 | } |
| 282 | |
| 283 | static void set_sdc_power_ctrl() |
| 284 | { |
| 285 | /* Drive strength configs for sdc pins */ |
| 286 | struct tlmm_cfgs sdc1_hdrv_cfg[] = |
| 287 | { |
| 288 | { SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK }, |
| 289 | { SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK }, |
| 290 | { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_6MA, TLMM_HDRV_MASK }, |
| 291 | }; |
| 292 | |
| 293 | /* Pull configs for sdc pins */ |
| 294 | struct tlmm_cfgs sdc1_pull_cfg[] = |
| 295 | { |
| 296 | { SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK }, |
| 297 | { SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK }, |
| 298 | { SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK }, |
| 299 | }; |
| 300 | |
| 301 | /* Set the drive strength & pull control values */ |
| 302 | tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg)); |
| 303 | tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg)); |
| 304 | } |
| 305 | |
| 306 | void target_usb_init(void) |
| 307 | { |
| 308 | uint32_t val; |
| 309 | |
| 310 | /* Select and enable external configuration with USB PHY */ |
| 311 | ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_SET); |
| 312 | |
| 313 | /* Enable sess_vld */ |
| 314 | val = readl(USB_GENCONFIG_2) | GEN2_SESS_VLD_CTRL_EN; |
| 315 | writel(val, USB_GENCONFIG_2); |
| 316 | |
| 317 | /* Enable external vbus configuration in the LINK */ |
| 318 | val = readl(USB_USBCMD); |
| 319 | val |= SESS_VLD_CTRL; |
| 320 | writel(val, USB_USBCMD); |
| 321 | } |
| 322 | |
Padmanabhan Komanduru | 1869a76 | 2014-04-01 20:12:05 +0530 | [diff] [blame] | 323 | uint8_t target_panel_auto_detect_enabled() |
| 324 | { |
| 325 | uint8_t ret = 0; |
| 326 | uint32_t hw_subtype = board_hardware_subtype(); |
| 327 | |
| 328 | switch(board_hardware_id()) { |
| 329 | case HW_PLATFORM_SURF: |
| 330 | ret = 1; |
| 331 | break; |
| 332 | default: |
| 333 | ret = 0; |
| 334 | break; |
| 335 | } |
| 336 | return ret; |
| 337 | } |
| 338 | |
| 339 | static uint8_t splash_override; |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 340 | /* Returns 1 if target supports continuous splash screen. */ |
| 341 | int target_cont_splash_screen() |
| 342 | { |
| 343 | uint8_t splash_screen = 0; |
Padmanabhan Komanduru | 1869a76 | 2014-04-01 20:12:05 +0530 | [diff] [blame] | 344 | if (!splash_override) { |
| 345 | switch (board_hardware_id()) { |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 346 | case HW_PLATFORM_MTP: |
| 347 | case HW_PLATFORM_SURF: |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 348 | splash_screen = 1; |
| 349 | break; |
| 350 | default: |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 351 | splash_screen = 0; |
| 352 | break; |
Padmanabhan Komanduru | 1869a76 | 2014-04-01 20:12:05 +0530 | [diff] [blame] | 353 | } |
| 354 | dprintf(SPEW, "Target_cont_splash=%d\n", splash_screen); |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 355 | } |
Padmanabhan Komanduru | 1869a76 | 2014-04-01 20:12:05 +0530 | [diff] [blame] | 356 | return splash_screen; |
| 357 | } |
| 358 | |
| 359 | void target_force_cont_splash_disable(uint8_t override) |
| 360 | { |
| 361 | splash_override = override; |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 362 | } |
| 363 | |
Zhenhua Huang | 9b8cb1c | 2014-04-11 15:23:05 +0800 | [diff] [blame^] | 364 | unsigned target_pause_for_battery_charge(void) |
| 365 | { |
| 366 | uint8_t pon_reason = pm8x41_get_pon_reason(); |
| 367 | uint8_t is_cold_boot = pm8x41_get_is_cold_boot(); |
| 368 | dprintf(INFO, "%s : pon_reason is %d cold_boot:%d\n", __func__, |
| 369 | pon_reason, is_cold_boot); |
| 370 | /* In case of fastboot reboot,adb reboot or if we see the power key |
| 371 | * pressed we do not want go into charger mode. |
| 372 | * fastboot reboot is warm boot with PON hard reset bit not set |
| 373 | * adb reboot is a cold boot with PON hard reset bit set |
| 374 | */ |
| 375 | if (is_cold_boot && |
| 376 | (!(pon_reason & HARD_RST)) && |
| 377 | (!(pon_reason & KPDPWR_N)) && |
| 378 | ((pon_reason & USB_CHG) || (pon_reason & DC_CHG))) |
| 379 | return 1; |
| 380 | else |
| 381 | return 0; |
| 382 | } |
| 383 | |
Aparna Mallavarapu | 7cc5a79 | 2014-02-27 21:49:59 -0800 | [diff] [blame] | 384 | void target_usb_stop(void) |
| 385 | { |
| 386 | /* Disable VBUS mimicing in the controller. */ |
| 387 | ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_CLEAR); |
| 388 | } |
| 389 | |
| 390 | |
| 391 | void target_uninit(void) |
| 392 | { |
| 393 | mmc_put_card_to_sleep(dev); |
| 394 | sdhci_mode_disable(&dev->host); |
| 395 | } |
| 396 | |
| 397 | /* Do any target specific intialization needed before entering fastboot mode */ |
| 398 | void target_fastboot_init(void) |
| 399 | { |
| 400 | /* Set the BOOT_DONE flag in PM8916 */ |
| 401 | pm8x41_set_boot_done(); |
Aparna Mallavarapu | fe1f3d1 | 2013-10-19 15:05:30 +0530 | [diff] [blame] | 402 | } |
Aparna Mallavarapu | acb6ede | 2014-03-21 19:22:00 +0530 | [diff] [blame] | 403 | |
| 404 | int set_download_mode(enum dload_mode mode) |
| 405 | { |
| 406 | int ret = 0; |
| 407 | ret = scm_dload_mode(mode); |
| 408 | |
| 409 | pm8x41_clear_pmic_watchdog(); |
| 410 | |
| 411 | return ret; |
| 412 | } |