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gerrit-public.fairphone.software / kernel / lk / a0a74726423f35c1e9f64bad5ce010e858479870 / . / platform / msm8952 / include / platform / iomap.h
blob: 2bf5d7e86d93c9ce4f11af4ac092c3b84c4fc5a8 [file] [log] [blame]
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]1/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef _PLATFORM_MSM8952_IOMAP_H_
30#define _PLATFORM_MSM8952_IOMAP_H_
31
32#define MSM_IOMAP_BASE 0x00000000
33#define MSM_IOMAP_END 0x08000000
34
35#define SDRAM_START_ADDR 0x80000000
36
Aparna Mallavarapue9bdacd2015-03-15 14:24:21 +0530[diff] [blame]37#define DDR_START get_ddr_start()
38#define ABOOT_FORCE_KERNEL_ADDR DDR_START + 0x8000
39#define ABOOT_FORCE_KERNEL64_ADDR DDR_START + 0x80000
40#define ABOOT_FORCE_RAMDISK_ADDR DDR_START + 0x2000000
41#define ABOOT_FORCE_TAGS_ADDR DDR_START + 0x1E00000
42
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]43#define MSM_SHARED_BASE 0x86300000
44#define MSM_SHARED_IMEM_BASE 0x08600000
45
46#define BS_INFO_OFFSET (0x6B0)
47#define BS_INFO_ADDR (MSM_SHARED_IMEM_BASE + BS_INFO_OFFSET)
48
49#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
50
51#define APPS_SS_BASE 0x0B000000
Aparna Mallavarapue9bdacd2015-03-15 14:24:21 +0530[diff] [blame]52#define APPS_SS_END 0x0B200000
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]53
54#define MSM_GIC_DIST_BASE APPS_SS_BASE
55#define MSM_GIC_CPU_BASE (APPS_SS_BASE + 0x2000)
56#define APPS_APCS_QTMR_AC_BASE (APPS_SS_BASE + 0x00020000)
57#define APPS_APCS_F0_QTMR_V1_BASE (APPS_SS_BASE + 0x00021000)
58#define QTMR_BASE APPS_APCS_F0_QTMR_V1_BASE
Aparna Mallavarapufa5f8a72015-03-31 06:21:36 +0530[diff] [blame]59#define APCS_ALIAS0_IPC_INTERRUPT (APPS_SS_BASE + 0x00111008)
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]60
61#define PERIPH_SS_BASE 0x07800000
62
63#define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00024000)
64#define MSM_SDC2_BASE (PERIPH_SS_BASE + 0x00064000)
65
Aparna Mallavarapu7b638e62015-03-26 05:51:57 +0530[diff] [blame]66/* UART */
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]67#define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x000AF000)
68#define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x000B0000)
69#define MSM_USB_BASE (PERIPH_SS_BASE + 0x000DB000)
70
71#define CLK_CTL_BASE 0x1800000
72
Matthew Qin7afa8492015-06-26 17:05:18 +0800[diff] [blame]73#define PMI_SLAVE_ID 3
74#define PMI_ADDR_BASE (PMI_SLAVE_ID << 16)
75
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]76#define SPMI_BASE 0x02000000
77#define SPMI_GENI_BASE (SPMI_BASE + 0xA000)
78#define SPMI_PIC_BASE (SPMI_BASE + 0x01800000)
79#define PMIC_ARB_CORE 0x200F000
80
81#define TLMM_BASE_ADDR 0x1000000
82#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + (x)*0x1000)
83#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x00000004 + (x)*0x1000)
84
85#define MPM2_MPM_CTRL_BASE 0x004A0000
86#define MPM2_MPM_PS_HOLD 0x004AB000
87#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0x004A3000
88
89/* CRYPTO ENGINE */
90#define MSM_CE1_BASE 0x073A000
91#define MSM_CE1_BAM_BASE 0x0704000
Aparna Mallavarapu7b638e62015-03-26 05:51:57 +0530[diff] [blame]92#define GCC_CRYPTO_BCR (CLK_CTL_BASE + 0x16000)
93#define GCC_CRYPTO_CMD_RCGR (CLK_CTL_BASE + 0x16004)
94#define GCC_CRYPTO_CFG_RCGR (CLK_CTL_BASE + 0x16008)
95#define GCC_CRYPTO_CBCR (CLK_CTL_BASE + 0x1601C)
96#define GCC_CRYPTO_AXI_CBCR (CLK_CTL_BASE + 0x16020)
97#define GCC_CRYPTO_AHB_CBCR (CLK_CTL_BASE + 0x16024)
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]98
99/* GPLL */
100#define GPLL0_STATUS (CLK_CTL_BASE + 0x2101C)
vijay kumara0a74722015-09-04 15:45:49 +0530[diff] [blame^]101#define GPLL2_STATUS (CLK_CTL_BASE + 0x4A01C)
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]102#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x45000)
103#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x45004)
Aparna Mallavarapu7b638e62015-03-26 05:51:57 +0530[diff] [blame]104#define GPLL4_MODE (CLK_CTL_BASE + 0x24000)
Unnati Gandhi81b77062015-05-28 14:23:39 +0530[diff] [blame]105#define GPLL4_STATUS (CLK_CTL_BASE + 0x24024)
Padmanabhan Komanduru2655ea62015-06-08 12:23:32 +0530[diff] [blame]106#define GPLL6_STATUS (CLK_CTL_BASE + 0x3701C)
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]107
108/* SDCC */
109#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x10A000)
110#define SDCC1_BCR (CLK_CTL_BASE + 0x42000) /* block reset*/
111#define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x42018) /* branch ontrol */
112#define SDCC1_AHB_CBCR (CLK_CTL_BASE + 0x4201C)
113#define SDCC1_CMD_RCGR (CLK_CTL_BASE + 0x42004) /* cmd */
114#define SDCC1_CFG_RCGR (CLK_CTL_BASE + 0x42008) /* cfg */
115#define SDCC1_M (CLK_CTL_BASE + 0x4200C) /* m */
116#define SDCC1_N (CLK_CTL_BASE + 0x42010) /* n */
117#define SDCC1_D (CLK_CTL_BASE + 0x42014) /* d */
118
Aparna Mallavarapu7b638e62015-03-26 05:51:57 +0530[diff] [blame]119/* SDHCI */
120#define MSM_SDC1_SDHCI_BASE (PERIPH_SS_BASE + 0x00024900)
121#define MSM_SDC2_SDHCI_BASE (PERIPH_SS_BASE + 0x00064900)
122
123#define SDCC_MCI_HC_MODE (0x00000078)
124#define SDCC_HC_PWRCTL_STATUS_REG (0x000000DC)
125#define SDCC_HC_PWRCTL_MASK_REG (0x000000E0)
126#define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4)
127#define SDCC_HC_PWRCTL_CTL_REG (0x000000E8)
128
129#define SDCC2_BCR (CLK_CTL_BASE + 0x43000) /* block reset */
130#define SDCC2_APPS_CBCR (CLK_CTL_BASE + 0x43018) /* branch control */
131#define SDCC2_AHB_CBCR (CLK_CTL_BASE + 0x4301C)
132#define SDCC2_CMD_RCGR (CLK_CTL_BASE + 0x43004) /* cmd */
133#define SDCC2_CFG_RCGR (CLK_CTL_BASE + 0x43008) /* cfg */
134#define SDCC2_M (CLK_CTL_BASE + 0x4300C) /* m */
135#define SDCC2_N (CLK_CTL_BASE + 0x43010) /* n */
136#define SDCC2_D (CLK_CTL_BASE + 0x43014) /* d */
137
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]138/* UART */
139#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x1008)
140#define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x302C)
141#define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x3034)
142#define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x3038)
143#define BLSP1_UART2_APPS_M (CLK_CTL_BASE + 0x303C)
144#define BLSP1_UART2_APPS_N (CLK_CTL_BASE + 0x3040)
145#define BLSP1_UART2_APPS_D (CLK_CTL_BASE + 0x3044)
146
147/* USB */
148#define USB_HS_BCR (CLK_CTL_BASE + 0x41000)
149#define USB_HS_SYSTEM_CBCR (CLK_CTL_BASE + 0x41004)
150#define USB_HS_AHB_CBCR (CLK_CTL_BASE + 0x41008)
151#define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x41010)
152#define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x41014)
153
Padmanabhan Komanduru80389722015-04-09 20:49:42 -0700[diff] [blame]154/* MDSS */
155#define MIPI_DSI_BASE (0x1A98000)
156#define MIPI_DSI0_BASE MIPI_DSI_BASE
Padmanabhan Komanduru6cabd5a2015-06-08 14:13:04 +0530[diff] [blame]157#define MIPI_DSI1_BASE (0x1A96000)
Padmanabhan Komanduru80389722015-04-09 20:49:42 -0700[diff] [blame]158#define DSI0_PHY_BASE (0x1A98500)
Padmanabhan Komanduru6cabd5a2015-06-08 14:13:04 +0530[diff] [blame]159#define DSI1_PHY_BASE (0x1A96400)
Padmanabhan Komanduru80389722015-04-09 20:49:42 -0700[diff] [blame]160#define DSI0_PLL_BASE (0x1A98300)
Padmanabhan Komanduru6cabd5a2015-06-08 14:13:04 +0530[diff] [blame]161#define DSI1_PLL_BASE (0x1A96A00)
Padmanabhan Komanduru80389722015-04-09 20:49:42 -0700[diff] [blame]162#define DSI0_REGULATOR_BASE (0x1A98780)
163#define DSI1_REGULATOR_BASE DSI0_REGULATOR_BASE
164#define MDP_BASE (0x1A00000)
165#define REG_MDP(off) (MDP_BASE + (off))
166
167#ifdef MDP_HW_REV
168#undef MDP_HW_REV
169#endif
170#define MDP_HW_REV REG_MDP(0x1000)
171
172#ifdef MDP_INTR_EN
173#undef MDP_INTR_EN
174#endif
175#define MDP_INTR_EN REG_MDP(0x1010)
176
177#ifdef MDP_INTR_CLEAR
178#undef MDP_INTR_CLEAR
179#endif
180#define MDP_INTR_CLEAR REG_MDP(0x1018)
181
182#ifdef MDP_HIST_INTR_EN
183#undef MDP_HIST_INTR_EN
184#endif
185#define MDP_HIST_INTR_EN REG_MDP(0x101C)
186
187#ifdef MDP_VP_0_VIG_0_BASE
188#undef MDP_VP_0_VIG_0_BASE
189#endif
190#define MDP_VP_0_VIG_0_BASE REG_MDP(0x5000)
191
192#ifdef MDP_VP_0_VIG_1_BASE
193#undef MDP_VP_0_VIG_1_BASE
194#endif
195#define MDP_VP_0_VIG_1_BASE REG_MDP(0x7000)
196
197#ifdef MDP_VP_0_RGB_0_BASE
198#undef MDP_VP_0_RGB_0_BASE
199#endif
200#define MDP_VP_0_RGB_0_BASE REG_MDP(0x15000)
201
202#ifdef MDP_VP_0_RGB_1_BASE
203#undef MDP_VP_0_RGB_1_BASE
204#endif
205#define MDP_VP_0_RGB_1_BASE REG_MDP(0x17000)
206
207#ifdef MDP_VP_0_DMA_0_BASE
208#undef MDP_VP_0_DMA_0_BASE
209#endif
210#define MDP_VP_0_DMA_0_BASE REG_MDP(0x25000)
211
212#ifdef MDP_VP_0_DMA_1_BASE
213#undef MDP_VP_0_DMA_1_BASE
214#endif
215#define MDP_VP_0_DMA_1_BASE REG_MDP(0x27000)
216
217#ifdef MDP_VP_0_MIXER_0_BASE
218#undef MDP_VP_0_MIXER_0_BASE
219#endif
220#define MDP_VP_0_MIXER_0_BASE REG_MDP(0x45000)
221
222#ifdef MDP_VP_0_MIXER_1_BASE
223#undef MDP_VP_0_MIXER_1_BASE
224#endif
225#define MDP_VP_0_MIXER_1_BASE REG_MDP(0x46000)
226
227#ifdef MDP_DISP_INTF_SEL
228#undef MDP_DISP_INTF_SEL
229#endif
230#define MDP_DISP_INTF_SEL REG_MDP(0x1004)
231
232#ifdef MDP_VIDEO_INTF_UNDERFLOW_CTL
233#undef MDP_VIDEO_INTF_UNDERFLOW_CTL
234#endif
235#define MDP_VIDEO_INTF_UNDERFLOW_CTL REG_MDP(0x12E0)
236
237#ifdef MDP_UPPER_NEW_ROI_PRIOR_RO_START
238#undef MDP_UPPER_NEW_ROI_PRIOR_RO_START
239#endif
240#define MDP_UPPER_NEW_ROI_PRIOR_RO_START REG_MDP(0x11EC)
241
242#ifdef MDP_LOWER_NEW_ROI_PRIOR_TO_START
243#undef MDP_LOWER_NEW_ROI_PRIOR_TO_START
244#endif
245#define MDP_LOWER_NEW_ROI_PRIOR_TO_START REG_MDP(0x13F8)
246
247#ifdef MDP_CTL_0_BASE
248#undef MDP_CTL_0_BASE
249#endif
250#define MDP_CTL_0_BASE REG_MDP(0x2000)
251
252#ifdef MDP_CTL_1_BASE
253#undef MDP_CTL_1_BASE
254#endif
255#define MDP_CTL_1_BASE REG_MDP(0x2200)
256
257#ifdef MDP_CLK_CTRL0
258#undef MDP_CLK_CTRL0
259#endif
260#define MDP_CLK_CTRL0 REG_MDP(0x012AC)
261
262#ifdef MDP_CLK_CTRL1
263#undef MDP_CLK_CTRL1
264#endif
265#define MDP_CLK_CTRL1 REG_MDP(0x012B4)
266
267#ifdef MDP_CLK_CTRL2
268#undef MDP_CLK_CTRL2
269#endif
270#define MDP_CLK_CTRL2 REG_MDP(0x012BC)
271
272#ifdef MDP_CLK_CTRL3
273#undef MDP_CLK_CTRL3
274#endif
275#define MDP_CLK_CTRL3 REG_MDP(0x013A8)
276
277#ifdef MDP_CLK_CTRL4
278#undef MDP_CLK_CTRL4
279#endif
280#define MDP_CLK_CTRL4 REG_MDP(0x013B0)
281
282#ifdef MDP_CLK_CTRL5
283#undef MDP_CLK_CTRL5
284#endif
285#define MDP_CLK_CTRL5 REG_MDP(0x013B8)
286
287#ifdef MDP_INTF_1_BASE
288#undef MDP_INTF_1_BASE
289#endif
290#define MDP_INTF_1_BASE REG_MDP(0x12700)
291
Padmanabhan Komanduruf912cfb2015-06-08 16:36:58 +0530[diff] [blame]292#ifdef MDP_INTF_2_BASE
293#undef MDP_INTF_2_BASE
294#endif
295#define MDP_INTF_2_BASE REG_MDP(0x12F00)
296
297#ifdef MDP_REG_SPLIT_DISPLAY_EN
298#undef MDP_REG_SPLIT_DISPLAY_EN
299#endif
300#define MDP_REG_SPLIT_DISPLAY_EN REG_MDP(0x12F4)
301
302#ifdef MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL
303#undef MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL
304#endif
305#define MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL REG_MDP(0x12F8)
306
307#ifdef MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL
308#undef MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL
309#endif
310#define MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL REG_MDP(0x13F0)
311
Padmanabhan Komanduru80389722015-04-09 20:49:42 -0700[diff] [blame]312#ifdef MMSS_MDP_SMP_ALLOC_W_BASE
313#undef MMSS_MDP_SMP_ALLOC_W_BASE
314#endif
315#define MMSS_MDP_SMP_ALLOC_W_BASE REG_MDP(0x1080)
316
317#ifdef MMSS_MDP_SMP_ALLOC_R_BASE
318#undef MMSS_MDP_SMP_ALLOC_R_BASE
319#endif
320#define MMSS_MDP_SMP_ALLOC_R_BASE REG_MDP(0x1130)
321
322#ifdef MDP_QOS_REMAPPER_CLASS_0
323#undef MDP_QOS_REMAPPER_CLASS_0
324#endif
325#define MDP_QOS_REMAPPER_CLASS_0 REG_MDP(0x11E0)
326
327#ifdef VBIF_VBIF_DDR_FORCE_CLK_ON
328#undef VBIF_VBIF_DDR_FORCE_CLK_ON
329#endif
330#define VBIF_VBIF_DDR_FORCE_CLK_ON REG_MDP(0xc8004)
331
332#ifdef VBIF_VBIF_DDR_OUT_MAX_BURST
333#undef VBIF_VBIF_DDR_OUT_MAX_BURST
334#endif
335#define VBIF_VBIF_DDR_OUT_MAX_BURST REG_MDP(0xc80D8)
336
337#ifdef VBIF_VBIF_DDR_ARB_CTRL
338#undef VBIF_VBIF_DDR_ARB_CTRL
339#endif
340#define VBIF_VBIF_DDR_ARB_CTRL REG_MDP(0xc80F0)
341
342#ifdef VBIF_VBIF_DDR_RND_RBN_QOS_ARB
343#undef VBIF_VBIF_DDR_RND_RBN_QOS_ARB
344#endif
345#define VBIF_VBIF_DDR_RND_RBN_QOS_ARB REG_MDP(0xc8124)
346
347#ifdef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0
348#undef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0
349#endif
350#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0 REG_MDP(0xc8160)
351
352#ifdef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1
353#undef VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1
354#endif
355#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1 REG_MDP(0xc8164)
356
357#ifdef VBIF_VBIF_DDR_OUT_AOOO_AXI_EN
358#undef VBIF_VBIF_DDR_OUT_AOOO_AXI_EN
359#endif
360#define VBIF_VBIF_DDR_OUT_AOOO_AXI_EN REG_MDP(0xc8178)
361
362#ifdef VBIF_VBIF_DDR_OUT_AX_AOOO
363#undef VBIF_VBIF_DDR_OUT_AX_AOOO
364#endif
365#define VBIF_VBIF_DDR_OUT_AX_AOOO REG_MDP(0xc817C)
366
367#ifdef VBIF_VBIF_IN_RD_LIM_CONF0
368#undef VBIF_VBIF_IN_RD_LIM_CONF0
369#endif
370#define VBIF_VBIF_IN_RD_LIM_CONF0 REG_MDP(0xc80B0)
371
372#ifdef VBIF_VBIF_IN_RD_LIM_CONF1
373#undef VBIF_VBIF_IN_RD_LIM_CONF1
374#endif
375#define VBIF_VBIF_IN_RD_LIM_CONF1 REG_MDP(0xc80B4)
376
377#ifdef VBIF_VBIF_IN_WR_LIM_CONF0
378#undef VBIF_VBIF_IN_WR_LIM_CONF0
379#endif
380#define VBIF_VBIF_IN_WR_LIM_CONF0 REG_MDP(0xc80C0)
381
382#ifdef VBIF_VBIF_IN_WR_LIM_CONF1
383#undef VBIF_VBIF_IN_WR_LIM_CONF1
384#endif
385#define VBIF_VBIF_IN_WR_LIM_CONF1 REG_MDP(0xc80C4)
386
Sandeep Pandae0b27712015-07-31 16:41:13 +0530[diff] [blame]387#ifdef MDP_INTF_2_TIMING_ENGINE_EN
388#undef MDP_INTF_2_TIMING_ENGINE_EN
389#endif
390#define MDP_INTF_2_TIMING_ENGINE_EN REG_MDP(0x12F00)
391
392#ifdef MDP_PP_0_BASE
393#undef MDP_PP_0_BASE
394#endif
395#define MDP_PP_0_BASE REG_MDP(0x71000)
396
397#ifdef MDP_PP_1_BASE
398#undef MDP_PP_1_BASE
399#endif
400#define MDP_PP_1_BASE REG_MDP(0x71800)
401
402#ifdef MDSS_MDP_REG_DCE_SEL
403#undef MDSS_MDP_REG_DCE_SEL
404#endif
405#define MDSS_MDP_REG_DCE_SEL REG_MDP(0x1428)
406
407#ifdef MDSS_MDP_PP_DCE_DATA_OUT_SWAP
408#undef MDSS_MDP_PP_DCE_DATA_OUT_SWAP
409#endif
410#define MDSS_MDP_PP_DCE_DATA_OUT_SWAP 0x0CC
411
412#define MDP_DSC_0_BASE REG_MDP(0x81000)
413#define MDP_DSC_1_BASE REG_MDP(0x81400)
414
415
Padmanabhan Komanduru80389722015-04-09 20:49:42 -0700[diff] [blame]416#define SOFT_RESET 0x118
417#define CLK_CTRL 0x11C
418#define TRIG_CTRL 0x084
419#define CTRL 0x004
420#define COMMAND_MODE_DMA_CTRL 0x03C
421#define COMMAND_MODE_MDP_CTRL 0x040
422#define COMMAND_MODE_MDP_DCS_CMD_CTRL 0x044
423#define COMMAND_MODE_MDP_STREAM0_CTRL 0x058
424#define COMMAND_MODE_MDP_STREAM0_TOTAL 0x05C
425#define COMMAND_MODE_MDP_STREAM1_CTRL 0x060
426#define COMMAND_MODE_MDP_STREAM1_TOTAL 0x064
427#define ERR_INT_MASK0 0x10C
428
429#define LANE_CTL 0x0AC
430#define LANE_SWAP_CTL 0x0B0
431#define TIMING_CTL 0x0C4
432
433#define VIDEO_MODE_ACTIVE_H 0x024
434#define VIDEO_MODE_ACTIVE_V 0x028
435#define VIDEO_MODE_TOTAL 0x02C
436#define VIDEO_MODE_HSYNC 0x030
437#define VIDEO_MODE_VSYNC 0x034
438#define VIDEO_MODE_VSYNC_VPOS 0x038
439
440#define DMA_CMD_OFFSET 0x048
441#define DMA_CMD_LENGTH 0x04C
442
443#define INT_CTRL 0x110
444#define CMD_MODE_DMA_SW_TRIGGER 0x090
445
446#define EOT_PACKET_CTRL 0x0CC
447#define MISR_CMD_CTRL 0x0A0
448#define MISR_VIDEO_CTRL 0x0A4
449#define VIDEO_MODE_CTRL 0x010
450#define HS_TIMER_CTRL 0x0BC
451
Sandeep Pandae0b27712015-07-31 16:41:13 +0530[diff] [blame]452#define VIDEO_COMPRESSION_MODE_CTRL 0x2A0
453#define VIDEO_COMPRESSION_MODE_CTRL_2 0x2A4
454#define CMD_COMPRESSION_MODE_CTRL 0x2A8
455#define CMD_COMPRESSION_MODE_CTRL_2 0x2AC
456#define CMD_COMPRESSION_MODE_CTRL_3 0x2B0
457
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]458#define TCSR_TZ_WONCE 0x193D000
459#define TCSR_BOOT_MISC_DETECT 0x193D100
Aparna Mallavarapu59914502015-06-01 15:31:28 +0530[diff] [blame]460
461#define APPS_WDOG_BARK_VAL_REG 0x0B017010
462#define APPS_WDOG_BITE_VAL_REG 0x0B017014
463#define APPS_WDOG_RESET_REG 0x0B017008
464#define APPS_WDOG_CTL_REG 0x0B017004
Aparna Mallavarapuca676882015-01-19 20:39:06 +0530[diff] [blame]465#endif