Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <assert.h> |
| 30 | #include <reg.h> |
| 31 | #include <err.h> |
| 32 | #include <clock.h> |
| 33 | #include <clock_pll.h> |
| 34 | #include <clock_lib2.h> |
| 35 | #include <platform/clock.h> |
| 36 | #include <platform/iomap.h> |
| 37 | |
| 38 | |
| 39 | /* Mux source select values */ |
| 40 | #define cxo_source_val 0 |
| 41 | #define gpll0_source_val 1 |
| 42 | #define gpll4_source_val 5 |
| 43 | #define cxo_mm_source_val 0 |
| 44 | #define mmpll0_mm_source_val 1 |
| 45 | #define mmpll1_mm_source_val 2 |
| 46 | #define mmpll3_mm_source_val 3 |
| 47 | #define gpll0_mm_source_val 5 |
| 48 | |
| 49 | struct clk_freq_tbl rcg_dummy_freq = F_END; |
| 50 | |
| 51 | |
| 52 | /* Clock Operations */ |
Channagoud Kadabi | 3dcc4ed | 2014-04-10 14:59:41 -0700 | [diff] [blame] | 53 | static struct clk_ops clk_ops_rst = |
| 54 | { |
| 55 | .reset = clock_lib2_reset_clk_reset, |
| 56 | }; |
| 57 | |
Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 58 | static struct clk_ops clk_ops_branch = |
| 59 | { |
| 60 | .enable = clock_lib2_branch_clk_enable, |
| 61 | .disable = clock_lib2_branch_clk_disable, |
| 62 | .set_rate = clock_lib2_branch_set_rate, |
Channagoud Kadabi | 3dcc4ed | 2014-04-10 14:59:41 -0700 | [diff] [blame] | 63 | .reset = clock_lib2_branch_clk_reset, |
Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 64 | }; |
| 65 | |
| 66 | static struct clk_ops clk_ops_rcg_mnd = |
| 67 | { |
| 68 | .enable = clock_lib2_rcg_enable, |
| 69 | .set_rate = clock_lib2_rcg_set_rate, |
| 70 | }; |
| 71 | |
| 72 | static struct clk_ops clk_ops_rcg = |
| 73 | { |
| 74 | .enable = clock_lib2_rcg_enable, |
| 75 | .set_rate = clock_lib2_rcg_set_rate, |
| 76 | }; |
| 77 | |
| 78 | static struct clk_ops clk_ops_cxo = |
| 79 | { |
| 80 | .enable = cxo_clk_enable, |
| 81 | .disable = cxo_clk_disable, |
| 82 | }; |
| 83 | |
| 84 | static struct clk_ops clk_ops_pll_vote = |
| 85 | { |
| 86 | .enable = pll_vote_clk_enable, |
| 87 | .disable = pll_vote_clk_disable, |
| 88 | .auto_off = pll_vote_clk_disable, |
| 89 | .is_enabled = pll_vote_clk_is_enabled, |
| 90 | }; |
| 91 | |
| 92 | static struct clk_ops clk_ops_vote = |
| 93 | { |
| 94 | .enable = clock_lib2_vote_clk_enable, |
| 95 | .disable = clock_lib2_vote_clk_disable, |
| 96 | }; |
| 97 | |
| 98 | /* Clock Sources */ |
| 99 | static struct fixed_clk cxo_clk_src = |
| 100 | { |
| 101 | .c = { |
| 102 | .rate = 19200000, |
| 103 | .dbg_name = "cxo_clk_src", |
| 104 | .ops = &clk_ops_cxo, |
| 105 | }, |
| 106 | }; |
| 107 | |
| 108 | static struct pll_vote_clk gpll0_clk_src = |
| 109 | { |
| 110 | .en_reg = (void *) APCS_GPLL_ENA_VOTE, |
| 111 | .en_mask = BIT(0), |
| 112 | .status_reg = (void *) GPLL0_MODE, |
| 113 | .status_mask = BIT(30), |
| 114 | .parent = &cxo_clk_src.c, |
| 115 | |
| 116 | .c = { |
| 117 | .rate = 600000000, |
| 118 | .dbg_name = "gpll0_clk_src", |
| 119 | .ops = &clk_ops_pll_vote, |
| 120 | }, |
| 121 | }; |
| 122 | |
| 123 | static struct pll_vote_clk gpll4_clk_src = |
| 124 | { |
| 125 | .en_reg = (void *) APCS_GPLL_ENA_VOTE, |
| 126 | .en_mask = BIT(4), |
| 127 | .status_reg = (void *) GPLL4_MODE, |
| 128 | .status_mask = BIT(30), |
| 129 | .parent = &cxo_clk_src.c, |
| 130 | |
| 131 | .c = { |
| 132 | .rate = 1600000000, |
| 133 | .dbg_name = "gpll4_clk_src", |
| 134 | .ops = &clk_ops_pll_vote, |
| 135 | }, |
| 136 | }; |
| 137 | |
| 138 | /* UART Clocks */ |
| 139 | static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = |
| 140 | { |
| 141 | F( 3686400, gpll0, 1, 96, 15625), |
| 142 | F( 7372800, gpll0, 1, 192, 15625), |
| 143 | F(14745600, gpll0, 1, 384, 15625), |
| 144 | F(16000000, gpll0, 5, 2, 15), |
| 145 | F(19200000, cxo, 1, 0, 0), |
| 146 | F(24000000, gpll0, 5, 1, 5), |
| 147 | F(32000000, gpll0, 1, 4, 75), |
| 148 | F(40000000, gpll0, 15, 0, 0), |
| 149 | F(46400000, gpll0, 1, 29, 375), |
| 150 | F(48000000, gpll0, 12.5, 0, 0), |
| 151 | F(51200000, gpll0, 1, 32, 375), |
| 152 | F(56000000, gpll0, 1, 7, 75), |
| 153 | F(58982400, gpll0, 1, 1536, 15625), |
| 154 | F(60000000, gpll0, 10, 0, 0), |
Channagoud Kadabi | a66a6f2 | 2014-05-28 17:19:44 -0700 | [diff] [blame^] | 155 | F(63160000, gpll0, 9.5, 0, 0), |
Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 156 | F_END |
| 157 | }; |
| 158 | |
| 159 | static struct rcg_clk blsp2_uart2_apps_clk_src = |
| 160 | { |
| 161 | .cmd_reg = (uint32_t *) BLSP2_UART2_APPS_CMD_RCGR, |
| 162 | .cfg_reg = (uint32_t *) BLSP2_UART2_APPS_CFG_RCGR, |
| 163 | .m_reg = (uint32_t *) BLSP2_UART2_APPS_M, |
| 164 | .n_reg = (uint32_t *) BLSP2_UART2_APPS_N, |
| 165 | .d_reg = (uint32_t *) BLSP2_UART2_APPS_D, |
| 166 | |
| 167 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 168 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
| 169 | .current_freq = &rcg_dummy_freq, |
| 170 | |
| 171 | .c = { |
| 172 | .dbg_name = "blsp1_uart2_apps_clk", |
| 173 | .ops = &clk_ops_rcg_mnd, |
| 174 | }, |
| 175 | }; |
| 176 | |
| 177 | static struct rcg_clk blsp1_uart2_apps_clk_src = |
| 178 | { |
| 179 | .cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR, |
| 180 | .cfg_reg = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR, |
| 181 | .m_reg = (uint32_t *) BLSP1_UART2_APPS_M, |
| 182 | .n_reg = (uint32_t *) BLSP1_UART2_APPS_N, |
| 183 | .d_reg = (uint32_t *) BLSP1_UART2_APPS_D, |
| 184 | |
| 185 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 186 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
| 187 | .current_freq = &rcg_dummy_freq, |
| 188 | |
| 189 | .c = { |
| 190 | .dbg_name = "blsp1_uart2_apps_clk", |
| 191 | .ops = &clk_ops_rcg_mnd, |
| 192 | }, |
| 193 | }; |
| 194 | |
| 195 | static struct branch_clk gcc_blsp2_uart2_apps_clk = |
| 196 | { |
| 197 | .cbcr_reg = (uint32_t *) BLSP2_UART2_APPS_CBCR, |
| 198 | .parent = &blsp2_uart2_apps_clk_src.c, |
| 199 | |
| 200 | .c = { |
| 201 | .dbg_name = "gcc_blsp2_uart2_apps_clk", |
| 202 | .ops = &clk_ops_branch, |
| 203 | }, |
| 204 | }; |
| 205 | |
| 206 | static struct branch_clk gcc_blsp1_uart2_apps_clk = |
| 207 | { |
| 208 | .cbcr_reg = (uint32_t *) BLSP1_UART2_APPS_CBCR, |
| 209 | .parent = &blsp1_uart2_apps_clk_src.c, |
| 210 | |
| 211 | .c = { |
| 212 | .dbg_name = "gcc_blsp1_uart2_apps_clk", |
| 213 | .ops = &clk_ops_branch, |
| 214 | }, |
| 215 | }; |
| 216 | |
| 217 | static struct vote_clk gcc_blsp1_ahb_clk = { |
| 218 | .cbcr_reg = (uint32_t *) BLSP1_AHB_CBCR, |
| 219 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 220 | .en_mask = BIT(17), |
| 221 | |
| 222 | .c = { |
| 223 | .dbg_name = "gcc_blsp1_ahb_clk", |
| 224 | .ops = &clk_ops_vote, |
| 225 | }, |
| 226 | }; |
| 227 | |
| 228 | static struct vote_clk gcc_blsp2_ahb_clk = { |
| 229 | .cbcr_reg = (uint32_t *) BLSP2_AHB_CBCR, |
| 230 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 231 | .en_mask = BIT(15), |
| 232 | |
| 233 | .c = { |
| 234 | .dbg_name = "gcc_blsp2_ahb_clk", |
| 235 | .ops = &clk_ops_vote, |
| 236 | }, |
| 237 | }; |
| 238 | |
| 239 | /* USB Clocks */ |
| 240 | static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = |
| 241 | { |
| 242 | F(75000000, gpll0, 8, 0, 0), |
| 243 | F_END |
| 244 | }; |
| 245 | |
| 246 | static struct rcg_clk usb_hs_system_clk_src = |
| 247 | { |
| 248 | .cmd_reg = (uint32_t *) USB_HS_SYSTEM_CMD_RCGR, |
| 249 | .cfg_reg = (uint32_t *) USB_HS_SYSTEM_CFG_RCGR, |
| 250 | |
| 251 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 252 | .freq_tbl = ftbl_gcc_usb_hs_system_clk, |
| 253 | .current_freq = &rcg_dummy_freq, |
| 254 | |
| 255 | .c = { |
| 256 | .dbg_name = "usb_hs_system_clk", |
| 257 | .ops = &clk_ops_rcg, |
| 258 | }, |
| 259 | }; |
| 260 | |
| 261 | static struct branch_clk gcc_usb_hs_system_clk = |
| 262 | { |
| 263 | .cbcr_reg = (uint32_t *) USB_HS_SYSTEM_CBCR, |
| 264 | .parent = &usb_hs_system_clk_src.c, |
| 265 | |
| 266 | .c = { |
| 267 | .dbg_name = "gcc_usb_hs_system_clk", |
| 268 | .ops = &clk_ops_branch, |
| 269 | }, |
| 270 | }; |
| 271 | |
| 272 | static struct branch_clk gcc_usb_hs_ahb_clk = |
| 273 | { |
| 274 | .cbcr_reg = (uint32_t *) USB_HS_AHB_CBCR, |
| 275 | .has_sibling = 1, |
| 276 | |
| 277 | .c = { |
| 278 | .dbg_name = "gcc_usb_hs_ahb_clk", |
| 279 | .ops = &clk_ops_branch, |
| 280 | }, |
| 281 | }; |
| 282 | |
| 283 | /* SDCC Clocks */ |
| 284 | static struct clk_freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] = |
| 285 | { |
| 286 | F( 144000, cxo, 16, 3, 25), |
| 287 | F( 400000, cxo, 12, 1, 4), |
| 288 | F( 20000000, gpll0, 15, 1, 2), |
| 289 | F( 25000000, gpll0, 12, 1, 2), |
| 290 | F( 50000000, gpll0, 12, 0, 0), |
Channagoud Kadabi | a66a6f2 | 2014-05-28 17:19:44 -0700 | [diff] [blame^] | 291 | F( 96000000, gpll4, 6, 0, 0), |
| 292 | F(192000000, gpll4, 2, 0, 0), |
| 293 | F(384000000, gpll4, 1, 0, 0), |
Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 294 | F_END |
| 295 | }; |
| 296 | |
| 297 | static struct rcg_clk sdcc1_apps_clk_src = |
| 298 | { |
| 299 | .cmd_reg = (uint32_t *) SDCC1_CMD_RCGR, |
| 300 | .cfg_reg = (uint32_t *) SDCC1_CFG_RCGR, |
| 301 | .m_reg = (uint32_t *) SDCC1_M, |
| 302 | .n_reg = (uint32_t *) SDCC1_N, |
| 303 | .d_reg = (uint32_t *) SDCC1_D, |
| 304 | |
| 305 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 306 | .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, |
| 307 | .current_freq = &rcg_dummy_freq, |
| 308 | |
| 309 | .c = { |
| 310 | .dbg_name = "sdc1_clk", |
| 311 | .ops = &clk_ops_rcg_mnd, |
| 312 | }, |
| 313 | }; |
| 314 | |
| 315 | static struct branch_clk gcc_sdcc1_apps_clk = |
| 316 | { |
| 317 | .cbcr_reg = (uint32_t *) SDCC1_APPS_CBCR, |
| 318 | .parent = &sdcc1_apps_clk_src.c, |
| 319 | |
| 320 | .c = { |
| 321 | .dbg_name = "gcc_sdcc1_apps_clk", |
| 322 | .ops = &clk_ops_branch, |
| 323 | }, |
| 324 | }; |
| 325 | |
| 326 | static struct branch_clk gcc_sdcc1_ahb_clk = |
| 327 | { |
| 328 | .cbcr_reg = (uint32_t *) SDCC1_AHB_CBCR, |
| 329 | .has_sibling = 1, |
| 330 | |
| 331 | .c = { |
| 332 | .dbg_name = "gcc_sdcc1_ahb_clk", |
| 333 | .ops = &clk_ops_branch, |
| 334 | }, |
| 335 | }; |
| 336 | |
Channagoud Kadabi | 3dcc4ed | 2014-04-10 14:59:41 -0700 | [diff] [blame] | 337 | static struct branch_clk gcc_sys_noc_usb30_axi_clk = { |
| 338 | .cbcr_reg = (uint32_t *) SYS_NOC_USB3_AXI_CBCR, |
| 339 | .has_sibling = 1, |
| 340 | |
| 341 | .c = { |
| 342 | .dbg_name = "sys_noc_usb30_axi_clk", |
| 343 | .ops = &clk_ops_branch, |
| 344 | }, |
| 345 | }; |
| 346 | |
| 347 | static struct branch_clk gcc_usb2b_phy_sleep_clk = { |
| 348 | .cbcr_reg = (uint32_t *) USB2B_PHY_SLEEP_CBCR, |
| 349 | .bcr_reg = (uint32_t *) USB2B_PHY_BCR, |
| 350 | .has_sibling = 1, |
| 351 | |
| 352 | .c = { |
| 353 | .dbg_name = "usb2b_phy_sleep_clk", |
| 354 | .ops = &clk_ops_branch, |
| 355 | }, |
| 356 | }; |
| 357 | |
| 358 | static struct clk_freq_tbl ftbl_gcc_usb30_master_clk[] = { |
| 359 | F( 125000000, gpll0, 1, 5, 24), |
| 360 | F_END |
| 361 | }; |
| 362 | |
| 363 | static struct rcg_clk usb30_master_clk_src = { |
| 364 | .cmd_reg = (uint32_t *) USB30_MASTER_CMD_RCGR, |
| 365 | .cfg_reg = (uint32_t *) USB30_MASTER_CFG_RCGR, |
| 366 | .m_reg = (uint32_t *) USB30_MASTER_M, |
| 367 | .n_reg = (uint32_t *) USB30_MASTER_N, |
| 368 | .d_reg = (uint32_t *) USB30_MASTER_D, |
| 369 | |
| 370 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 371 | .freq_tbl = ftbl_gcc_usb30_master_clk, |
| 372 | .current_freq = &rcg_dummy_freq, |
| 373 | |
| 374 | .c = { |
| 375 | .dbg_name = "usb30_master_clk_src", |
| 376 | .ops = &clk_ops_rcg, |
| 377 | }, |
| 378 | }; |
| 379 | |
| 380 | static struct branch_clk gcc_usb30_master_clk = { |
| 381 | .cbcr_reg = (uint32_t *) USB30_MASTER_CBCR, |
| 382 | .bcr_reg = (uint32_t *) USB_30_BCR, |
| 383 | .parent = &usb30_master_clk_src.c, |
| 384 | |
| 385 | .c = { |
| 386 | .dbg_name = "usb30_master_clk", |
| 387 | .ops = &clk_ops_branch, |
| 388 | }, |
| 389 | }; |
| 390 | |
| 391 | static struct clk_freq_tbl ftbl_gcc_usb30_mock_utmi_clk_src[] = { |
| 392 | F( 60000000, gpll0, 10, 0, 0), |
| 393 | F_END |
| 394 | }; |
| 395 | |
| 396 | static struct rcg_clk usb30_mock_utmi_clk_src = { |
| 397 | .cmd_reg = (uint32_t *) USB30_MOCK_UTMI_CMD_RCGR, |
| 398 | .cfg_reg = (uint32_t *) USB30_MOCK_UTMI_CFG_RCGR, |
| 399 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 400 | .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk_src, |
| 401 | .current_freq = &rcg_dummy_freq, |
| 402 | |
| 403 | .c = { |
| 404 | .dbg_name = "usb30_mock_utmi_clk_src", |
| 405 | .ops = &clk_ops_rcg, |
| 406 | }, |
| 407 | }; |
| 408 | |
| 409 | static struct branch_clk gcc_usb30_mock_utmi_clk = { |
| 410 | .cbcr_reg = (uint32_t *) USB30_MOCK_UTMI_CBCR, |
| 411 | .has_sibling = 0, |
| 412 | .parent = &usb30_mock_utmi_clk_src.c, |
| 413 | |
| 414 | .c = { |
| 415 | .dbg_name = "usb30_mock_utmi_clk", |
| 416 | .ops = &clk_ops_branch, |
| 417 | }, |
| 418 | }; |
| 419 | |
| 420 | static struct branch_clk gcc_usb30_sleep_clk = { |
| 421 | .cbcr_reg = (uint32_t *) USB30_SLEEP_CBCR, |
| 422 | .has_sibling = 1, |
| 423 | |
| 424 | .c = { |
| 425 | .dbg_name = "usb30_sleep_clk", |
| 426 | .ops = &clk_ops_branch, |
| 427 | }, |
| 428 | }; |
| 429 | |
| 430 | static struct clk_freq_tbl ftbl_gcc_usb30_phy_aux_clk_src[] = { |
| 431 | F( 1200000, cxo, 16, 0, 0), |
| 432 | F_END |
| 433 | }; |
| 434 | |
| 435 | static struct rcg_clk usb30_phy_aux_clk_src = { |
| 436 | .cmd_reg = (uint32_t *) USB30_PHY_AUX_CMD_RCGR, |
| 437 | .cfg_reg = (uint32_t *) USB30_PHY_AUX_CFG_RCGR, |
| 438 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 439 | .freq_tbl = ftbl_gcc_usb30_phy_aux_clk_src, |
| 440 | .current_freq = &rcg_dummy_freq, |
| 441 | |
| 442 | .c = { |
| 443 | .dbg_name = "usb30_phy_aux_clk_src", |
| 444 | .ops = &clk_ops_rcg, |
| 445 | }, |
| 446 | }; |
| 447 | |
| 448 | static struct branch_clk gcc_usb30_phy_aux_clk = { |
| 449 | .cbcr_reg = (uint32_t *)USB30_PHY_AUX_CBCR, |
| 450 | .has_sibling = 0, |
| 451 | .parent = &usb30_phy_aux_clk_src.c, |
| 452 | |
| 453 | .c = { |
| 454 | .dbg_name = "usb30_phy_aux_clk", |
| 455 | .ops = &clk_ops_branch, |
| 456 | }, |
| 457 | }; |
| 458 | |
| 459 | static struct branch_clk gcc_usb30_pipe_clk = { |
| 460 | .bcr_reg = (uint32_t *) USB30PHY_PHY_BCR, |
| 461 | .cbcr_reg = (uint32_t *) USB30_PHY_PIPE_CBCR, |
| 462 | .has_sibling = 1, |
| 463 | |
| 464 | .c = { |
| 465 | .dbg_name = "usb30_pipe_clk", |
| 466 | .ops = &clk_ops_branch, |
| 467 | }, |
| 468 | }; |
| 469 | |
| 470 | static struct reset_clk gcc_usb30_phy_reset = { |
| 471 | .bcr_reg = (uint32_t *)USB30_PHY_BCR, |
| 472 | |
| 473 | .c = { |
| 474 | .dbg_name = "usb30_phy_reset", |
| 475 | .ops = &clk_ops_rst, |
| 476 | }, |
| 477 | }; |
| 478 | |
Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 479 | /* Clock lookup table */ |
Channagoud Kadabi | 608b6a7 | 2014-04-14 13:58:03 -0700 | [diff] [blame] | 480 | static struct clk_lookup msm_8994_clocks[] = |
Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 481 | { |
| 482 | CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c), |
| 483 | CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c), |
| 484 | |
| 485 | CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c), |
| 486 | CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c), |
| 487 | |
| 488 | CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c), |
| 489 | CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c), |
Channagoud Kadabi | 3dcc4ed | 2014-04-10 14:59:41 -0700 | [diff] [blame] | 490 | |
| 491 | /* USB30 clocks */ |
| 492 | CLK_LOOKUP("usb2b_phy_sleep_clk", gcc_usb2b_phy_sleep_clk.c), |
| 493 | CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c), |
| 494 | CLK_LOOKUP("usb30_iface_clk", gcc_sys_noc_usb30_axi_clk), |
| 495 | CLK_LOOKUP("usb30_mock_utmi_clk", gcc_usb30_mock_utmi_clk.c), |
| 496 | CLK_LOOKUP("usb30_sleep_clk", gcc_usb30_sleep_clk.c), |
| 497 | CLK_LOOKUP("usb30_phy_aux_clk", gcc_usb30_phy_aux_clk.c), |
| 498 | CLK_LOOKUP("usb30_pipe_clk", gcc_usb30_pipe_clk.c), |
| 499 | CLK_LOOKUP("usb30_phy_reset", gcc_usb30_phy_reset.c), |
Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 500 | }; |
| 501 | |
| 502 | void platform_clock_init(void) |
| 503 | { |
Channagoud Kadabi | 608b6a7 | 2014-04-14 13:58:03 -0700 | [diff] [blame] | 504 | clk_init(msm_8994_clocks, ARRAY_SIZE(msm_8994_clocks)); |
Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 505 | } |