Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / lk / 60b5b5d39ea6650409fee71f932943ab48559817 / . / platform / qsd8k / arch_init.S
blob: 508330a578922625a7340dd1c2d0e39eeb484f25 [file] [log] [blame]
Brian Swetlanddfdb4612009-01-01 11:44:36 -0800[diff] [blame]1/*
2 * Copyright (c) 2008, QUALCOMM Incorporated.
3 * Copyright (c) 2008, Google Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in
13 * the documentation and/or other materials provided with the
14 * distribution.
15 * * Neither the name of Google, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
22 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
23 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
25 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
26 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
27 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
28 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
29 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 */
32
33
34/* TODO:
35 * - style cleanup
36 * - do we need to do *all* of this at boot?
37 */
38
39.text
40.code 32
41
42#define DSB .byte 0x4f, 0xf0, 0x7f, 0xf5
43#define ISB .byte 0x6f, 0xf0, 0x7f, 0xf5
44
45/*
46 ; LVT Ring Osc counter
47 ; used to determine sense amp settings
48 ; Clobbers registers r0, r4, r5, r6, r7, r9, r10, r11
49*/
50.equ CLK_CTL_BASE, 0xA8600000
51.equ A_GLBL_CLK_ENA, 0x0000
52.equ A_PRPH_WEB_NS_REG,0x0080
53.equ A_MSM_CLK_RINGOSC,0x00D0
54.equ A_TCXO_CNT, 0x00D4
55.equ A_TCXO_CNT_DONE, 0x00D8
56.equ A_RINGOSC_CNT, 0x00DC
57.equ A_MISC_CLK_CTL, 0x0108
58.equ CLK_TEST, 0xA8600114
59.equ SPSS_CSR_BASE, 0xAC100000
60.equ A_SCRINGOSC, 0x0510
61
62//;; Number of TCXO cycles to count ring oscillations
63.equ TCXO_CNT_VAL, 0x100
64
65SET_SA:
66 //; clear CLK_TEST[19] (RING_OSC_DBG_SEL) to count ring osc
67 LDR r5, =CLK_TEST
68 LDR r4, [r5]
69 BIC r4, r4, #0x80000
70 STR r4, [r5]
71
72 //; setup memory pointers
73 LDR r5, =CLK_CTL_BASE
74 LDR r6, =SPSS_CSR_BASE
75
76 //; PRPH_WEB_NS_REG = 0x00000A00 - enable root and crc
77 MOV r7, #0x0A00
78 STR r7,[r5,#A_PRPH_WEB_NS_REG]
79
80 //; MISC_CLK_CTL = 0x0 to disable tcxo4cnt, ringosccnt
81 MOV r0, #0
82 STR r0,[r5,#A_MISC_CLK_CTL]
83 DSB
84
85 //;; MSM_CLK_RINGOSC = 0x00000A0E
86 //;; the E selects Scorpion LVT RO(or DS) output,
87 //;; the A enables RO CRC and CXC
88 LDR r7, =0x0A0E
89 STR r7,[r5,#A_MSM_CLK_RINGOSC]
90
91 MOV r10, #0x1 //; SCRINGOSC[1:0] = 01
92 MOV r11, #TCXO_CNT_VAL
93
94 //;; initialize r9 - counts the 4 oscillators
95 MOV r9,#0x0
96 LDR r4,=RO_CNT
97
98ACQUIRE_FREQ:
99 //; SCRINGOSC[1:0] is set by r10, [13:11][10:8] = 0..7
100 //;MOV r7, r10
101 BIC r7, r10, #0x3F00
102 //;BFI r7, r9, #8, #3
103 ORR r7, r7, r9, LSL #8
104 //;BFI r7, r9, #11, #3
105 ORR r7, r7, r9, LSL #11
106 STR r7,[r6,#A_SCRINGOSC]
107
108 STR r11,[r5,#A_TCXO_CNT]
109 DSB //; Make sure the countdown value gets written before the ROs are enabled
110
111 //; MISC_CLK_CTL = 0x3 to enable tcxo4cnt, ringosccnt
112 MOV r7,#0x3
113 STR r7,[r5,#A_MISC_CLK_CTL]
114
115 //;; According to Raptor HDD, to read TCXO_CNT_DONE, use address for TCXO_CNT on pass1.
116 //;; Then read RINGOSC_CNT and store to debug_mem table
117WAIT_TCXO_CNT_DONE:
118 LDR r7,[r5,#A_TCXO_CNT_DONE]
119 CMP r7,#0x1
120 BNE WAIT_TCXO_CNT_DONE
121 LDR r7,[r5,#A_RINGOSC_CNT]
122 STR r7,[r4],#0x04 //; post-indexed update r4 to next empty table entry
123
124 //; MISC_CLK_CTL = 0x0 to disable tcxo4cnt, ringosccnt
125 STR r0,[r5,#A_MISC_CLK_CTL]
126 DSB
127
128 //;; move to next oscillator - r9 counts oscillators 0..7
129 ADD r9,r9,#1
130 CMP r9,#0x4
131 BLT ACQUIRE_FREQ
132
133 //; average the 4 counts
134 LDR r4,=RO_CNT
135 LDR r5, [r4], #0x4
136 LDR r6, [r4], #0x4
137 ADD r5, r5, r6
138 LDR r6, [r4], #0x4
139 ADD r5, r5, r6
140 LDR r6, [r4], #0x4
141 ADD r5, r5, r6
142 MOV r5, r5, LSR #2
143
144.equ SLOW_THRESHOLD, 0x0E10
145.equ NOM_THRESHOLD, 0x123A
146
147 //; compare average to slow part threshold
148 LDR r4, =SLOW_THRESHOLD
149 CMP r5, r4
150 LDRLT r4, =SLOW_SA
151 BLT WRITE_SA
152
153 //; compare average to nominal part threshold
154 LDR r4, =NOM_THRESHOLD
155 CMP r5, r4
156 LDRLT r4, =NOM_SA
157 BLT WRITE_SA
158
159 //; must be fast part
160 LDR r4, =FAST_SA
161 B WRITE_SA
162
163
164SLOW_SA:
165 .word 0x38001C00 //; PVR0F0
166 .word 0x1C000000 //; PVR2F0
167 .word 0x00212102 //; L2VR3F1
168
169NOM_SA:
170 .word 0x38001C00 //; PVR0F0
171 .word 0x1C000000 //; PVR2F0
172 .word 0x00212102 //; L2VR3F1
173
174FAST_SA:
175 .word 0x38003C00 //; PVR0F0
176 .word 0x1C000000 //; PVR2F0
177 .word 0x00212102 //; L2VR3F1
178
179RO_CNT:
180 .word 0x0
181 .word 0x0
182 .word 0x0
183 .word 0x0
184
185WRITE_SA:
186 //; write the sense amp settings
187
188 //; PVR0F0[15:10] = I$
189 LDR r5, [r4], #4
190 //;WCP15_PVR0F0 r5
191 MCR p15,0x0,r5,c15,c15,0
192
193 //; PVR2F0[31:26] = D$
194 LDR r5, [r4], #4
195 //;WCP15_PVR2F0 r5
196 MCR p15,0x2,r5,c15,c15,0
197
198 //; L2VR3F1[23:0]
199 LDR r5, [r4], #4
200 //;WCP15_L2VR3F1 r5
201 MCR p15,0x3,r5,c15,c15,1
202
203 ISB
204
205 BX lr
206
207.globl __cpu_early_init
208__cpu_early_init:
Brian Swetlanddfdb4612009-01-01 11:44:36 -0800[diff] [blame]209 //; Zero out r0 for use throughout this code. All other GPRs
210 //; (r1-r3) are set throughout this code to help establish
211 //; a consistent startup state for any code that follows.
212 //; Users should add code at the end of this routine to establish
213 //; their own stack address (r13), add translation page tables, enable
214 //; the caches, etc.
215 MOV r0, #0x0
216
217 //; Write L2VR3F1 to make L2 array work properly at 998 on Raptor2
218 LDR r1, =0x00212102 //; the l2 timing watch out on P2
219 MCR p15, 3, r1, c15, c15, 1 //; WCP15_L2VR3F1
220 DSB
221 ISB
222
223 //; write the value for Icache to run at 998 on Raptor2
224 LDR r1, =0x3800E000
225 MCR p15, 0, r1, c15, c15, 0 //; WCP15_PVR0F0
226 ISB
227
228 //; DCIALL to invalidate L2 cache bank (needs to be run 4 times, once per bank)
229 //; This must be done early in code (prior to enabling the caches)
230 MOV r1, #0x2
231 MCR p15, 0, r1, c9, c0, 6 //; DCIALL bank D ([15:14] == 2'b00)
232 ORR r1, r1, #0x00004000
233 MCR p15, 0, r1, c9, c0, 6 //; DCIALL bank C ([15:14] == 2'b01)
234 ADD r1, r1, #0x00004000
235 MCR p15, 0, r1, c9, c0, 6 //; DCIALL bank B ([15:14] == 2'b10)
236 ADD r1, r1, #0x00004000
237 MCR p15, 0, r1, c9, c0, 6 //; DCIALL bank A ([15:14] == 2'b11)
238
239 //; Initialize the BPCR - setup Global History Mask (GHRM) to all 1's
240 //; and have all address bits (AM) participate.
241 //; Different settings can be used to improve performance
242 .word 0xe30011ff // MOVW r1, #0x01FF
243 .word 0xe34011ff // MOVT r1, #0x01FF
244 MCR p15, 7, r1, c15, c0, 2 //; WCP15_BPCR
245
246
247 //; Initialize all I$ Victim Registers to 0 for startup
248 MCR p15, 0, r0, c9, c1, 0 //; WCP15_ICVIC0 r0
249 MCR p15, 0, r0, c9, c1, 1 //; WCP15_ICVIC1 r0
250 MCR p15, 0, r0, c9, c1, 2 //; WCP15_ICVIC2 r0
251 MCR p15, 0, r0, c9, c1, 3 //; WCP15_ICVIC3 r0
252 MCR p15, 0, r0, c9, c1, 4 //; WCP15_ICVIC4 r0
253 MCR p15, 0, r0, c9, c1, 5 //; WCP15_ICVIC5 r0
254 MCR p15, 0, r0, c9, c1, 6 //; WCP15_ICVIC5 r0
255 MCR p15, 0, r0, c9, c1, 7 //; WCP15_ICVIC7 r0
256
257 //; Initialize all I$ Locked Victim Registers (Unlocked Floors) to 0
258 MCR p15, 1, r0, c9, c1, 0 //; WCP15_ICFLOOR0 r0
259 MCR p15, 1, r0, c9, c1, 1 //; WCP15_ICFLOOR1 r0
260 MCR p15, 1, r0, c9, c1, 2 //; WCP15_ICFLOOR2 r0
261 MCR p15, 1, r0, c9, c1, 3 //; WCP15_ICFLOOR3 r0
262 MCR p15, 1, r0, c9, c1, 4 //; WCP15_ICFLOOR4 r0
263 MCR p15, 1, r0, c9, c1, 5 //; WCP15_ICFLOOR5 r0
264 MCR p15, 1, r0, c9, c1, 6 //; WCP15_ICFLOOR6 r0
265 MCR p15, 1, r0, c9, c1, 7 //; WCP15_ICFLOOR7 r0
266
267 //; Initialize all D$ Victim Registers to 0
268 MCR p15, 2, r0, c9, c1, 0 //; WP15_DCVIC0 r0
269 MCR p15, 2, r0, c9, c1, 1 //; WP15_DCVIC1 r0
270 MCR p15, 2, r0, c9, c1, 2 //; WP15_DCVIC2 r0
271 MCR p15, 2, r0, c9, c1, 3 //; WP15_DCVIC3 r0
272 MCR p15, 2, r0, c9, c1, 4 //; WP15_DCVIC4 r0
273 MCR p15, 2, r0, c9, c1, 5 //; WP15_DCVIC5 r0
274 MCR p15, 2, r0, c9, c1, 6 //; WP15_DCVIC6 r0
275 MCR p15, 2, r0, c9, c1, 7 //; WP15_DCVIC7 r0
276
277 //; Initialize all D$ Locked VDCtim Registers (Unlocked Floors) to 0
278 MCR p15, 3, r0, c9, c1, 0 //; WCP15_DCFLOOR0 r0
279 MCR p15, 3, r0, c9, c1, 1 //; WCP15_DCFLOOR1 r0
280 MCR p15, 3, r0, c9, c1, 2 //; WCP15_DCFLOOR2 r0
281 MCR p15, 3, r0, c9, c1, 3 //; WCP15_DCFLOOR3 r0
282 MCR p15, 3, r0, c9, c1, 4 //; WCP15_DCFLOOR4 r0
283 MCR p15, 3, r0, c9, c1, 5 //; WCP15_DCFLOOR5 r0
284 MCR p15, 3, r0, c9, c1, 6 //; WCP15_DCFLOOR6 r0
285 MCR p15, 3, r0, c9, c1, 7 //; WCP15_DCFLOOR7 r0
286
287 //; Initialize ASID to zero
288 MCR p15, 0, r0, c13, c0, 1 //; WCP15_CONTEXTIDR r0
289
290 //; ICIALL to invalidate entire I-Cache
291 MCR p15, 0, r0, c7, c5, 0 //; ICIALLU
292
293 //; DCIALL to invalidate entire D-Cache
294 MCR p15, 0, r0, c9, c0, 6 //; DCIALL r0
295
296
297 //; The VBAR (Vector Base Address Register) should be initialized
298 //; early in your code. We are setting it to zero
299 MCR p15, 0, r0, c12, c0, 0 //; WCP15_VBAR r0
300
301 //; Ensure the MCR's above have completed their operation before continuing
302 DSB
303 ISB
304
305 //;-------------------------------------------------------------------
306 //; There are a number of registers that must be set prior to enabling
307 //; the MMU. The DCAR is one of these registers. We are setting
308 //; it to zero (no access) to easily detect improper setup in subsequent
309 //; code sequences
310 //;-------------------------------------------------------------------
311 //; Setup DACR (Domain Access Control Register) to zero
312 MCR p15, 0, r0, c3, c0, 0 //; WCP15_DACR r0
313
314 //; Setup DCLKCR to allow normal D-Cache line fills
315 MCR p15, 1, r0, c9, c0, 7 //; WCP15_DCLKCR r0
316
317 //; Setup the TLBLKCR
318 //; Victim = 6'b000000; Floor = 6'b000000;
319 //; IASIDCFG = 2'b00 (State-Machine); IALLCFG = 2'b01 (Flash); BNA = 1'b0;
320 MOV r1, #0x02
321 MCR p15, 0, r1, c10, c1, 3 //; WCP15_TLBLKCR r1
322
323 //;Make sure TLBLKCR is complete before continuing
324 ISB
325
326 //; Invalidate the UTLB
327 MCR p15, 0, r0, c8, c7, 0 //; UTLBIALL
328
329 //; Make sure UTLB request has been presented to macro before continuing
330 ISB
331
332 //; setup L2CR1 to some default Instruction and data prefetching values
333 //; Users may want specific settings for various performance enhancements
334 MCR p15, 3, r0, c15, c0, 3 //; WCP15_L2CR1 r0
335
336
337 //; Enable Z bit to enable branch prediction (default is off)
338
339 MRC p15, 0, r2, c1, c0, 0 //; RCP15_SCTLR r2
340 ORR r2, r2, #0x00000800
341 MCR p15, 0, r2, c1, c0, 0 //; WCP15_SCTLR r2
342
343 mov r1, lr
344 //; Make sure Link stack is initialized with branch and links to sequential addresses
345 //; This aids in creating a predictable startup environment
346 BL SEQ1
347SEQ1: BL SEQ2
348SEQ2: BL SEQ3
349SEQ3: BL SEQ4
350SEQ4: BL SEQ5
351SEQ5: BL SEQ6
352SEQ6: BL SEQ7
353SEQ7: BL SEQ8
354SEQ8:
355
356 mov lr, r1
357
358 //; REMOVE FOLLOWING THREE INSTRUCTIONS WHEN POWER COLLAPSE IS ENA
359 //;Make sure the DBGOSLSR[LOCK] bit is cleared to allow access to the debug registers
360 //; Writing anything but the "secret code" to the DBGOSLAR clears the DBGOSLSR[LOCK] bit
361 MCR p14, 0, r0, c1, c0, 4 //; WCP14_DBGOSLAR r0
362
363
364 //; Read the DBGPRSR to clear the DBGPRSR[STICKYPD]
365 //; Any read to DBGPRSR clear the STICKYPD bit
366 //; ISB guarantees the read completes before attempting to
367 //; execute a CP14 instruction.
368 MRC p14, 0, r3, c1, c5, 4 //; RCP14_DBGPRSR r3
369 ISB
370
371 //; Initialize the Watchpoint Control Registers to zero (optional)
372//;;; MCR p14, 0, r0, c0, c0, 7 ; WCP14_DBGWCR0 r0
373//;;; MCR p14, 0, r0, c0, c1, 7 ; WCP14_DBGWCR1 r0
374
375 //;----------------------------------------------------------------------
376 //; Enabling Error reporting is something users may want to do at
377 //; some other point in time. We have chosen some default settings
378 //; that should be reviewed. Most of these registers come up in an
379 //; unpredictable state after reset.
380 //;----------------------------------------------------------------------
381//;Start of error and control setting
382
383 //; setup L2CR0 with various L2/TCM control settings
384 //; enable out of order bus attributes and error reporting
385 //; this register comes up unpredictable after reset
386 .word 0xe3001f0f // MOVW r1, #0x0F0F
387 .word 0xe34c1005 // MOVT r1, #0xC005
388
389 MCR p15, 3, r1, c15, c0, 1 //; WCP15_L2CR0 r1
390
391 //; setup L2CPUCR
392 MOV r2, #0
393 MCR p15, 3, r2, c15, c0, 2 //; WCP15_L2CPUCR r2
394
395 //; setup SPCR
396 //; enable all error reporting (reset value is unpredicatble for most bits)
397 MOV r3, #0x0F
398 MCR p15, 0, r3, c9, c7, 0 //; WCP15_SPCR r3
399
400
401 //; setup DMACHCRs (reset value unpredictable)
402 //; control setting and enable all error reporting
403 MOV r1, #0x0F
404
405 //; DMACHCR0 = 0000000F
406 MOV r2, #0x00 //; channel 0
407 MCR p15, 0, r2, c11, c0, 0 //; WCP15_DMASELR r2
408 MCR p15, 0, r1, c11, c0, 2 //; WCP15_DMACHCR r1
409
410 //; DMACHCR1 = 0000000F
411 MOV r2, #0x01 //; channel 1
412 MCR p15, 0, r2, c11, c0, 0 //; WCP15_DMASELR r2
413 MCR p15, 0, r1, c11, c0, 2 //; WCP15_DMACHCR r1
414
415 //; DMACHCR2 = 0000000F
416 MOV r2, #0x02 //; channel 2
417 MCR p15, 0, r2, c11, c0, 0 //; WCP15_DMASELR r2
418 MCR p15, 0, r1, c11, c0, 2 //; WCP15_DMACHCR r1
419
420 //; DMACHCR3 = 0000000F
421 MOV r2, #0x03 //; channel 3
422 MCR p15, 0, r2, c11, c0, 0 //; WCP15_DMASELR r2
423 MCR p15, 0, r1, c11, c0, 2 //; WCP15_DMACHCR r1
424
425 //; Set ACTLR (reset unpredictable)
426 //; Set AVIVT control, error reporting, etc.
427 MOV r3, #0x04
428
429 //; keep d-cache disabled on Raptor Rev 1.0 silicon
Brian Swetland89f67ec2009-01-29 17:23:08 -0800[diff] [blame]430 //; orr r3, r3, #0x4000 //;disable dcache
Brian Swetlanddfdb4612009-01-01 11:44:36 -0800[diff] [blame]431 MCR p15, 0, r3, c1, c0, 1 //; WCP15_ACTLR r3
432
433//;End of error and control setting
434
435 //;----------------------------------------------------------------------
436 //; Unlock ETM and read StickyPD to halt the ETM clocks from running.
437 //; This is required for power saving whether the ETM is used or not.
438 //;----------------------------------------------------------------------
439
440 //;Clear ETMOSLSR[LOCK] bit
441 MOV r1, #0x00000000
442 MCR p14, 1, r1, c1, c0, 4 //; WCP14_ETMOSLAR r1
443
444 //;Clear ETMPDSR[STICKYPD] bit
445 MRC p14, 1, r2, c1, c5, 4 //; RCP14_ETMPDSR r2
446
447/*
448#ifdef APPSBL_ETM_ENABLE
449 ;----------------------------------------------------------------------
450 ; Optionally Enable the ETM (Embedded Trace Macro) which is used for debug
451 ;----------------------------------------------------------------------
452
453 ; enable ETM clock if disabled
454 MRC p15, 7, r1, c15, c0, 5 ; RCP15_CPMR r1
455 ORR r1, r1, #0x00000008
456 MCR p15, 7, r1, c15, c0, 5 ; WCP15_CPMR r1
457 ISB
458
459 ; set trigger event to counter1 being zero
460 MOV r3, #0x00000040
461 MCR p14, 1, r3, c0, c2, 0 ; WCP14_ETMTRIGGER r3
462
463 ; clear ETMSR
464 MOV r2, #0x00000000
465 MCR p14, 1, r2, c0, c4, 0 ; WCP14_ETMSR r2
466
467 ; clear trace enable single address comparator usage
468 MCR p14, 1, r2, c0, c7, 0 ; WCP14_ETMTECR2 r2
469
470 ; set trace enable to always
471 MOV r2, #0x0000006F
472 MCR p14, 1, r2, c0, c8, 0 ; WCP14_ETMTEEVR r2
473
474 ; clear trace enable address range comparator usage and exclude nothing
475 MOV r2, #0x01000000
476 MCR p14, 1, r2, c0, c9, 0 ; WCP14_ETMTECR1 r2
477
478 ; set view data to always
479 MOV r2, #0x0000006F
480 MCR p14, 1, r2, c0, c12, 0 ; WCP14_ETMVDEVR r2
481
482 ; clear view data single address comparator usage
483 MOV r2, #0x00000000
484 MCR p14, 1, r2, c0, c13, 0 ; WCP14_ETMVDCR1 r2
485
486 ; clear view data address range comparator usage and exclude nothing
487 MOV r2, #0x00010000
488 MCR p14, 1, r2, c0, c15, 0 ; WCP14_ETMVDCR3 r2
489
490 ; set counter1 to 194
491 MOV r2, #0x000000C2
492 MCR p14, 1, r2, c0, c0, 5 ; WCP14_ETMCNTRLDVR1 r2
493
494 ; set counter1 to never reload
495 MOV r2, #0x0000406F
496 MCR p14, 1, r2, c0, c8, 5 ; WCP14_ETMCNTRLDEVR1 r2
497
498 ; set counter1 to decrement every cycle
499 MOV r2, #0x0000006F
500 MCR p14, 1, r2, c0, c4, 5 ; WCP14_ETMCNTENR1 r2
501
502 ; Set trace synchronization frequency 1024 bytes
503 MOV r2, #0x00000400
504 MCR p14, 1, r2, c0, c8, 7 ; WCP14_ETMSYNCFR r2
505
506 ; Program etm control register
507 ; - Set the CPU to ETM clock ratio to 1:1
508 ; - Set the ETM to perform data address tracing
509 MOV r2, #0x00002008
510 MCR p14, 1, r2, c0, c0, 0 ; WCP14_ETMCR r2
511 ISB
512#endif *//* APPSBL_ETM_ENABLE */
513
514/*
515#ifdef APPSBL_VFP_ENABLE
516 ;----------------------------------------------------------------------
517 ; Perform the following operations if you intend to make use of
518 ; the VFP/Neon unit. Note that the FMXR instruction requires a CPU ID
519 ; indicating the VFP unit is present (i.e.Cortex-A8). .
520 ; Some tools will require full double precision floating point support
521 ; which will become available in Scorpion pass 2
522 ;----------------------------------------------------------------------
523 ; allow full access to CP 10 and 11 space for VFP/NEON use
524 MRC p15, 0, r1, c1, c0, 2 ; Read CP Access Control Register
525 ORR r1, r1, #0x00F00000 ; enable full access for p10,11
526 MCR p15, 0, r1, c1, c0, 2 ; Write CPACR
527
528 ;make sure the CPACR is complete before continuing
529 ISB
530
531 ; Enable VFP itself (certain OSes may want to dynamically set/clear
532 ; the enable bit based on the application being executed
533 MOV r1, #0x40000000
534 FMXR FPEXC, r1
535#endif *//* APPSBL_VFP_ENABLE */
536
537 /* we have no stack, so just tail-call into the SET_SA routine... */
538 b SET_SA
539
540.ltorg