Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 1 | /* Copyright (c) 2013, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions |
| 5 | * are met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer in |
| 10 | * the documentation and/or other materials provided with the |
| 11 | * distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 19 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 20 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 22 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
| 23 | * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
| 24 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 25 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 26 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 27 | * SUCH DAMAGE. |
| 28 | */ |
| 29 | |
| 30 | #include <debug.h> |
| 31 | #include <smem.h> |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 32 | #include <err.h> |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 33 | #include <msm_panel.h> |
Arpita Banerjee | 0906ffd | 2013-05-24 16:25:38 -0700 | [diff] [blame] | 34 | #include <mipi_dsi.h> |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 35 | #include <pm8x41.h> |
| 36 | #include <pm8x41_wled.h> |
| 37 | #include <board.h> |
| 38 | #include <mdp5.h> |
Aravind Venkateswaran | fada7f3 | 2013-09-19 15:23:34 -0700 | [diff] [blame] | 39 | #include <scm.h> |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 40 | #include <platform/gpio.h> |
| 41 | #include <platform/iomap.h> |
| 42 | #include <target/display.h> |
| 43 | |
Casey Piper | cbdfbd2 | 2013-08-14 17:22:16 -0700 | [diff] [blame] | 44 | #include "include/panel.h" |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 45 | #include "include/display_resource.h" |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 46 | |
Dhaval Patel | 815567c | 2013-07-31 11:13:25 -0700 | [diff] [blame] | 47 | #define HFPLL_LDO_ID 8 |
| 48 | |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 49 | static struct pm8x41_wled_data wled_ctrl = { |
rayzhang | a3667cd | 2013-07-01 12:22:54 +0800 | [diff] [blame] | 50 | .mod_scheme = 0x00, |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 51 | .led1_brightness = (0x0F << 8) | 0xEF, |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 52 | .max_duty_cycle = 0x01, |
rayzhang | a3667cd | 2013-07-01 12:22:54 +0800 | [diff] [blame] | 53 | .ovp = 0x0, |
Zhenhua Huang | d5355cb | 2013-09-04 16:03:01 +0800 | [diff] [blame] | 54 | .full_current_scale = 0x19, |
| 55 | .fdbck = 0x1 |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 56 | }; |
| 57 | |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 58 | static uint32_t dsi_pll_enable_seq_m(uint32_t ctl_base) |
| 59 | { |
| 60 | uint32_t i = 0; |
| 61 | uint32_t pll_locked = 0; |
| 62 | |
| 63 | mdss_dsi_uniphy_pll_sw_reset(ctl_base); |
| 64 | |
| 65 | /* |
| 66 | * Add hardware recommended delays between register writes for |
| 67 | * the updates to take effect. These delays are necessary for the |
| 68 | * PLL to successfully lock |
| 69 | */ |
| 70 | writel(0x01, ctl_base + 0x0220); /* GLB CFG */ |
| 71 | udelay(200); |
| 72 | writel(0x05, ctl_base + 0x0220); /* GLB CFG */ |
| 73 | udelay(200); |
| 74 | writel(0x0f, ctl_base + 0x0220); /* GLB CFG */ |
| 75 | udelay(1000); |
| 76 | |
| 77 | mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base); |
| 78 | pll_locked = readl(ctl_base + 0x02c0) & 0x01; |
| 79 | for (i = 0; (i < 4) && !pll_locked; i++) { |
| 80 | writel(0x07, ctl_base + 0x0220); /* GLB CFG */ |
| 81 | if (i != 0) |
| 82 | writel(0x34, ctl_base + 0x00270); /* CAL CFG1*/ |
| 83 | udelay(1); |
| 84 | writel(0x0f, ctl_base + 0x0220); /* GLB CFG */ |
| 85 | udelay(1000); |
| 86 | mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base); |
| 87 | pll_locked = readl(ctl_base + 0x02c0) & 0x01; |
| 88 | } |
| 89 | |
| 90 | return pll_locked; |
| 91 | } |
| 92 | |
| 93 | static uint32_t dsi_pll_enable_seq_d(uint32_t ctl_base) |
| 94 | { |
| 95 | uint32_t pll_locked = 0; |
| 96 | |
| 97 | mdss_dsi_uniphy_pll_sw_reset(ctl_base); |
| 98 | |
| 99 | /* |
| 100 | * Add hardware recommended delays between register writes for |
| 101 | * the updates to take effect. These delays are necessary for the |
| 102 | * PLL to successfully lock |
| 103 | */ |
| 104 | writel(0x01, ctl_base + 0x0220); /* GLB CFG */ |
| 105 | udelay(200); |
| 106 | writel(0x05, ctl_base + 0x0220); /* GLB CFG */ |
| 107 | udelay(200); |
| 108 | writel(0x07, ctl_base + 0x0220); /* GLB CFG */ |
| 109 | udelay(200); |
| 110 | writel(0x05, ctl_base + 0x0220); /* GLB CFG */ |
| 111 | udelay(200); |
| 112 | writel(0x07, ctl_base + 0x0220); /* GLB CFG */ |
| 113 | udelay(200); |
| 114 | writel(0x0f, ctl_base + 0x0220); /* GLB CFG */ |
| 115 | udelay(1000); |
| 116 | |
| 117 | mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base); |
| 118 | pll_locked = readl(ctl_base + 0x02c0) & 0x01; |
| 119 | |
| 120 | return pll_locked; |
| 121 | } |
| 122 | |
| 123 | static uint32_t dsi_pll_enable_seq_f1(uint32_t ctl_base) |
| 124 | { |
| 125 | uint32_t pll_locked = 0; |
| 126 | |
| 127 | mdss_dsi_uniphy_pll_sw_reset(ctl_base); |
| 128 | |
| 129 | /* |
| 130 | * Add hardware recommended delays between register writes for |
| 131 | * the updates to take effect. These delays are necessary for the |
| 132 | * PLL to successfully lock |
| 133 | */ |
| 134 | writel(0x01, ctl_base + 0x0220); /* GLB CFG */ |
| 135 | udelay(200); |
| 136 | writel(0x05, ctl_base + 0x0220); /* GLB CFG */ |
| 137 | udelay(200); |
| 138 | writel(0x0f, ctl_base + 0x0220); /* GLB CFG */ |
| 139 | udelay(200); |
| 140 | writel(0x0d, ctl_base + 0x0220); /* GLB CFG */ |
| 141 | udelay(200); |
| 142 | writel(0x0f, ctl_base + 0x0220); /* GLB CFG */ |
| 143 | udelay(1000); |
| 144 | |
| 145 | mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base); |
| 146 | pll_locked = readl(ctl_base + 0x02c0) & 0x01; |
| 147 | |
| 148 | return pll_locked; |
| 149 | } |
| 150 | |
| 151 | static uint32_t dsi_pll_enable_seq_c(uint32_t ctl_base) |
| 152 | { |
| 153 | uint32_t pll_locked = 0; |
| 154 | |
| 155 | mdss_dsi_uniphy_pll_sw_reset(ctl_base); |
| 156 | |
| 157 | /* |
| 158 | * Add hardware recommended delays between register writes for |
| 159 | * the updates to take effect. These delays are necessary for the |
| 160 | * PLL to successfully lock |
| 161 | */ |
| 162 | writel(0x01, ctl_base + 0x0220); /* GLB CFG */ |
| 163 | udelay(200); |
| 164 | writel(0x05, ctl_base + 0x0220); /* GLB CFG */ |
| 165 | udelay(200); |
| 166 | writel(0x0f, ctl_base + 0x0220); /* GLB CFG */ |
| 167 | udelay(1000); |
| 168 | |
| 169 | mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base); |
| 170 | pll_locked = readl(ctl_base + 0x02c0) & 0x01; |
| 171 | |
| 172 | return pll_locked; |
| 173 | } |
| 174 | |
| 175 | static uint32_t dsi_pll_enable_seq_e(uint32_t ctl_base) |
| 176 | { |
| 177 | uint32_t pll_locked = 0; |
| 178 | |
| 179 | mdss_dsi_uniphy_pll_sw_reset(ctl_base); |
| 180 | |
| 181 | /* |
| 182 | * Add hardware recommended delays between register writes for |
| 183 | * the updates to take effect. These delays are necessary for the |
| 184 | * PLL to successfully lock |
| 185 | */ |
| 186 | writel(0x01, ctl_base + 0x0220); /* GLB CFG */ |
| 187 | udelay(200); |
| 188 | writel(0x05, ctl_base + 0x0220); /* GLB CFG */ |
| 189 | udelay(200); |
| 190 | writel(0x0d, ctl_base + 0x0220); /* GLB CFG */ |
| 191 | udelay(1); |
| 192 | writel(0x0f, ctl_base + 0x0220); /* GLB CFG */ |
| 193 | udelay(1000); |
| 194 | |
| 195 | mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base); |
| 196 | pll_locked = readl(ctl_base + 0x02c0) & 0x01; |
| 197 | |
| 198 | return pll_locked; |
| 199 | } |
| 200 | |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 201 | int target_backlight_ctrl(uint8_t enable) |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 202 | { |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 203 | dprintf(SPEW, "target_backlight_ctrl\n"); |
| 204 | |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 205 | pm8x41_wled_config(&wled_ctrl); |
| 206 | pm8x41_wled_sink_control(1); |
| 207 | pm8x41_wled_iled_sync_control(1); |
| 208 | pm8x41_wled_enable(1); |
| 209 | |
| 210 | return 0; |
| 211 | } |
| 212 | |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 213 | static void dsi_pll_enable_seq(uint32_t ctl_base) |
| 214 | { |
| 215 | if (dsi_pll_enable_seq_m(ctl_base)) { |
| 216 | } else if (dsi_pll_enable_seq_d(ctl_base)) { |
| 217 | } else if (dsi_pll_enable_seq_d(ctl_base)) { |
| 218 | } else if (dsi_pll_enable_seq_f1(ctl_base)) { |
| 219 | } else if (dsi_pll_enable_seq_c(ctl_base)) { |
| 220 | } else if (dsi_pll_enable_seq_e(ctl_base)) { |
| 221 | } else { |
| 222 | dprintf(CRITICAL, "Not able to enable the pll\n"); |
| 223 | } |
| 224 | } |
| 225 | |
Arpita Banerjee | 0906ffd | 2013-05-24 16:25:38 -0700 | [diff] [blame] | 226 | int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo) |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 227 | { |
Aravind Venkateswaran | fada7f3 | 2013-09-19 15:23:34 -0700 | [diff] [blame] | 228 | int32_t ret; |
Arpita Banerjee | 0906ffd | 2013-05-24 16:25:38 -0700 | [diff] [blame] | 229 | struct mdss_dsi_pll_config *pll_data; |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 230 | dprintf(SPEW, "target_panel_clock\n"); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 231 | |
Arpita Banerjee | 0906ffd | 2013-05-24 16:25:38 -0700 | [diff] [blame] | 232 | pll_data = pinfo->mipi.dsi_pll_config; |
| 233 | |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 234 | if (enable) { |
| 235 | mdp_gdsc_ctrl(enable); |
Aravind Venkateswaran | 5f54692 | 2013-09-19 15:13:43 -0700 | [diff] [blame] | 236 | mmss_bus_clocks_enable(); |
| 237 | mdp_clock_enable(); |
Aravind Venkateswaran | fada7f3 | 2013-09-19 15:23:34 -0700 | [diff] [blame] | 238 | ret = restore_secure_cfg(SECURE_DEVICE_MDSS); |
| 239 | if (ret) { |
| 240 | dprintf(CRITICAL, |
| 241 | "%s: Failed to restore MDP security configs", |
| 242 | __func__); |
| 243 | mdp_clock_disable(); |
| 244 | mmss_bus_clocks_disable(); |
| 245 | mdp_gdsc_ctrl(0); |
| 246 | return ret; |
| 247 | } |
Casey Piper | aee8120 | 2013-08-26 11:14:02 -0700 | [diff] [blame] | 248 | mdss_dsi_auto_pll_config(MIPI_DSI0_BASE, pll_data); |
| 249 | dsi_pll_enable_seq(MIPI_DSI0_BASE); |
Aravind Venkateswaran | 5f54692 | 2013-09-19 15:13:43 -0700 | [diff] [blame] | 250 | mmss_dsi_clocks_enable(pll_data->pclk_m, |
Arpita Banerjee | 0906ffd | 2013-05-24 16:25:38 -0700 | [diff] [blame] | 251 | pll_data->pclk_n, |
| 252 | pll_data->pclk_d); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 253 | } else if(!target_cont_splash_screen()) { |
Aravind Venkateswaran | 5f54692 | 2013-09-19 15:13:43 -0700 | [diff] [blame] | 254 | mmss_dsi_clocks_disable(); |
| 255 | mdp_clock_disable(); |
| 256 | mmss_bus_clocks_disable(); |
| 257 | mdp_gdsc_ctrl(enable); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 258 | } |
| 259 | |
| 260 | return 0; |
| 261 | } |
| 262 | |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 263 | int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq, |
| 264 | struct msm_panel_info *pinfo) |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 265 | { |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 266 | int ret = NO_ERROR; |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 267 | if (enable) { |
Aravind Venkateswaran | af24121 | 2013-11-04 16:46:46 -0800 | [diff] [blame^] | 268 | if (pinfo->mipi.use_enable_gpio) { |
| 269 | gpio_tlmm_config(enable_gpio.pin_id, 0, |
| 270 | enable_gpio.pin_direction, enable_gpio.pin_pull, |
| 271 | enable_gpio.pin_strength, |
| 272 | enable_gpio.pin_state); |
| 273 | |
| 274 | gpio_set_dir(enable_gpio.pin_id, 2); |
| 275 | } |
| 276 | |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 277 | gpio_tlmm_config(reset_gpio.pin_id, 0, |
| 278 | reset_gpio.pin_direction, reset_gpio.pin_pull, |
| 279 | reset_gpio.pin_strength, reset_gpio.pin_state); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 280 | |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 281 | gpio_set_dir(reset_gpio.pin_id, 2); |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 282 | |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 283 | gpio_set_value(reset_gpio.pin_id, resetseq->pin_state[0]); |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 284 | mdelay(resetseq->sleep[0]); |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 285 | gpio_set_value(reset_gpio.pin_id, resetseq->pin_state[1]); |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 286 | mdelay(resetseq->sleep[1]); |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 287 | gpio_set_value(reset_gpio.pin_id, resetseq->pin_state[2]); |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 288 | mdelay(resetseq->sleep[2]); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 289 | } else if(!target_cont_splash_screen()) { |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 290 | gpio_set_value(reset_gpio.pin_id, 0); |
Aravind Venkateswaran | af24121 | 2013-11-04 16:46:46 -0800 | [diff] [blame^] | 291 | if (pinfo->mipi.use_enable_gpio) |
| 292 | gpio_set_value(enable_gpio.pin_id, 0); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 293 | } |
| 294 | |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 295 | return ret; |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 296 | } |
| 297 | |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 298 | int target_ldo_ctrl(uint8_t enable) |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 299 | { |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 300 | uint32_t ret = NO_ERROR; |
| 301 | uint32_t ldocounter = 0; |
| 302 | uint32_t pm8x41_ldo_base = 0x13F00; |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 303 | |
Dhaval Patel | 7a34956 | 2013-08-08 20:43:52 -0700 | [diff] [blame] | 304 | while (ldocounter < TOTAL_LDO_DEFINED) { |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 305 | struct pm8x41_ldo ldo_entry = LDO((pm8x41_ldo_base + |
| 306 | 0x100 * ldo_entry_array[ldocounter].ldo_id), |
| 307 | ldo_entry_array[ldocounter].ldo_type); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 308 | |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 309 | dprintf(SPEW, "Setting %s\n", |
| 310 | ldo_entry_array[ldocounter].ldo_id); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 311 | |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 312 | /* Set voltage during power on */ |
Dhaval Patel | 815567c | 2013-07-31 11:13:25 -0700 | [diff] [blame] | 313 | if (enable) { |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 314 | pm8x41_ldo_set_voltage(&ldo_entry, |
| 315 | ldo_entry_array[ldocounter].ldo_voltage); |
Dhaval Patel | 815567c | 2013-07-31 11:13:25 -0700 | [diff] [blame] | 316 | |
| 317 | pm8x41_ldo_control(&ldo_entry, enable); |
| 318 | |
| 319 | } else if(!target_cont_splash_screen() && |
| 320 | ldo_entry_array[ldocounter].ldo_id != HFPLL_LDO_ID) { |
| 321 | pm8x41_ldo_control(&ldo_entry, enable); |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 322 | } |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 323 | ldocounter++; |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 324 | } |
| 325 | |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 326 | return ret; |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 327 | } |
| 328 | |
| 329 | void display_init(void) |
| 330 | { |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 331 | gcdb_display_init(MDP_REV_50, MIPI_FB_ADDR); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 332 | } |
| 333 | |
| 334 | void display_shutdown(void) |
| 335 | { |
Arpita Banerjee | c5f78df | 2013-05-24 15:43:40 -0700 | [diff] [blame] | 336 | gcdb_display_shutdown(); |
Ray Zhang | 743e503 | 2013-05-25 23:25:39 +0800 | [diff] [blame] | 337 | } |