Amol Jadi | cd43ea0 | 2011-02-15 20:56:04 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2011, Code Aurora Forum. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer in the |
| 10 | * documentation and/or other materials provided with the distribution. |
| 11 | * * Neither the name of Code Aurora nor |
| 12 | * the names of its contributors may be used to endorse or promote |
| 13 | * products derived from this software without specific prior written |
| 14 | * permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 18 | * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 19 | * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 20 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 21 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 22 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; |
| 23 | * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR |
| 25 | * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF |
| 26 | * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <debug.h> |
| 30 | #include <reg.h> |
| 31 | #include <platform/iomap.h> |
Amol Jadi | c52c8a3 | 2011-07-12 11:27:04 -0700 | [diff] [blame^] | 32 | #include <platform/clock.h> |
| 33 | #include <uart_dm.h> |
| 34 | #include <gsbi.h> |
Shashank Mittal | ed17773 | 2011-05-06 19:12:59 -0700 | [diff] [blame] | 35 | |
| 36 | |
Amol Jadi | cd43ea0 | 2011-02-15 20:56:04 -0800 | [diff] [blame] | 37 | /* Set rate and enable the clock */ |
Amol Jadi | c52c8a3 | 2011-07-12 11:27:04 -0700 | [diff] [blame^] | 38 | void clock_config(uint32_t ns, uint32_t md, uint32_t ns_addr, uint32_t md_addr) |
Amol Jadi | cd43ea0 | 2011-02-15 20:56:04 -0800 | [diff] [blame] | 39 | { |
Shashank Mittal | ed17773 | 2011-05-06 19:12:59 -0700 | [diff] [blame] | 40 | unsigned int val = 0; |
| 41 | |
| 42 | /* Activate the reset for the M/N Counter */ |
| 43 | val = 1 << 7; |
| 44 | writel(val, ns_addr); |
| 45 | |
| 46 | /* Write the MD value into the MD register */ |
| 47 | writel(md, md_addr); |
| 48 | |
| 49 | /* Write the ns value, and active reset for M/N Counter, again */ |
| 50 | val = 1 << 7; |
| 51 | val |= ns; |
| 52 | writel(val, ns_addr); |
| 53 | |
| 54 | /* De-activate the reset for M/N Counter */ |
| 55 | val = 1 << 7; |
| 56 | val = ~val; |
| 57 | val = val & readl(ns_addr); |
| 58 | writel(val, ns_addr); |
| 59 | |
| 60 | /* Enable the Clock Root */ |
| 61 | val = 1 << 11; |
| 62 | val = val | readl(ns_addr); |
| 63 | writel(val, ns_addr); |
| 64 | |
| 65 | /* Enable the Clock Branch */ |
| 66 | val = 1 << 9; |
| 67 | val = val | readl(ns_addr); |
| 68 | writel(val, ns_addr); |
| 69 | |
| 70 | /* Enable the M/N Counter */ |
| 71 | val = 1 << 8; |
| 72 | val = val | readl(ns_addr); |
| 73 | writel(val, ns_addr); |
Amol Jadi | cd43ea0 | 2011-02-15 20:56:04 -0800 | [diff] [blame] | 74 | } |
| 75 | |
Shashank Mittal | ed17773 | 2011-05-06 19:12:59 -0700 | [diff] [blame] | 76 | void pll8_enable(void) |
Amol Jadi | cd43ea0 | 2011-02-15 20:56:04 -0800 | [diff] [blame] | 77 | { |
Shashank Mittal | ed17773 | 2011-05-06 19:12:59 -0700 | [diff] [blame] | 78 | unsigned int curr_value = 0; |
| 79 | |
| 80 | /* Vote for PLL8 to be enabled */ |
| 81 | curr_value = readl(MSM_BOOT_PLL_ENABLE_SC0); |
| 82 | curr_value |= (1 << 8); |
| 83 | writel(curr_value, MSM_BOOT_PLL_ENABLE_SC0); |
| 84 | |
| 85 | /* Proceed only after PLL is enabled */ |
| 86 | while (!(readl(MSM_BOOT_PLL8_STATUS) & (1<<16))); |
Amol Jadi | cd43ea0 | 2011-02-15 20:56:04 -0800 | [diff] [blame] | 87 | } |
| 88 | |
| 89 | void hsusb_clock_init(void) |
| 90 | { |
Shashank Mittal | ed17773 | 2011-05-06 19:12:59 -0700 | [diff] [blame] | 91 | /* TODO: Enable pll8 here */ |
| 92 | /* Setup USB AHB clock */ |
| 93 | |
Shashank Mittal | ed17773 | 2011-05-06 19:12:59 -0700 | [diff] [blame] | 94 | /* Setup XCVR clock */ |
Amol Jadi | c52c8a3 | 2011-07-12 11:27:04 -0700 | [diff] [blame^] | 95 | clock_config(USB_XCVR_CLK_NS, |
| 96 | USB_XCVR_CLK_MD, |
Shashank Mittal | ed17773 | 2011-05-06 19:12:59 -0700 | [diff] [blame] | 97 | USB_HS1_XCVR_FS_CLK_NS, |
| 98 | USB_HS1_XCVR_FS_CLK_MD); |
Amol Jadi | cd43ea0 | 2011-02-15 20:56:04 -0800 | [diff] [blame] | 99 | } |
Amol Jadi | c52c8a3 | 2011-07-12 11:27:04 -0700 | [diff] [blame^] | 100 | |
| 101 | /* Configure UART clock - based on the gsbi id */ |
| 102 | void clock_config_uart_dm(uint8_t id) |
| 103 | { |
| 104 | /* Enable gsbi_uart_clk */ |
| 105 | clock_config(UART_DM_CLK_NS_115200, |
| 106 | UART_DM_CLK_MD_115200, |
| 107 | GSBIn_UART_APPS_NS(id), |
| 108 | GSBIn_UART_APPS_MD(id)); |
| 109 | |
| 110 | |
| 111 | /* Enable gsbi_pclk */ |
| 112 | writel(GSBI_HCLK_CTL_CLK_ENA << GSBI_HCLK_CTL_S, GSBIn_HCLK_CTL(id)); |
| 113 | } |
| 114 | |
| 115 | /* Configure i2c clock */ |
| 116 | void clock_config_i2c(uint8_t id, uint32_t freq) |
| 117 | { |
| 118 | uint32_t ns; |
| 119 | uint32_t md; |
| 120 | |
| 121 | switch (freq) |
| 122 | { |
| 123 | case 24000000: |
| 124 | ns = I2C_CLK_NS_24MHz; |
| 125 | md = I2C_CLK_MD_24MHz; |
| 126 | break; |
| 127 | default: |
| 128 | ASSERT(0); |
| 129 | } |
| 130 | |
| 131 | clock_config(ns, md, GSBIn_QUP_APPS_NS(id), GSBIn_QUP_APPS_MD(id)); |
| 132 | |
| 133 | /* Enable the GSBI HCLK */ |
| 134 | writel(GSBI_HCLK_CTL_CLK_ENA << GSBI_HCLK_CTL_S, GSBIn_HCLK_CTL(id)); |
| 135 | } |
| 136 | |