Channagoud Kadabi | a1ef809 | 2014-01-08 12:11:58 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
Deepa Dinamani | 32bfad0 | 2012-11-02 12:15:05 -0700 | [diff] [blame] | 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 15 | * |
Deepa Dinamani | 32bfad0 | 2012-11-02 12:15:05 -0700 | [diff] [blame] | 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 27 | */ |
| 28 | |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 29 | #include <err.h> |
| 30 | #include <assert.h> |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 31 | #include <debug.h> |
| 32 | #include <reg.h> |
Deepa Dinamani | 32bfad0 | 2012-11-02 12:15:05 -0700 | [diff] [blame] | 33 | #include <platform/timer.h> |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 34 | #include <platform/iomap.h> |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 35 | #include <mmc.h> |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 36 | #include <clock.h> |
| 37 | #include <platform/clock.h> |
Channagoud Kadabi | 634ac6d | 2012-12-12 18:13:56 -0800 | [diff] [blame] | 38 | #include <blsp_qup.h> |
Channagoud Kadabi | 57298ed | 2014-02-04 17:04:26 -0800 | [diff] [blame] | 39 | #include <pm8x41.h> |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 40 | |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 41 | void hsusb_clock_init(void) |
| 42 | { |
| 43 | int ret; |
Deepa Dinamani | 0687ecd | 2012-08-10 16:00:26 -0700 | [diff] [blame] | 44 | struct clk *iclk, *cclk; |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 45 | |
| 46 | ret = clk_get_set_enable("usb_iface_clk", 0, 1); |
| 47 | if(ret) |
| 48 | { |
| 49 | dprintf(CRITICAL, "failed to set usb_iface_clk ret = %d\n", ret); |
| 50 | ASSERT(0); |
| 51 | } |
| 52 | |
| 53 | ret = clk_get_set_enable("usb_core_clk", 75000000, 1); |
| 54 | if(ret) |
| 55 | { |
| 56 | dprintf(CRITICAL, "failed to set usb_core_clk ret = %d\n", ret); |
| 57 | ASSERT(0); |
| 58 | } |
Deepa Dinamani | 0687ecd | 2012-08-10 16:00:26 -0700 | [diff] [blame] | 59 | |
| 60 | mdelay(20); |
| 61 | |
| 62 | iclk = clk_get("usb_iface_clk"); |
| 63 | cclk = clk_get("usb_core_clk"); |
| 64 | |
Deepa Dinamani | 0687ecd | 2012-08-10 16:00:26 -0700 | [diff] [blame] | 65 | clk_disable(iclk); |
| 66 | clk_disable(cclk); |
| 67 | |
| 68 | mdelay(20); |
| 69 | |
| 70 | /* Start the block reset for usb */ |
| 71 | writel(1, USB_HS_BCR); |
| 72 | |
| 73 | mdelay(20); |
| 74 | |
| 75 | /* Take usb block out of reset */ |
Deepa Dinamani | 32bfad0 | 2012-11-02 12:15:05 -0700 | [diff] [blame] | 76 | writel(0, USB_HS_BCR); |
Deepa Dinamani | 0687ecd | 2012-08-10 16:00:26 -0700 | [diff] [blame] | 77 | |
| 78 | mdelay(20); |
| 79 | |
| 80 | ret = clk_enable(iclk); |
Deepa Dinamani | 32bfad0 | 2012-11-02 12:15:05 -0700 | [diff] [blame] | 81 | |
Deepa Dinamani | 0687ecd | 2012-08-10 16:00:26 -0700 | [diff] [blame] | 82 | if(ret) |
| 83 | { |
| 84 | dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret); |
| 85 | ASSERT(0); |
| 86 | } |
| 87 | |
| 88 | ret = clk_enable(cclk); |
| 89 | |
| 90 | if(ret) |
| 91 | { |
| 92 | dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret); |
| 93 | ASSERT(0); |
| 94 | } |
| 95 | |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 96 | } |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 97 | |
| 98 | void clock_init_mmc(uint32_t interface) |
| 99 | { |
Deepa Dinamani | b10c0e4 | 2012-08-10 14:36:24 -0700 | [diff] [blame] | 100 | char clk_name[64]; |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 101 | int ret; |
| 102 | |
Deepa Dinamani | b10c0e4 | 2012-08-10 14:36:24 -0700 | [diff] [blame] | 103 | snprintf(clk_name, 64, "sdc%u_iface_clk", interface); |
| 104 | |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 105 | /* enable interface clock */ |
Deepa Dinamani | b10c0e4 | 2012-08-10 14:36:24 -0700 | [diff] [blame] | 106 | ret = clk_get_set_enable(clk_name, 0, 1); |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 107 | if(ret) |
| 108 | { |
| 109 | dprintf(CRITICAL, "failed to set sdc1_iface_clk ret = %d\n", ret); |
| 110 | ASSERT(0); |
| 111 | } |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 112 | } |
| 113 | |
| 114 | /* Configure MMC clock */ |
| 115 | void clock_config_mmc(uint32_t interface, uint32_t freq) |
| 116 | { |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 117 | int ret; |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 118 | uint32_t reg; |
Deepa Dinamani | b10c0e4 | 2012-08-10 14:36:24 -0700 | [diff] [blame] | 119 | char clk_name[64]; |
| 120 | |
| 121 | snprintf(clk_name, 64, "sdc%u_core_clk", interface); |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 122 | |
Channagoud Kadabi | 9651841 | 2013-03-14 16:38:41 -0700 | [diff] [blame] | 123 | /* Disalbe MCI_CLK before changing the sdcc clock */ |
Channagoud Kadabi | 4fb29e9 | 2013-04-05 11:32:11 -0700 | [diff] [blame] | 124 | #ifndef MMC_SDHCI_SUPPORT |
Channagoud Kadabi | 9651841 | 2013-03-14 16:38:41 -0700 | [diff] [blame] | 125 | mmc_boot_mci_clk_disable(); |
Channagoud Kadabi | 4fb29e9 | 2013-04-05 11:32:11 -0700 | [diff] [blame] | 126 | #endif |
Channagoud Kadabi | 9651841 | 2013-03-14 16:38:41 -0700 | [diff] [blame] | 127 | |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 128 | if(freq == MMC_CLK_400KHZ) |
| 129 | { |
Deepa Dinamani | b10c0e4 | 2012-08-10 14:36:24 -0700 | [diff] [blame] | 130 | ret = clk_get_set_enable(clk_name, 400000, 1); |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 131 | } |
Channagoud Kadabi | bdac709 | 2013-08-20 15:28:07 -0700 | [diff] [blame] | 132 | else if(freq == MMC_CLK_25MHZ) |
| 133 | { |
| 134 | ret = clk_get_set_enable(clk_name, 25000000, 1); |
| 135 | } |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 136 | else if(freq == MMC_CLK_50MHZ) |
| 137 | { |
Neeti Desai | ddc771b | 2012-08-28 18:17:04 -0700 | [diff] [blame] | 138 | ret = clk_get_set_enable(clk_name, 50000000, 1); |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 139 | } |
Channagoud Kadabi | 8495f88 | 2013-04-02 11:20:28 -0700 | [diff] [blame] | 140 | else if(freq == MMC_CLK_96MHZ) |
| 141 | { |
| 142 | ret = clk_get_set_enable(clk_name, 100000000, 1); |
| 143 | } |
Channagoud Kadabi | bdac709 | 2013-08-20 15:28:07 -0700 | [diff] [blame] | 144 | else if(freq == MMC_CLK_192MHZ) |
| 145 | { |
| 146 | ret = clk_get_set_enable(clk_name, 192000000, 1); |
| 147 | } |
Channagoud Kadabi | 4fb29e9 | 2013-04-05 11:32:11 -0700 | [diff] [blame] | 148 | else if(freq == MMC_CLK_200MHZ) |
| 149 | { |
| 150 | ret = clk_get_set_enable(clk_name, 200000000, 1); |
| 151 | } |
Channagoud Kadabi | bdac709 | 2013-08-20 15:28:07 -0700 | [diff] [blame] | 152 | else if(freq == MMC_CLK_400MHZ) |
| 153 | { |
| 154 | ret = clk_get_set_enable(clk_name, 384000000, 1); |
| 155 | } |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 156 | else |
| 157 | { |
Channagoud Kadabi | cb6cf69 | 2013-08-02 11:53:13 -0700 | [diff] [blame] | 158 | dprintf(CRITICAL, "sdc frequency (%u) is not supported\n", freq); |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 159 | ASSERT(0); |
| 160 | } |
| 161 | |
| 162 | |
| 163 | if(ret) |
| 164 | { |
Channagoud Kadabi | cb6cf69 | 2013-08-02 11:53:13 -0700 | [diff] [blame] | 165 | dprintf(CRITICAL, "failed to set sdc%u_core_clk ret = %d\n", interface, ret); |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 166 | ASSERT(0); |
| 167 | } |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 168 | |
Channagoud Kadabi | 9651841 | 2013-03-14 16:38:41 -0700 | [diff] [blame] | 169 | /* Enalbe MCI clock */ |
Channagoud Kadabi | 4fb29e9 | 2013-04-05 11:32:11 -0700 | [diff] [blame] | 170 | #ifndef MMC_SDHCI_SUPPORT |
Channagoud Kadabi | 9651841 | 2013-03-14 16:38:41 -0700 | [diff] [blame] | 171 | mmc_boot_mci_clk_enable(); |
Channagoud Kadabi | 4fb29e9 | 2013-04-05 11:32:11 -0700 | [diff] [blame] | 172 | #endif |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 173 | } |
| 174 | |
Channagoud Kadabi | bdac709 | 2013-08-20 15:28:07 -0700 | [diff] [blame] | 175 | /* Configure clocks needed for CDCLP533 circuit */ |
| 176 | void clock_config_cdc(uint32_t interface) |
| 177 | { |
| 178 | int ret = 0; |
| 179 | char clk_name[64]; |
| 180 | |
Channagoud Kadabi | 0316b14 | 2014-04-01 14:43:03 -0700 | [diff] [blame] | 181 | /* CDC clocks are not supported for 8974 v1 & v2 |
| 182 | * only pro msm's support it |
| 183 | */ |
| 184 | if (platform_is_8974()) |
| 185 | return; |
| 186 | |
Channagoud Kadabi | bdac709 | 2013-08-20 15:28:07 -0700 | [diff] [blame] | 187 | snprintf(clk_name, sizeof(clk_name), "gcc_sdcc%u_cdccal_sleep_clk", interface); |
| 188 | ret = clk_get_set_enable(clk_name, 0 , 1); |
| 189 | if (ret) |
| 190 | { |
| 191 | dprintf(CRITICAL, "Failed to enable clock: %s\n", clk_name); |
| 192 | ASSERT(0); |
| 193 | } |
| 194 | |
| 195 | snprintf(clk_name, sizeof(clk_name), "gcc_sdcc%u_cdccal_ff_clk", interface); |
| 196 | ret = clk_get_set_enable(clk_name, 0 , 1); |
| 197 | if (ret) |
| 198 | { |
| 199 | dprintf(CRITICAL, "Failed to enable clock: %s\n", clk_name); |
| 200 | ASSERT(0); |
| 201 | } |
| 202 | } |
| 203 | |
Deepa Dinamani | 26e9326 | 2012-05-21 17:35:14 -0700 | [diff] [blame] | 204 | /* Configure UART clock based on the UART block id*/ |
| 205 | void clock_config_uart_dm(uint8_t id) |
| 206 | { |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 207 | int ret; |
Deepa Dinamani | 26e9326 | 2012-05-21 17:35:14 -0700 | [diff] [blame] | 208 | |
Neeti Desai | ac01127 | 2012-08-29 18:24:54 -0700 | [diff] [blame] | 209 | |
| 210 | ret = clk_get_set_enable("uart2_iface_clk", 0, 1); |
| 211 | if(ret) |
| 212 | { |
| 213 | dprintf(CRITICAL, "failed to set uart2_iface_clk ret = %d\n", ret); |
| 214 | ASSERT(0); |
| 215 | } |
| 216 | |
| 217 | ret = clk_get_set_enable("uart2_core_clk", 7372800, 1); |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 218 | if(ret) |
| 219 | { |
| 220 | dprintf(CRITICAL, "failed to set uart1_core_clk ret = %d\n", ret); |
| 221 | ASSERT(0); |
| 222 | } |
Deepa Dinamani | 26e9326 | 2012-05-21 17:35:14 -0700 | [diff] [blame] | 223 | } |
Deepa Dinamani | 32bfad0 | 2012-11-02 12:15:05 -0700 | [diff] [blame] | 224 | |
| 225 | /* Function to asynchronously reset CE. |
| 226 | * Function assumes that all the CE clocks are off. |
| 227 | */ |
| 228 | static void ce_async_reset(uint8_t instance) |
| 229 | { |
| 230 | if (instance == 1) |
| 231 | { |
Channagoud Kadabi | a1ef809 | 2014-01-08 12:11:58 -0800 | [diff] [blame] | 232 | /* TODO: Add support for instance 1. */ |
| 233 | dprintf(CRITICAL, "CE instance not supported instance = %d", instance); |
| 234 | ASSERT(0); |
Deepa Dinamani | 32bfad0 | 2012-11-02 12:15:05 -0700 | [diff] [blame] | 235 | } |
| 236 | else if (instance == 2) |
| 237 | { |
| 238 | /* Start the block reset for CE */ |
| 239 | writel(1, GCC_CE2_BCR); |
| 240 | |
| 241 | udelay(2); |
| 242 | |
| 243 | /* Take CE block out of reset */ |
| 244 | writel(0, GCC_CE2_BCR); |
| 245 | |
| 246 | udelay(2); |
| 247 | } |
| 248 | else |
| 249 | { |
| 250 | dprintf(CRITICAL, "CE instance not supported instance = %d", instance); |
| 251 | ASSERT(0); |
| 252 | } |
| 253 | } |
| 254 | |
sundarajan srinivasan | 6aaa50c | 2013-02-27 14:18:57 -0800 | [diff] [blame] | 255 | void clock_ce_enable(uint8_t instance) |
Deepa Dinamani | 32bfad0 | 2012-11-02 12:15:05 -0700 | [diff] [blame] | 256 | { |
| 257 | int ret; |
| 258 | char clk_name[64]; |
| 259 | |
| 260 | snprintf(clk_name, 64, "ce%u_src_clk", instance); |
| 261 | ret = clk_get_set_enable(clk_name, 100000000, 1); |
| 262 | if(ret) |
| 263 | { |
| 264 | dprintf(CRITICAL, "failed to set ce_src_clk ret = %d\n", ret); |
| 265 | ASSERT(0); |
| 266 | } |
| 267 | |
| 268 | snprintf(clk_name, 64, "ce%u_core_clk", instance); |
| 269 | ret = clk_get_set_enable(clk_name, 0, 1); |
| 270 | if(ret) |
| 271 | { |
| 272 | dprintf(CRITICAL, "failed to set ce_core_clk ret = %d\n", ret); |
| 273 | ASSERT(0); |
| 274 | } |
| 275 | |
| 276 | snprintf(clk_name, 64, "ce%u_ahb_clk", instance); |
| 277 | ret = clk_get_set_enable(clk_name, 0, 1); |
| 278 | if(ret) |
| 279 | { |
| 280 | dprintf(CRITICAL, "failed to set ce_ahb_clk ret = %d\n", ret); |
| 281 | ASSERT(0); |
| 282 | } |
| 283 | |
| 284 | snprintf(clk_name, 64, "ce%u_axi_clk", instance); |
| 285 | ret = clk_get_set_enable(clk_name, 0, 1); |
| 286 | if(ret) |
| 287 | { |
| 288 | dprintf(CRITICAL, "failed to set ce_axi_clk ret = %d\n", ret); |
| 289 | ASSERT(0); |
| 290 | } |
| 291 | |
| 292 | /* Wait for 48 * #pipes cycles. |
| 293 | * This is necessary as immediately after an access control reset (boot up) |
| 294 | * or a debug re-enable, the Crypto core sequentially clears its internal |
| 295 | * pipe key storage memory. If pipe key initialization writes are attempted |
| 296 | * during this time, they may be overwritten by the internal clearing logic. |
| 297 | */ |
| 298 | udelay(1); |
| 299 | } |
| 300 | |
sundarajan srinivasan | 6aaa50c | 2013-02-27 14:18:57 -0800 | [diff] [blame] | 301 | void clock_ce_disable(uint8_t instance) |
Deepa Dinamani | 32bfad0 | 2012-11-02 12:15:05 -0700 | [diff] [blame] | 302 | { |
| 303 | struct clk *ahb_clk; |
| 304 | struct clk *cclk; |
| 305 | struct clk *axi_clk; |
| 306 | struct clk *src_clk; |
| 307 | char clk_name[64]; |
| 308 | |
| 309 | snprintf(clk_name, 64, "ce%u_src_clk", instance); |
| 310 | src_clk = clk_get(clk_name); |
| 311 | |
| 312 | snprintf(clk_name, 64, "ce%u_ahb_clk", instance); |
| 313 | ahb_clk = clk_get(clk_name); |
| 314 | |
| 315 | snprintf(clk_name, 64, "ce%u_axi_clk", instance); |
| 316 | axi_clk = clk_get(clk_name); |
| 317 | |
| 318 | snprintf(clk_name, 64, "ce%u_core_clk", instance); |
| 319 | cclk = clk_get(clk_name); |
| 320 | |
| 321 | clk_disable(ahb_clk); |
| 322 | clk_disable(axi_clk); |
| 323 | clk_disable(cclk); |
| 324 | clk_disable(src_clk); |
| 325 | |
| 326 | /* Some delay for the clocks to stabalize. */ |
| 327 | udelay(1); |
| 328 | } |
| 329 | |
| 330 | void clock_config_ce(uint8_t instance) |
| 331 | { |
| 332 | /* Need to enable the clock before disabling since the clk_disable() |
| 333 | * has a check to default to nop when the clk_enable() is not called |
| 334 | * on that particular clock. |
| 335 | */ |
| 336 | clock_ce_enable(instance); |
| 337 | |
| 338 | clock_ce_disable(instance); |
| 339 | |
| 340 | ce_async_reset(instance); |
| 341 | |
| 342 | clock_ce_enable(instance); |
sundarajan srinivasan | 6aaa50c | 2013-02-27 14:18:57 -0800 | [diff] [blame] | 343 | |
Deepa Dinamani | 32bfad0 | 2012-11-02 12:15:05 -0700 | [diff] [blame] | 344 | } |
Channagoud Kadabi | 634ac6d | 2012-12-12 18:13:56 -0800 | [diff] [blame] | 345 | |
| 346 | void clock_config_blsp_i2c(uint8_t blsp_id, uint8_t qup_id) |
| 347 | { |
| 348 | uint8_t ret = 0; |
| 349 | char clk_name[64]; |
| 350 | |
| 351 | struct clk *qup_clk; |
| 352 | |
| 353 | snprintf(clk_name, 64, "blsp%u_ahb_clk", blsp_id); |
| 354 | |
| 355 | ret = clk_get_set_enable(clk_name, 0 , 1); |
| 356 | |
| 357 | if (ret) { |
| 358 | dprintf(CRITICAL, "Failed to enable %s clock\n", clk_name); |
| 359 | return; |
| 360 | } |
| 361 | |
| 362 | snprintf(clk_name, 64, "blsp%u_qup%u_i2c_apps_clk", blsp_id, |
| 363 | (qup_id + 1)); |
| 364 | |
| 365 | qup_clk = clk_get(clk_name); |
| 366 | |
| 367 | if (!qup_clk) { |
| 368 | dprintf(CRITICAL, "Failed to get %s\n", clk_name); |
| 369 | return; |
| 370 | } |
| 371 | |
| 372 | ret = clk_enable(qup_clk); |
| 373 | |
| 374 | if (ret) { |
| 375 | dprintf(CRITICAL, "Failed to enable %s\n", clk_name); |
| 376 | return; |
| 377 | } |
| 378 | } |
Siddhartha Agrawal | acdaf5b | 2013-01-22 18:14:53 -0800 | [diff] [blame] | 379 | |
| 380 | void mdp_gdsc_ctrl(uint8_t enable) |
| 381 | { |
| 382 | uint32_t reg = 0; |
| 383 | reg = readl(MDP_GDSCR); |
| 384 | if (enable) { |
Pradeep Jilagam | 570d1d0 | 2013-07-10 10:30:07 -0700 | [diff] [blame] | 385 | if (!(reg & GDSC_POWER_ON_BIT)) { |
Siddhartha Agrawal | 267fc3f | 2013-03-25 17:03:50 -0700 | [diff] [blame] | 386 | reg &= ~(BIT(0) | GDSC_EN_FEW_WAIT_MASK); |
| 387 | reg |= GDSC_EN_FEW_WAIT_256_MASK; |
| 388 | writel(reg, MDP_GDSCR); |
Pradeep Jilagam | 570d1d0 | 2013-07-10 10:30:07 -0700 | [diff] [blame] | 389 | while(!(readl(MDP_GDSCR) & (GDSC_POWER_ON_BIT))); |
| 390 | } else { |
| 391 | dprintf(INFO, "MDP GDSC already enabled\n"); |
Siddhartha Agrawal | 267fc3f | 2013-03-25 17:03:50 -0700 | [diff] [blame] | 392 | } |
Siddhartha Agrawal | 9d6e28f | 2013-04-21 16:00:07 -0700 | [diff] [blame] | 393 | } else { |
Pradeep Jilagam | 570d1d0 | 2013-07-10 10:30:07 -0700 | [diff] [blame] | 394 | reg |= BIT(0); |
Siddhartha Agrawal | 9d6e28f | 2013-04-21 16:00:07 -0700 | [diff] [blame] | 395 | writel(reg, MDP_GDSCR); |
Pradeep Jilagam | 570d1d0 | 2013-07-10 10:30:07 -0700 | [diff] [blame] | 396 | while(readl(MDP_GDSCR) & (GDSC_POWER_ON_BIT)); |
Siddhartha Agrawal | 9d6e28f | 2013-04-21 16:00:07 -0700 | [diff] [blame] | 397 | } |
Siddhartha Agrawal | acdaf5b | 2013-01-22 18:14:53 -0800 | [diff] [blame] | 398 | } |
| 399 | |
| 400 | /* Configure MDP clock */ |
| 401 | void mdp_clock_init(void) |
| 402 | { |
| 403 | int ret; |
| 404 | |
Siddhartha Agrawal | 6bf6c15 | 2013-05-29 20:47:20 -0700 | [diff] [blame] | 405 | /* Set MDP clock to 240MHz */ |
Siddhartha Agrawal | acdaf5b | 2013-01-22 18:14:53 -0800 | [diff] [blame] | 406 | ret = clk_get_set_enable("mdp_ahb_clk", 0, 1); |
| 407 | if(ret) |
| 408 | { |
| 409 | dprintf(CRITICAL, "failed to set mdp_ahb_clk ret = %d\n", ret); |
| 410 | ASSERT(0); |
| 411 | } |
| 412 | |
Siddhartha Agrawal | 6bf6c15 | 2013-05-29 20:47:20 -0700 | [diff] [blame] | 413 | ret = clk_get_set_enable("mdss_mdp_clk_src", 240000000, 1); |
Siddhartha Agrawal | acdaf5b | 2013-01-22 18:14:53 -0800 | [diff] [blame] | 414 | if(ret) |
| 415 | { |
| 416 | dprintf(CRITICAL, "failed to set mdp_clk_src ret = %d\n", ret); |
| 417 | ASSERT(0); |
| 418 | } |
| 419 | |
Siddhartha Agrawal | 9d6e28f | 2013-04-21 16:00:07 -0700 | [diff] [blame] | 420 | ret = clk_get_set_enable("mdss_vsync_clk", 0, 1); |
| 421 | if(ret) |
| 422 | { |
| 423 | dprintf(CRITICAL, "failed to set mdss vsync clk ret = %d\n", ret); |
| 424 | ASSERT(0); |
| 425 | } |
| 426 | |
Siddhartha Agrawal | acdaf5b | 2013-01-22 18:14:53 -0800 | [diff] [blame] | 427 | ret = clk_get_set_enable("mdss_mdp_clk", 0, 1); |
| 428 | if(ret) |
| 429 | { |
| 430 | dprintf(CRITICAL, "failed to set mdp_clk ret = %d\n", ret); |
| 431 | ASSERT(0); |
| 432 | } |
| 433 | |
| 434 | ret = clk_get_set_enable("mdss_mdp_lut_clk", 0, 1); |
| 435 | if(ret) |
| 436 | { |
| 437 | dprintf(CRITICAL, "failed to set lut_mdp clk ret = %d\n", ret); |
| 438 | ASSERT(0); |
| 439 | } |
| 440 | } |
| 441 | |
Siddhartha Agrawal | c88737b | 2013-05-29 20:41:35 -0700 | [diff] [blame] | 442 | void mdp_clock_disable(uint32_t dual_dsi) |
Siddhartha Agrawal | 9d6e28f | 2013-04-21 16:00:07 -0700 | [diff] [blame] | 443 | { |
| 444 | writel(0x0, DSI_BYTE0_CBCR); |
| 445 | writel(0x0, DSI_PIXEL0_CBCR); |
Siddhartha Agrawal | c88737b | 2013-05-29 20:41:35 -0700 | [diff] [blame] | 446 | if (dual_dsi) { |
| 447 | writel(0x0, DSI_BYTE1_CBCR); |
| 448 | writel(0x0, DSI_PIXEL1_CBCR); |
| 449 | } |
Siddhartha Agrawal | 9d6e28f | 2013-04-21 16:00:07 -0700 | [diff] [blame] | 450 | clk_disable(clk_get("mdss_vsync_clk")); |
| 451 | clk_disable(clk_get("mdss_mdp_clk")); |
| 452 | clk_disable(clk_get("mdss_mdp_lut_clk")); |
| 453 | clk_disable(clk_get("mdss_mdp_clk_src")); |
| 454 | clk_disable(clk_get("mdp_ahb_clk")); |
| 455 | |
| 456 | } |
| 457 | |
Siddhartha Agrawal | acdaf5b | 2013-01-22 18:14:53 -0800 | [diff] [blame] | 458 | /* Initialize all clocks needed by Display */ |
Siddhartha Agrawal | c88737b | 2013-05-29 20:41:35 -0700 | [diff] [blame] | 459 | void mmss_clock_init(uint32_t dsi_pixel0_cfg_rcgr, uint32_t dual_dsi) |
Siddhartha Agrawal | acdaf5b | 2013-01-22 18:14:53 -0800 | [diff] [blame] | 460 | { |
| 461 | int ret; |
| 462 | |
| 463 | /* Configure Byte clock */ |
| 464 | writel(0x100, DSI_BYTE0_CFG_RCGR); |
| 465 | writel(0x1, DSI_BYTE0_CMD_RCGR); |
| 466 | writel(0x1, DSI_BYTE0_CBCR); |
| 467 | |
| 468 | /* Configure ESC clock */ |
| 469 | ret = clk_get_set_enable("mdss_esc0_clk", 0, 1); |
| 470 | if(ret) |
| 471 | { |
| 472 | dprintf(CRITICAL, "failed to set esc0_clk ret = %d\n", ret); |
| 473 | ASSERT(0); |
| 474 | } |
| 475 | |
| 476 | /* Configure MMSSNOC AXI clock */ |
| 477 | ret = clk_get_set_enable("mmss_mmssnoc_axi_clk", 100000000, 1); |
| 478 | if(ret) |
| 479 | { |
| 480 | dprintf(CRITICAL, "failed to set mmssnoc_axi_clk ret = %d\n", ret); |
| 481 | ASSERT(0); |
| 482 | } |
| 483 | |
| 484 | /* Configure MMSSNOC AXI clock */ |
| 485 | ret = clk_get_set_enable("mmss_s0_axi_clk", 100000000, 1); |
| 486 | if(ret) |
| 487 | { |
| 488 | dprintf(CRITICAL, "failed to set mmss_s0_axi_clk ret = %d\n", ret); |
| 489 | ASSERT(0); |
| 490 | } |
| 491 | |
| 492 | /* Configure AXI clock */ |
| 493 | ret = clk_get_set_enable("mdss_axi_clk", 100000000, 1); |
| 494 | if(ret) |
| 495 | { |
| 496 | dprintf(CRITICAL, "failed to set mdss_axi_clk ret = %d\n", ret); |
| 497 | ASSERT(0); |
| 498 | } |
| 499 | |
| 500 | /* Configure Pixel clock */ |
Asaf Penso | fd099cf | 2013-05-20 11:12:38 +0300 | [diff] [blame] | 501 | writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL0_CFG_RCGR); |
Siddhartha Agrawal | acdaf5b | 2013-01-22 18:14:53 -0800 | [diff] [blame] | 502 | writel(0x1, DSI_PIXEL0_CMD_RCGR); |
| 503 | writel(0x1, DSI_PIXEL0_CBCR); |
Siddhartha Agrawal | c88737b | 2013-05-29 20:41:35 -0700 | [diff] [blame] | 504 | |
| 505 | if (dual_dsi) { |
| 506 | /* Configure Byte 1 clock */ |
| 507 | writel(0x100, DSI_BYTE1_CFG_RCGR); |
| 508 | writel(0x1, DSI_BYTE1_CMD_RCGR); |
| 509 | writel(0x1, DSI_BYTE1_CBCR); |
| 510 | |
| 511 | /* Configure ESC clock */ |
| 512 | ret = clk_get_set_enable("mdss_esc1_clk", 0, 1); |
| 513 | if(ret) |
| 514 | { |
| 515 | dprintf(CRITICAL, "failed to set esc1_clk ret = %d\n", ret); |
| 516 | ASSERT(0); |
| 517 | } |
| 518 | |
| 519 | /* Configure Pixel clock */ |
| 520 | writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL1_CFG_RCGR); |
| 521 | writel(0x1, DSI_PIXEL1_CMD_RCGR); |
| 522 | writel(0x1, DSI_PIXEL1_CBCR); |
| 523 | } |
Siddhartha Agrawal | acdaf5b | 2013-01-22 18:14:53 -0800 | [diff] [blame] | 524 | } |
Siddhartha Agrawal | 9d6e28f | 2013-04-21 16:00:07 -0700 | [diff] [blame] | 525 | |
Arpita Banerjee | 469bf9b | 2013-05-30 15:03:23 -0700 | [diff] [blame] | 526 | void mmss_clock_auto_pll_init(uint32_t dsi_pixel0_cfg_rcgr, uint32_t dual_dsi, |
| 527 | uint8_t pclk0_m, uint8_t pclk0_n, uint8_t pclk0_d) |
| 528 | { |
| 529 | int ret; |
| 530 | |
| 531 | /* Configure Byte clock -autopll- This will not change because |
| 532 | byte clock does not need any divider*/ |
| 533 | writel(0x100, DSI_BYTE0_CFG_RCGR); |
| 534 | writel(0x1, DSI_BYTE0_CMD_RCGR); |
| 535 | writel(0x1, DSI_BYTE0_CBCR); |
| 536 | |
| 537 | /* Configure ESC clock */ |
| 538 | ret = clk_get_set_enable("mdss_esc0_clk", 0, 1); |
| 539 | if(ret) |
| 540 | { |
| 541 | dprintf(CRITICAL, "failed to set esc0_clk ret = %d\n", ret); |
| 542 | ASSERT(0); |
| 543 | } |
| 544 | |
| 545 | /* Configure MMSSNOC AXI clock */ |
| 546 | ret = clk_get_set_enable("mmss_mmssnoc_axi_clk", 100000000, 1); |
| 547 | if(ret) |
| 548 | { |
| 549 | dprintf(CRITICAL, "failed to set mmssnoc_axi_clk ret = %d\n", ret); |
| 550 | ASSERT(0); |
| 551 | } |
| 552 | |
| 553 | /* Configure S0 AXI clock */ |
| 554 | ret = clk_get_set_enable("mmss_s0_axi_clk", 100000000, 1); |
| 555 | if(ret) |
| 556 | { |
| 557 | dprintf(CRITICAL, "failed to set mmss_s0_axi_clk ret = %d\n", ret); |
| 558 | ASSERT(0); |
| 559 | } |
| 560 | |
| 561 | /* Configure AXI clock */ |
| 562 | ret = clk_get_set_enable("mdss_axi_clk", 100000000, 1); |
| 563 | if(ret) |
| 564 | { |
| 565 | dprintf(CRITICAL, "failed to set mdss_axi_clk ret = %d\n", ret); |
| 566 | ASSERT(0); |
| 567 | } |
| 568 | |
| 569 | /* Configure Pixel clock */ |
| 570 | writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL0_CFG_RCGR); |
| 571 | writel(0x1, DSI_PIXEL0_CMD_RCGR); |
| 572 | writel(0x1, DSI_PIXEL0_CBCR); |
| 573 | |
| 574 | writel(pclk0_m, DSI_PIXEL0_M); |
| 575 | writel(pclk0_n, DSI_PIXEL0_N); |
| 576 | writel(pclk0_d, DSI_PIXEL0_D); |
| 577 | |
| 578 | if (dual_dsi) { |
| 579 | /* Configure Byte 1 clock */ |
| 580 | writel(0x100, DSI_BYTE1_CFG_RCGR); |
| 581 | writel(0x1, DSI_BYTE1_CMD_RCGR); |
| 582 | writel(0x1, DSI_BYTE1_CBCR); |
| 583 | |
| 584 | /* Configure ESC clock */ |
| 585 | ret = clk_get_set_enable("mdss_esc1_clk", 0, 1); |
| 586 | if(ret) |
| 587 | { |
| 588 | dprintf(CRITICAL, "failed to set esc1_clk ret = %d\n", ret); |
| 589 | ASSERT(0); |
| 590 | } |
| 591 | |
| 592 | /* Configure Pixel clock */ |
| 593 | writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL1_CFG_RCGR); |
| 594 | writel(0x1, DSI_PIXEL1_CMD_RCGR); |
| 595 | writel(0x1, DSI_PIXEL1_CBCR); |
| 596 | |
| 597 | writel(pclk0_m, DSI_PIXEL0_M); |
| 598 | writel(pclk0_n, DSI_PIXEL0_N); |
| 599 | writel(pclk0_d, DSI_PIXEL0_D); |
| 600 | } |
| 601 | } |
| 602 | |
Siddhartha Agrawal | c88737b | 2013-05-29 20:41:35 -0700 | [diff] [blame] | 603 | void mmss_clock_disable(uint32_t dual_dsi) |
Siddhartha Agrawal | 9d6e28f | 2013-04-21 16:00:07 -0700 | [diff] [blame] | 604 | { |
| 605 | |
| 606 | /* Disable ESC clock */ |
| 607 | clk_disable(clk_get("mdss_esc0_clk")); |
| 608 | |
Siddhartha Agrawal | c88737b | 2013-05-29 20:41:35 -0700 | [diff] [blame] | 609 | if (dual_dsi) { |
| 610 | /* Disable ESC clock */ |
| 611 | clk_disable(clk_get("mdss_esc1_clk")); |
| 612 | } |
| 613 | |
Siddhartha Agrawal | 9d6e28f | 2013-04-21 16:00:07 -0700 | [diff] [blame] | 614 | /* Disable MDSS AXI clock */ |
| 615 | clk_disable(clk_get("mdss_axi_clk")); |
| 616 | |
| 617 | /* Disable MMSSNOC S0AXI clock */ |
| 618 | clk_disable(clk_get("mmss_s0_axi_clk")); |
| 619 | |
| 620 | /* Disable MMSSNOC AXI clock */ |
| 621 | clk_disable(clk_get("mmss_mmssnoc_axi_clk")); |
| 622 | |
| 623 | } |
Amol Jadi | 38450af | 2013-07-23 15:01:48 -0700 | [diff] [blame] | 624 | |
| 625 | /* enables usb30 interface and master clocks */ |
| 626 | void clock_usb30_init(void) |
| 627 | { |
| 628 | int ret; |
| 629 | |
| 630 | /* interface clock */ |
| 631 | ret = clk_get_set_enable("usb30_iface_clk", 0, 1); |
| 632 | if(ret) |
| 633 | { |
| 634 | dprintf(CRITICAL, "failed to set usb30_iface_clk. ret = %d\n", ret); |
| 635 | ASSERT(0); |
| 636 | } |
| 637 | |
| 638 | /* master clock */ |
| 639 | ret = clk_get_set_enable("usb30_master_clk", 125000000, 1); |
| 640 | if(ret) |
| 641 | { |
| 642 | dprintf(CRITICAL, "failed to set usb30_master_clk. ret = %d\n", ret); |
| 643 | ASSERT(0); |
| 644 | } |
Channagoud Kadabi | 57298ed | 2014-02-04 17:04:26 -0800 | [diff] [blame] | 645 | |
| 646 | /* Enable pmic diff clock */ |
| 647 | pm8x41_diff_clock_ctrl(1); |
Amol Jadi | 38450af | 2013-07-23 15:01:48 -0700 | [diff] [blame] | 648 | } |
Asaf Penso | e149921 | 2013-08-04 18:09:53 +0300 | [diff] [blame] | 649 | |
| 650 | void edp_clk_enable(void) |
| 651 | { |
| 652 | int ret; |
| 653 | |
Kuogee Hsieh | e99937a | 2013-06-06 14:21:48 -0700 | [diff] [blame] | 654 | /* Configure MMSSNOC AXI clock */ |
| 655 | ret = clk_get_set_enable("mmss_mmssnoc_axi_clk", 100000000, 1); |
| 656 | if(ret) |
| 657 | { |
| 658 | dprintf(CRITICAL, "failed to set mmssnoc_axi_clk ret = %d\n", ret); |
| 659 | ASSERT(0); |
| 660 | } |
| 661 | |
| 662 | /* Configure MMSSNOC AXI clock */ |
| 663 | ret = clk_get_set_enable("mmss_s0_axi_clk", 100000000, 1); |
| 664 | if(ret) |
| 665 | { |
| 666 | dprintf(CRITICAL, "failed to set mmss_s0_axi_clk ret = %d\n", ret); |
| 667 | ASSERT(0); |
| 668 | } |
| 669 | |
| 670 | /* Configure AXI clock */ |
| 671 | ret = clk_get_set_enable("mdss_axi_clk", 100000000, 1); |
| 672 | if(ret) |
| 673 | { |
| 674 | dprintf(CRITICAL, "failed to set mdss_axi_clk ret = %d\n", ret); |
| 675 | ASSERT(0); |
| 676 | } |
| 677 | |
Asaf Penso | e149921 | 2013-08-04 18:09:53 +0300 | [diff] [blame] | 678 | ret = clk_get_set_enable("edp_pixel_clk", 138500000, 1); |
| 679 | if (ret) { |
| 680 | dprintf(CRITICAL, "failed to set edp_pixel_clk ret = %d\n", |
| 681 | ret); |
| 682 | ASSERT(0); |
| 683 | } |
| 684 | |
| 685 | ret = clk_get_set_enable("edp_link_clk", 270000000, 1); |
| 686 | if (ret) { |
| 687 | dprintf(CRITICAL, "failed to set edp_link_clk ret = %d\n", ret); |
| 688 | ASSERT(0); |
| 689 | } |
Kuogee Hsieh | e99937a | 2013-06-06 14:21:48 -0700 | [diff] [blame] | 690 | |
| 691 | ret = clk_get_set_enable("edp_aux_clk", 19200000, 1); |
| 692 | if (ret) { |
| 693 | dprintf(CRITICAL, "failed to set edp_aux_clk ret = %d\n", ret); |
| 694 | ASSERT(0); |
| 695 | } |
| 696 | } |
| 697 | |
| 698 | void edp_clk_disable(void) |
| 699 | { |
| 700 | |
| 701 | writel(0x0, MDSS_EDPPIXEL_CBCR); |
| 702 | writel(0x0, MDSS_EDPLINK_CBCR); |
| 703 | clk_disable(clk_get("edp_pixel_clk")); |
| 704 | clk_disable(clk_get("edp_link_clk")); |
| 705 | clk_disable(clk_get("edp_aux_clk")); |
Asaf Penso | e149921 | 2013-08-04 18:09:53 +0300 | [diff] [blame] | 706 | } |