Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions |
| 5 | * are met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer in |
| 10 | * the documentation and/or other materials provided with the |
| 11 | * distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 19 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 20 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 22 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
| 23 | * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
| 24 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 25 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 26 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 27 | * SUCH DAMAGE. |
| 28 | */ |
| 29 | |
| 30 | #include <debug.h> |
| 31 | #include <smem.h> |
| 32 | #include <err.h> |
| 33 | #include <msm_panel.h> |
| 34 | #include <mipi_dsi.h> |
| 35 | #include <pm8x41.h> |
| 36 | #include <pm8x41_wled.h> |
| 37 | #include <board.h> |
| 38 | #include <mdp5.h> |
| 39 | #include <scm.h> |
| 40 | #include <platform/gpio.h> |
| 41 | #include <platform/iomap.h> |
| 42 | #include <target/display.h> |
| 43 | |
| 44 | #include "include/panel.h" |
| 45 | #include "include/display_resource.h" |
| 46 | |
Padmanabhan Komanduru | dc41582 | 2014-04-01 19:29:53 +0530 | [diff] [blame] | 47 | #define DDR_LDO_ID 2 |
| 48 | #define QFPROM_LDO_ID 6 |
| 49 | |
Padmanabhan Komanduru | 18aa507 | 2014-04-17 16:52:53 +0530 | [diff] [blame] | 50 | #define VCO_DELAY_USEC 1000 |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 51 | #define GPIO_STATE_LOW 0 |
| 52 | #define GPIO_STATE_HIGH 2 |
| 53 | #define RESET_GPIO_SEQ_LEN 3 |
| 54 | #define PWM_DUTY_US 13 |
| 55 | #define PWM_PERIOD_US 27 |
| 56 | |
Padmanabhan Komanduru | 0a5db94 | 2014-04-17 16:56:04 +0530 | [diff] [blame] | 57 | static void mdss_dsi_uniphy_pll_sw_reset_8916(uint32_t pll_base) |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 58 | { |
Padmanabhan Komanduru | 0a5db94 | 2014-04-17 16:56:04 +0530 | [diff] [blame] | 59 | writel(0x01, pll_base + 0x0068); /* PLL TEST CFG */ |
| 60 | mdelay(1); |
| 61 | writel(0x00, pll_base + 0x0068); /* PLL TEST CFG */ |
| 62 | mdelay(1); |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 63 | } |
| 64 | |
Padmanabhan Komanduru | 0a5db94 | 2014-04-17 16:56:04 +0530 | [diff] [blame] | 65 | static uint32_t dsi_pll_enable_seq_8916(uint32_t pll_base) |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 66 | { |
| 67 | uint32_t pll_locked = 0; |
| 68 | |
Padmanabhan Komanduru | 0a5db94 | 2014-04-17 16:56:04 +0530 | [diff] [blame] | 69 | writel(0x01, pll_base + 0x0068); /* PLL TEST CFG */ |
| 70 | udelay(1); |
| 71 | writel(0x00, pll_base + 0x0068); /* PLL TEST CFG */ |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 72 | |
| 73 | /* |
| 74 | * Add hardware recommended delays between register writes for |
| 75 | * the updates to take effect. These delays are necessary for the |
| 76 | * PLL to successfully lock |
| 77 | */ |
Padmanabhan Komanduru | 0a5db94 | 2014-04-17 16:56:04 +0530 | [diff] [blame] | 78 | writel(0x34, pll_base + 0x0070); /* CAL CFG1*/ |
| 79 | udelay(1); |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 80 | writel(0x01, pll_base + 0x0020); /* GLB CFG */ |
Padmanabhan Komanduru | 0a5db94 | 2014-04-17 16:56:04 +0530 | [diff] [blame] | 81 | udelay(1); |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 82 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 83 | udelay(1); |
| 84 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
Padmanabhan Komanduru | 0a5db94 | 2014-04-17 16:56:04 +0530 | [diff] [blame] | 85 | udelay(1); |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 86 | |
Padmanabhan Komanduru | 0a5db94 | 2014-04-17 16:56:04 +0530 | [diff] [blame] | 87 | writel(0x04, pll_base + 0x0064); /* LKDetect CFG2 */ |
| 88 | udelay(1); |
| 89 | writel(0x05, pll_base + 0x0064); /* LKDetect CFG2 */ |
| 90 | udelay(512); |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 91 | pll_locked = readl(pll_base + 0x00c0) & 0x01; |
| 92 | |
| 93 | return pll_locked; |
| 94 | } |
| 95 | |
| 96 | int target_backlight_ctrl(struct backlight *bl, uint8_t enable) |
| 97 | { |
| 98 | struct pm8x41_mpp mpp; |
| 99 | int rc; |
| 100 | |
Shuo Yan | 123546b | 2014-05-19 19:35:41 +0800 | [diff] [blame] | 101 | if (bl->bl_interface_type == BL_DCS) |
| 102 | return 0; |
| 103 | |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 104 | mpp.base = PM8x41_MMP4_BASE; |
| 105 | mpp.vin = MPP_VIN0; |
| 106 | if (enable) { |
| 107 | pm_pwm_enable(false); |
| 108 | rc = pm_pwm_config(PWM_DUTY_US, PWM_PERIOD_US); |
| 109 | if (rc < 0) |
| 110 | mpp.mode = MPP_HIGH; |
| 111 | else { |
| 112 | mpp.mode = MPP_DTEST1; |
| 113 | pm_pwm_enable(true); |
| 114 | } |
| 115 | pm8x41_config_output_mpp(&mpp); |
| 116 | pm8x41_enable_mpp(&mpp, MPP_ENABLE); |
| 117 | } else { |
| 118 | pm_pwm_enable(false); |
| 119 | pm8x41_enable_mpp(&mpp, MPP_DISABLE); |
| 120 | } |
| 121 | mdelay(20); |
| 122 | return 0; |
| 123 | } |
| 124 | |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 125 | int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo) |
| 126 | { |
| 127 | int32_t ret = 0; |
| 128 | struct mdss_dsi_pll_config *pll_data; |
| 129 | dprintf(SPEW, "target_panel_clock\n"); |
| 130 | |
| 131 | pll_data = pinfo->mipi.dsi_pll_config; |
Padmanabhan Komanduru | 18aa507 | 2014-04-17 16:52:53 +0530 | [diff] [blame] | 132 | pll_data->vco_delay = VCO_DELAY_USEC; |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 133 | |
| 134 | if (enable) { |
| 135 | mdp_gdsc_ctrl(enable); |
| 136 | mdss_bus_clocks_enable(); |
| 137 | mdp_clock_enable(); |
| 138 | ret = restore_secure_cfg(SECURE_DEVICE_MDSS); |
| 139 | if (ret) { |
| 140 | dprintf(CRITICAL, |
| 141 | "%s: Failed to restore MDP security configs", |
| 142 | __func__); |
| 143 | mdp_clock_disable(); |
| 144 | mdss_bus_clocks_disable(); |
| 145 | mdp_gdsc_ctrl(0); |
| 146 | return ret; |
| 147 | } |
Padmanabhan Komanduru | 0a5db94 | 2014-04-17 16:56:04 +0530 | [diff] [blame] | 148 | mdss_dsi_uniphy_pll_sw_reset_8916(DSI0_PLL_BASE); |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 149 | mdss_dsi_auto_pll_config(DSI0_PLL_BASE, |
| 150 | MIPI_DSI0_BASE, pll_data); |
Padmanabhan Komanduru | 0a5db94 | 2014-04-17 16:56:04 +0530 | [diff] [blame] | 151 | if (!dsi_pll_enable_seq_8916(DSI0_PLL_BASE)) |
| 152 | dprintf(CRITICAL, "Not able to enable the pll\n"); |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 153 | gcc_dsi_clocks_enable(pll_data->pclk_m, |
| 154 | pll_data->pclk_n, |
| 155 | pll_data->pclk_d); |
| 156 | } else if(!target_cont_splash_screen()) { |
| 157 | gcc_dsi_clocks_disable(); |
| 158 | mdp_clock_disable(); |
| 159 | mdss_bus_clocks_disable(); |
| 160 | mdp_gdsc_ctrl(enable); |
| 161 | } |
| 162 | |
| 163 | return 0; |
| 164 | } |
| 165 | |
| 166 | int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq, |
| 167 | struct msm_panel_info *pinfo) |
| 168 | { |
| 169 | int ret = NO_ERROR; |
Mao Flynn | 8140947 | 2014-04-10 15:01:30 +0800 | [diff] [blame] | 170 | uint32_t hw_id = board_hardware_id(); |
| 171 | uint32_t hw_subtype = board_hardware_subtype(); |
| 172 | |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 173 | if (enable) { |
| 174 | if (pinfo->mipi.use_enable_gpio) { |
| 175 | gpio_tlmm_config(enable_gpio.pin_id, 0, |
| 176 | enable_gpio.pin_direction, enable_gpio.pin_pull, |
| 177 | enable_gpio.pin_strength, |
| 178 | enable_gpio.pin_state); |
| 179 | |
| 180 | gpio_set_dir(enable_gpio.pin_id, 2); |
| 181 | } |
| 182 | |
Shuo Yan | c8a417f | 2014-05-20 14:44:56 +0800 | [diff] [blame^] | 183 | if (hw_id == HW_PLATFORM_QRD && |
Mao Flynn | 8140947 | 2014-04-10 15:01:30 +0800 | [diff] [blame] | 184 | hw_subtype == HW_PLATFORM_SUBTYPE_SKUH) { |
| 185 | /* for tps65132 ENP */ |
| 186 | gpio_tlmm_config(enp_gpio.pin_id, 0, |
| 187 | enp_gpio.pin_direction, enp_gpio.pin_pull, |
| 188 | enp_gpio.pin_strength, |
| 189 | enp_gpio.pin_state); |
| 190 | gpio_set_dir(enp_gpio.pin_id, 2); |
| 191 | |
| 192 | /* for tps65132 ENN */ |
| 193 | gpio_tlmm_config(enn_gpio.pin_id, 0, |
| 194 | enn_gpio.pin_direction, enn_gpio.pin_pull, |
| 195 | enn_gpio.pin_strength, |
| 196 | enn_gpio.pin_state); |
| 197 | gpio_set_dir(enn_gpio.pin_id, 2); |
| 198 | } |
| 199 | |
Shuo Yan | c8a417f | 2014-05-20 14:44:56 +0800 | [diff] [blame^] | 200 | if (hw_id == HW_PLATFORM_MTP || hw_id == HW_PLATFORM_SURF) { |
| 201 | /* configure backlight gpio for MTP & CDP */ |
| 202 | gpio_tlmm_config(bkl_gpio.pin_id, 0, |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 203 | bkl_gpio.pin_direction, bkl_gpio.pin_pull, |
| 204 | bkl_gpio.pin_strength, bkl_gpio.pin_state); |
Shuo Yan | c8a417f | 2014-05-20 14:44:56 +0800 | [diff] [blame^] | 205 | gpio_set_dir(bkl_gpio.pin_id, 2); |
| 206 | } |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 207 | |
| 208 | gpio_tlmm_config(reset_gpio.pin_id, 0, |
| 209 | reset_gpio.pin_direction, reset_gpio.pin_pull, |
| 210 | reset_gpio.pin_strength, reset_gpio.pin_state); |
| 211 | |
| 212 | gpio_set_dir(reset_gpio.pin_id, 2); |
| 213 | |
| 214 | /* reset */ |
| 215 | for (int i = 0; i < RESET_GPIO_SEQ_LEN; i++) { |
| 216 | if (resetseq->pin_state[i] == GPIO_STATE_LOW) |
| 217 | gpio_set_dir(reset_gpio.pin_id, GPIO_STATE_LOW); |
| 218 | else |
| 219 | gpio_set_dir(reset_gpio.pin_id, GPIO_STATE_HIGH); |
| 220 | mdelay(resetseq->sleep[i]); |
| 221 | } |
| 222 | } else if(!target_cont_splash_screen()) { |
| 223 | gpio_set_dir(reset_gpio.pin_id, 0); |
| 224 | if (pinfo->mipi.use_enable_gpio) |
| 225 | gpio_set_dir(enable_gpio.pin_id, 0); |
Mao Flynn | 8140947 | 2014-04-10 15:01:30 +0800 | [diff] [blame] | 226 | |
| 227 | if(hw_id == HW_PLATFORM_QRD && |
| 228 | hw_subtype == HW_PLATFORM_SUBTYPE_SKUH) { |
| 229 | gpio_set_dir(enp_gpio.pin_id, 0); /* ENP */ |
| 230 | gpio_set_dir(enn_gpio.pin_id, 0); /* ENN */ |
| 231 | } |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 232 | } |
| 233 | |
| 234 | return ret; |
| 235 | } |
| 236 | |
| 237 | int target_ldo_ctrl(uint8_t enable) |
| 238 | { |
| 239 | uint32_t ret = NO_ERROR; |
| 240 | uint32_t ldocounter = 0; |
| 241 | uint32_t pm8x41_ldo_base = 0x13F00; |
| 242 | |
| 243 | while (ldocounter < TOTAL_LDO_DEFINED) { |
| 244 | dprintf(SPEW, "Setting %i\n", |
| 245 | ldo_entry_array[ldocounter].ldo_id); |
| 246 | struct pm8x41_ldo ldo_entry = LDO((pm8x41_ldo_base + |
| 247 | 0x100 * ldo_entry_array[ldocounter].ldo_id), |
| 248 | ldo_entry_array[ldocounter].ldo_type); |
| 249 | |
| 250 | |
| 251 | /* Set voltage during power on */ |
| 252 | if (enable) { |
| 253 | /* TODO: Set the LDO voltage before enabling it */ |
| 254 | pm8x41_ldo_control(&ldo_entry, enable); |
| 255 | |
Padmanabhan Komanduru | dc41582 | 2014-04-01 19:29:53 +0530 | [diff] [blame] | 256 | } else if(!target_cont_splash_screen() && |
| 257 | ldo_entry_array[ldocounter].ldo_id != DDR_LDO_ID && |
| 258 | ldo_entry_array[ldocounter].ldo_id != QFPROM_LDO_ID) { |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 259 | pm8x41_ldo_control(&ldo_entry, enable); |
| 260 | } |
| 261 | ldocounter++; |
| 262 | } |
| 263 | |
| 264 | return ret; |
| 265 | } |
| 266 | |
| 267 | bool target_display_panel_node(char *panel_name, char *pbuf, uint16_t buf_size) |
| 268 | { |
| 269 | return gcdb_display_cmdline_arg(pbuf, buf_size); |
| 270 | } |
| 271 | |
| 272 | void target_display_init(const char *panel_name) |
| 273 | { |
Padmanabhan Komanduru | 1869a76 | 2014-04-01 20:12:05 +0530 | [diff] [blame] | 274 | uint32_t panel_loop = 0; |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 275 | uint32_t ret = 0; |
Padmanabhan Komanduru | 1869a76 | 2014-04-01 20:12:05 +0530 | [diff] [blame] | 276 | do { |
| 277 | ret = gcdb_display_init(panel_name, MDP_REV_50, MIPI_FB_ADDR); |
| 278 | if (!ret || ret == ERR_NOT_SUPPORTED) { |
| 279 | break; |
| 280 | } else { |
| 281 | target_force_cont_splash_disable(true); |
| 282 | msm_display_off(); |
| 283 | target_force_cont_splash_disable(false); |
| 284 | } |
| 285 | } while (++panel_loop <= oem_panel_max_auto_detect_panels()); |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 286 | } |
| 287 | |
| 288 | void target_display_shutdown(void) |
| 289 | { |
| 290 | gcdb_display_shutdown(); |
| 291 | } |