blob: 17fbf888cb4f974c8bb7026f48e4545a1839b95c [file] [log] [blame]
Sundarajan Srinivasan61d046a2014-01-02 17:26:03 -08001/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
Deepa Dinamani0a976552012-11-28 17:01:27 -08002 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <reg.h>
30#include <debug.h>
31#include <endian.h>
32#include <stdlib.h>
33#include <arch/ops.h>
34#include <platform.h>
35#include <platform/iomap.h>
36#include <clock.h>
37#include <platform/clock.h>
38#include <crypto5_eng.h>
39
40#define CLEAR_STATUS(dev) crypto_write_reg(&dev->bam, CRYPTO_STATUS(dev->base), 0, BAM_DESC_UNLOCK_FLAG)
41#define CONFIG_WRITE(dev, val) crypto_write_reg(&dev->bam, CRYPTO_CONFIG(dev->base), val, BAM_DESC_LOCK_FLAG)
42#define REG_WRITE(dev, addr, val) crypto_write_reg(&dev->bam, addr, val, 0)
43
Deepa Dinamanibcc62d22013-05-10 14:10:05 -070044#ifndef CRYPTO_REG_ACCESS
45#define CE_INIT(dev) dev->ce_array_index = 0; dev->cd_start = 0
Deepa Dinamani0a976552012-11-28 17:01:27 -080046#define ADD_WRITE_CE(dev, addr, val) crypto_add_cmd_element(dev, addr, val)
Deepa Dinamani0a976552012-11-28 17:01:27 -080047#define ADD_CMD_DESC(dev, flags) crypto_add_cmd_desc(dev, flags)
Deepa Dinamanibcc62d22013-05-10 14:10:05 -070048#define CMD_EXEC(bam, num_desc, pipe) crypto_wait_for_cmd_exec(bam, num_desc, pipe)
49
50#define REG_WRITE_QUEUE_INIT(dev) CE_INIT(dev)
51#define REG_WRITE_QUEUE(dev, addr, val) ADD_WRITE_CE(dev, addr, val)
52#define REG_WRITE_QUEUE_DONE(dev, flags) ADD_CMD_DESC(dev, flags)
53#define REG_WRITE_EXEC(bam, num_desc, pipe) CMD_EXEC(bam, num_desc, pipe)
54#else
55#define REG_WRITE_QUEUE_INIT(dev) /* nop */
56#define REG_WRITE_QUEUE(dev, addr, val) writel(val, addr)
57#define REG_WRITE_QUEUE_DONE(dev, flags) /* nop */
58#define REG_WRITE_EXEC(bam, num_desc, pipe) /* nop */
59#endif
60
Deepa Dinamani0a976552012-11-28 17:01:27 -080061#define ADD_READ_DESC(bam, buf_addr, buf_size, flags) bam_add_desc(bam, CRYPTO_READ_PIPE_INDEX, buf_addr, buf_size, flags)
62#define ADD_WRITE_DESC(bam, buf_addr, buf_size, flags) bam_add_desc(bam, CRYPTO_WRITE_PIPE_INDEX, buf_addr, buf_size, flags)
63
Deepa Dinamani0a976552012-11-28 17:01:27 -080064
65static struct bam_desc *crypto_allocate_fifo(uint32_t size)
66{
67 struct bam_desc *ptr;
68
69 ptr = (struct bam_desc *) memalign(lcm(CACHE_LINE, BAM_DESC_SIZE),
70 ROUNDUP(size * BAM_DESC_SIZE, CACHE_LINE));
71
72 if (ptr == NULL)
73 dprintf(CRITICAL, "Could not allocate fifo buffer\n");
74
75 return ptr;
76}
77
78static struct output_dump *crypto_allocate_dump_buffer(void)
79{
80 struct output_dump *ptr;
81
82 ptr = (struct output_dump *) memalign(lcm(CACHE_LINE, CRYPTO_BURST_LEN),
83 ROUNDUP(sizeof(struct output_dump), CACHE_LINE));
84
85 if (ptr == NULL)
86 dprintf(CRITICAL, "Could not allocate output dump buffer\n");
87
88 return ptr;
89}
90
91static struct cmd_element *crypto_allocate_ce_array(uint32_t size)
92{
Deepa Dinamanibcc62d22013-05-10 14:10:05 -070093 struct cmd_element *ptr = NULL;
Deepa Dinamani0a976552012-11-28 17:01:27 -080094
Deepa Dinamanibcc62d22013-05-10 14:10:05 -070095#ifndef CRYPTO_REG_ACCESS
Deepa Dinamani0a976552012-11-28 17:01:27 -080096 ptr = (struct cmd_element*) memalign(CACHE_LINE,
97 ROUNDUP(size * sizeof(struct cmd_element), CACHE_LINE));
98
99 if (ptr == NULL)
100 dprintf(CRITICAL, "Could not allocate ce array buffer\n");
Deepa Dinamanibcc62d22013-05-10 14:10:05 -0700101#endif
Deepa Dinamani0a976552012-11-28 17:01:27 -0800102
103 return ptr;
104}
105
106static void crypto_wait_for_cmd_exec(struct bam_instance *bam_core,
107 uint32_t num_desc,
108 uint8_t pipe)
109{
110 /* Create a read/write event to notify the periperal of the added desc. */
111 bam_sys_gen_event(bam_core, pipe, num_desc);
112
113 /* Wait for the descriptors to be processed */
114 bam_wait_for_interrupt(bam_core, pipe, P_PRCSD_DESC_EN_MASK);
115
116 /* Read offset update for the circular FIFO */
117 bam_read_offset_update(bam_core, pipe);
118}
119
120static void crypto_wait_for_data(struct bam_instance *bam, uint32_t pipe_num)
121{
122 /* Wait for the descriptors to be processed */
123 bam_wait_for_interrupt(bam, pipe_num, P_PRCSD_DESC_EN_MASK);
124
125 /* Read offset update for the circular FIFO */
126 bam_read_offset_update(bam, pipe_num);
127}
128
129static uint32_t crypto_write_reg(struct bam_instance *bam_core,
130 uint32_t reg_addr,
131 uint32_t val,
132 uint8_t flags)
133{
134 uint32_t ret = 0;
135 struct cmd_element cmd_list_ptr;
136
Deepa Dinamanibcc62d22013-05-10 14:10:05 -0700137#ifdef CRYPTO_REG_ACCESS
138 writel(val, reg_addr);
139#else
Deepa Dinamani0a976552012-11-28 17:01:27 -0800140 ret = (uint32_t)bam_add_cmd_element(&cmd_list_ptr, reg_addr, val, CE_WRITE_TYPE);
141
142 /* Enqueue the desc for the above command */
143 ret = bam_add_one_desc(bam_core,
144 CRYPTO_WRITE_PIPE_INDEX,
145 (unsigned char*)PA((addr_t)&cmd_list_ptr),
146 BAM_CE_SIZE,
147 BAM_DESC_CMD_FLAG | BAM_DESC_INT_FLAG | flags);
148
149 if (ret)
150 {
151 dprintf(CRITICAL,
152 "CRYPTO_WRITE_REG: Reg write failed. reg addr = %x\n",
153 reg_addr);
154 goto crypto_read_reg_err;
155 }
156
157 crypto_wait_for_cmd_exec(bam_core, 1, CRYPTO_WRITE_PIPE_INDEX);
Deepa Dinamanibcc62d22013-05-10 14:10:05 -0700158#endif
Deepa Dinamani0a976552012-11-28 17:01:27 -0800159
160crypto_read_reg_err:
Deepa Dinamanibcc62d22013-05-10 14:10:05 -0700161 return ret;
Deepa Dinamani0a976552012-11-28 17:01:27 -0800162}
163
164static void crypto_add_cmd_element(struct crypto_dev *dev,
165 uint32_t addr,
166 uint32_t val)
167{
168 struct cmd_element *ptr = dev->ce_array;
169
170 bam_add_cmd_element(&(ptr[dev->ce_array_index]), addr, val, CE_WRITE_TYPE);
171
172 arch_clean_invalidate_cache_range((addr_t) &(ptr[dev->ce_array_index]), sizeof(struct cmd_element));
173
174 dev->ce_array_index++;
175}
176
177static void crypto_add_cmd_desc(struct crypto_dev *dev, uint8_t flags)
178{
179 uint32_t ce_size;
180 uint32_t start = (uint32_t)&(dev->ce_array[dev->cd_start]);
181 uint32_t ret;
182
183 ce_size = (uint32_t)&(dev->ce_array[dev->ce_array_index]) - start;
184
185 ret = bam_add_one_desc(&dev->bam,
186 CRYPTO_WRITE_PIPE_INDEX,
187 (unsigned char*)start,
188 ce_size,
189 BAM_DESC_CMD_FLAG | flags);
190
191 if (ret)
192 {
193 dprintf(CRITICAL, "CRYPTO_ADD_DESC: Adding desc failed\n");
194 }
195
196 /* Update the CD ptr. */
197 dev->cd_start = dev->ce_array_index;
198}
199
200static int crypto_bam_init(struct crypto_dev *dev)
201{
202 uint32_t bam_ret;
203
Deepa Dinamanibcc62d22013-05-10 14:10:05 -0700204 /* Do BAM Init only if required. */
205 if (dev->do_bam_init)
206 bam_init(&dev->bam);
Deepa Dinamani0a976552012-11-28 17:01:27 -0800207
208 /* Initialize BAM CRYPTO read pipe */
209 bam_sys_pipe_init(&dev->bam, CRYPTO_READ_PIPE_INDEX);
210
211 /* Init read fifo */
212 bam_ret = bam_pipe_fifo_init(&dev->bam, CRYPTO_READ_PIPE_INDEX);
213
214 if (bam_ret)
215 {
216 dprintf(CRITICAL, "CRYPTO: BAM Read FIFO init error\n");
217 bam_ret = CRYPTO_ERR_FAIL;
218 goto crypto_bam_init_err;
219 }
220
221 /* Initialize BAM CRYPTO write pipe */
222 bam_sys_pipe_init(&dev->bam, CRYPTO_WRITE_PIPE_INDEX);
223
224 /* Init write fifo. Use the same fifo as read fifo. */
225 bam_ret = bam_pipe_fifo_init(&dev->bam, CRYPTO_WRITE_PIPE_INDEX);
226
227 if (bam_ret)
228 {
229 dprintf(CRITICAL, "CRYPTO: BAM Write FIFO init error\n");
230 bam_ret = CRYPTO_ERR_FAIL;
231 goto crypto_bam_init_err;
232 }
233
234 bam_ret = CRYPTO_ERR_NONE;
235
236crypto_bam_init_err:
237 return bam_ret;
238}
239
240static void crypto_reset(struct crypto_dev *dev)
241{
242 clock_config_ce(dev->instance);
243}
244
245void crypto5_init_params(struct crypto_dev *dev, struct crypto_init_params *params)
246{
247 dev->base = params->crypto_base;
248 dev->instance = params->crypto_instance;
249
Deepa Dinamanibcc62d22013-05-10 14:10:05 -0700250 dev->bam.base = params->bam_base;
251 dev->do_bam_init = params->do_bam_init;
Deepa Dinamani0a976552012-11-28 17:01:27 -0800252
253 /* Set Read pipe params. */
254 dev->bam.pipe[CRYPTO_READ_PIPE_INDEX].pipe_num = params->pipes.read_pipe;
255 /* System consumer */
256 dev->bam.pipe[CRYPTO_READ_PIPE_INDEX].trans_type = BAM2SYS;
257 dev->bam.pipe[CRYPTO_READ_PIPE_INDEX].fifo.size = params->read_fifo_size;
258 dev->bam.pipe[CRYPTO_READ_PIPE_INDEX].fifo.head = crypto_allocate_fifo(params->read_fifo_size);
Deepa Dinamani48637cd2013-07-09 14:04:21 -0700259 dev->bam.pipe[CRYPTO_READ_PIPE_INDEX].lock_grp = params->pipes.read_pipe_grp;
Deepa Dinamani0a976552012-11-28 17:01:27 -0800260
261 /* Set Write pipe params. */
262 dev->bam.pipe[CRYPTO_WRITE_PIPE_INDEX].pipe_num = params->pipes.write_pipe;
263 /* System producer */
264 dev->bam.pipe[CRYPTO_WRITE_PIPE_INDEX].trans_type = SYS2BAM;
265 dev->bam.pipe[CRYPTO_WRITE_PIPE_INDEX].fifo.size = params->write_fifo_size;
266 dev->bam.pipe[CRYPTO_WRITE_PIPE_INDEX].fifo.head = crypto_allocate_fifo(params->write_fifo_size);
Deepa Dinamani48637cd2013-07-09 14:04:21 -0700267 dev->bam.pipe[CRYPTO_WRITE_PIPE_INDEX].lock_grp = params->pipes.write_pipe_grp;
Deepa Dinamani0a976552012-11-28 17:01:27 -0800268
269 dev->bam.threshold = CRYPTO_MAX_THRESHOLD;
270
271 dev->bam.ee = params->bam_ee;
272
273 /* A H/W bug on Crypto 5.0.0 enforces a rule that the desc lengths must be burst aligned. */
274 dev->bam.max_desc_len = ROUNDDOWN(BAM_NDP_MAX_DESC_DATA_LEN, CRYPTO_BURST_LEN);
275
276 dev->dump = crypto_allocate_dump_buffer();
277 dev->ce_array = crypto_allocate_ce_array(params->num_ce);
278 dev->ce_array_index = 0;
279 dev->cd_start = 0;
280}
281
282void crypto5_init(struct crypto_dev *dev)
283{
284 uint32_t config = CRYPTO_RESET_CONFIG
285 | (dev->bam.pipe[CRYPTO_READ_PIPE_INDEX].pipe_num >> 1) << PIPE_SET_SELECT_SHIFT;
286
287 /* Configure CE clocks. */
288 clock_config_ce(dev->instance);
289
290 /* Setup BAM */
291 if (crypto_bam_init(dev) != CRYPTO_ERR_NONE)
292 {
293 dprintf(CRITICAL, "CRYPTO: BAM init error\n");
294 goto crypto_init_err;
295 }
296
297 /* Write basic config to CE.
298 * Note: This setting will be changed to be set from TZ.
299 */
300 writel(config, CRYPTO_CONFIG(dev->base));
301
302 config = 0;
303
304 /* Setup config reg. */
305 /* Mask all irqs. */
306 config |= MASK_ERR_INTR | MASK_OP_DONE_INTR |
307 MASK_DIN_INTR | MASK_DOUT_INTR;
308 /* Program BAM specific crypto settings. */
309 config |= HIGH_SPD_IN_EN_N
310 | ((dev->bam.pipe[CRYPTO_WRITE_PIPE_INDEX].pipe_num >> 1) << PIPE_SET_SELECT_SHIFT)
311 | MAX_QUEUED_REQS
312 | REQ_SIZE;
313 /* Use a few registers in little endian mode. */
314 config |= LITTLE_ENDIAN_MODE;
315
316 CONFIG_WRITE(dev, config);
317
318crypto_init_err:
319 return;
320}
321
322static uint32_t crypto5_get_sha_cfg(void *ctx_ptr, crypto_auth_alg_type auth_alg)
323{
324 crypto_SHA256_ctx *sha256_ctx = (crypto_SHA256_ctx *) ctx_ptr;
325 uint32_t seg_cfg_val;
326
327 seg_cfg_val = SEG_CFG_AUTH_ALG_SHA;
328
329 if (auth_alg == CRYPTO_AUTH_ALG_SHA256)
330 {
331 seg_cfg_val |= SEG_CFG_AUTH_SIZE_SHA256;
332
333 if (sha256_ctx->flags & CRYPTO_LAST_CHUNK)
334 {
335 seg_cfg_val |= SEG_CFG_LAST;
336 }
337 }
338 else
339 {
340 dprintf(CRITICAL, "crypto_set_sha_ctx invalid auth algorithm\n");
341 return 0;
342 }
343
344 return seg_cfg_val;
345}
346
347void crypto5_set_ctx(struct crypto_dev *dev,
348 void *ctx_ptr,
349 crypto_auth_alg_type auth_alg)
350{
Sundarajan Srinivasanb7e7e942014-01-08 14:08:04 -0800351 crypto_SHA256_ctx *sha256_ctx = (crypto_SHA256_ctx *) ctx_ptr;
352 crypto_SHA1_ctx *sha1_ctx = (crypto_SHA1_ctx *) ctx_ptr;
353 uint32_t i = 0;
354 uint32_t iv_len = 0;
355 uint32_t *auth_iv = sha1_ctx->auth_iv;
356 uint32_t seg_cfg_val;
357
358 if(auth_alg == CRYPTO_AUTH_ALG_SHA1)
359 {
360 iv_len = SHA1_INIT_VECTOR_SIZE;
361 }
362 else if(auth_alg == CRYPTO_AUTH_ALG_SHA256)
363 {
364 iv_len = SHA256_INIT_VECTOR_SIZE;
365 }
Deepa Dinamani0a976552012-11-28 17:01:27 -0800366
367 seg_cfg_val = crypto5_get_sha_cfg(ctx_ptr, auth_alg);
368
369 if (!seg_cfg_val)
370 {
371 dprintf(CRITICAL, "Authentication alg config failed.\n");
372 return;
373 }
374
375 /* Initialize CE pointers. */
Deepa Dinamanibcc62d22013-05-10 14:10:05 -0700376 REG_WRITE_QUEUE_INIT(dev);
Deepa Dinamani0a976552012-11-28 17:01:27 -0800377
Sundarajan Srinivasanb7e7e942014-01-08 14:08:04 -0800378 /* For authentication operation set the encryption cfg reg to 0 as per HPG */
379 REG_WRITE_QUEUE(dev, CRYPTO_ENCR_SEG_CFG(dev->base), 0);
380 REG_WRITE_QUEUE(dev, CRYPTO_AUTH_SEG_CFG(dev->base), seg_cfg_val);
Deepa Dinamani0a976552012-11-28 17:01:27 -0800381
382 for (i = 0; i < iv_len; i++)
383 {
384 if (sha256_ctx->flags & CRYPTO_FIRST_CHUNK)
Deepa Dinamanibcc62d22013-05-10 14:10:05 -0700385 REG_WRITE_QUEUE(dev, CRYPTO_AUTH_IVn(dev->base, i), BE32(*(auth_iv + i)));
Deepa Dinamani0a976552012-11-28 17:01:27 -0800386 else
Deepa Dinamanibcc62d22013-05-10 14:10:05 -0700387 REG_WRITE_QUEUE(dev, CRYPTO_AUTH_IVn(dev->base, i), (*(auth_iv + i)));
Deepa Dinamani0a976552012-11-28 17:01:27 -0800388 }
389
Deepa Dinamani0a976552012-11-28 17:01:27 -0800390 /* Typecast with crypto_SHA1_ctx because offset of auth_bytecnt
391 * in both crypto_SHA1_ctx and crypto_SHA256_ctx are same.
392 */
Sundarajan Srinivasanb7e7e942014-01-08 14:08:04 -0800393 REG_WRITE_QUEUE(dev, CRYPTO_AUTH_BYTECNTn(dev->base, 0), ((crypto_SHA1_ctx *) ctx_ptr)->auth_bytecnt[0]);
394 REG_WRITE_QUEUE(dev, CRYPTO_AUTH_BYTECNTn(dev->base, 1), ((crypto_SHA1_ctx *) ctx_ptr)->auth_bytecnt[1]);
395}
Deepa Dinamani0a976552012-11-28 17:01:27 -0800396
Sundarajan Srinivasanb7e7e942014-01-08 14:08:04 -0800397/* Function: crypto5_set_auth_cfg
398 * Arg : dev, ptr to data buffer, buffer_size, burst_mask for alignment
399 * Return : aligned buffer incase of unaligned data_ptr and total no. of bytes
400 * passed to crypto HW(includes header and trailer size).
401 * Flow : If data buffer is aligned, we just configure the crypto auth
402 * registers for start, size of data etc. If buffer is unaligned
403 * we align it to burst(64-byte) boundary and also make the no. of
404 * bytes a multiple of 64 for bam and then configure the registers
405 * for header/trailer settings.
406 */
Deepa Dinamani0a976552012-11-28 17:01:27 -0800407
Sundarajan Srinivasanb7e7e942014-01-08 14:08:04 -0800408static void crypto5_set_auth_cfg(struct crypto_dev *dev, uint8_t **buffer,
409 uint8_t *data_ptr,
410 uint32_t burst_mask,
411 uint32_t bytes_to_write,
412 uint32_t *total_bytes_to_write)
413{
414 uint32_t minor_ver = 0;
415 uint32_t auth_seg_start = 0;
Deepa Dinamani0a976552012-11-28 17:01:27 -0800416
Sundarajan Srinivasanb7e7e942014-01-08 14:08:04 -0800417 /* Bits 23:16 - minor version */
418 minor_ver = (readl(CRYPTO_VERSION(dev->base)) & 0x00FF0000) >> 16;
419
420 /* A H/W bug on Crypto 5.0.0 enforces a rule that the desc lengths must
421 * be burst aligned. Here we use the header/trailer crypto register settings.
422 * buffer : The previous 64 byte aligned address for data_ptr.
423 * CRYPTO_AUTH_SEG_START : Number of bytes to skip to reach the address data_ptr.
424 * CRYPTO_AUTH_SEG_SIZE : Number of bytes to be sent to crypto HW.
425 * CRYPTO_SEG_SIZE : CRYPTO_AUTH_SEG_START + CRYPTO_AUTH_SEG_SIZE.
426 * Function: We pick a previous 64 byte aligned address buffer, and tell crypto to
427 * skip (data_ptr - buffer) number of bytes.
428 * This bug is fixed in 5.1.0 onwards.*/
429
430 if(minor_ver == 0)
431 {
432 if ((uint32_t) data_ptr & (CRYPTO_BURST_LEN - 1))
433 {
434 dprintf(CRITICAL, "Data start not aligned at burst length.\n");
435
436 *buffer = (uint8_t *)ROUNDDOWN((uint32_t)data_ptr, CRYPTO_BURST_LEN);
437
438 /* Header & Trailer */
439 *total_bytes_to_write = ((bytes_to_write +(data_ptr - *buffer) + burst_mask) & (~burst_mask));
440
441 auth_seg_start = (data_ptr - *buffer);
442 }
443 else
444 {
445 /* No header */
446 /* Add trailer to make it a burst multiple as 5.0.x HW mandates data to be a multiple of 64. */
447 *total_bytes_to_write = (bytes_to_write + burst_mask) & (~burst_mask);
448 }
449 }
450 else
451 {
452 /* No header. 5.1 crypto HW doesnt require alignment as partial reads and writes are possible*/
453 *total_bytes_to_write = bytes_to_write;
454 }
455
456 REG_WRITE_QUEUE(dev, CRYPTO_AUTH_SEG_START(dev->base), auth_seg_start);
457 REG_WRITE_QUEUE(dev, CRYPTO_AUTH_SEG_SIZE(dev->base), bytes_to_write);
458 REG_WRITE_QUEUE(dev, CRYPTO_SEG_SIZE(dev->base), *total_bytes_to_write);
459 REG_WRITE_QUEUE(dev, CRYPTO_GOPROC(dev->base), GOPROC_GO);
Deepa Dinamanibcc62d22013-05-10 14:10:05 -0700460 REG_WRITE_QUEUE_DONE(dev, BAM_DESC_LOCK_FLAG | BAM_DESC_INT_FLAG);
Deepa Dinamanibcc62d22013-05-10 14:10:05 -0700461 REG_WRITE_EXEC(&dev->bam, 1, CRYPTO_WRITE_PIPE_INDEX);
Deepa Dinamani0a976552012-11-28 17:01:27 -0800462}
463
464uint32_t crypto5_send_data(struct crypto_dev *dev,
465 void *ctx_ptr,
466 uint8_t *data_ptr)
467{
468 uint32_t bam_status;
469 crypto_SHA256_ctx *sha256_ctx = (crypto_SHA256_ctx *) ctx_ptr;
470 uint32_t wr_flags = BAM_DESC_NWD_FLAG | BAM_DESC_INT_FLAG | BAM_DESC_EOT_FLAG;
471 uint32_t ret_status;
Sundarajan Srinivasan61d046a2014-01-02 17:26:03 -0800472 uint8_t *buffer = NULL;
Sundarajan Srinivasanb7e7e942014-01-08 14:08:04 -0800473 uint32_t total_bytes_to_write = 0;
Deepa Dinamani0a976552012-11-28 17:01:27 -0800474
Sundarajan Srinivasanb7e7e942014-01-08 14:08:04 -0800475 crypto5_set_auth_cfg(dev, &buffer, data_ptr, CRYPTO_BURST_LEN - 1, sha256_ctx->bytes_to_write,
476 &total_bytes_to_write);
Deepa Dinamani0a976552012-11-28 17:01:27 -0800477
Sundarajan Srinivasan61d046a2014-01-02 17:26:03 -0800478 if(buffer)
479 {
Sundarajan Srinivasanb7e7e942014-01-08 14:08:04 -0800480 arch_clean_invalidate_cache_range((addr_t) buffer, total_bytes_to_write);
Deepa Dinamani0a976552012-11-28 17:01:27 -0800481
Sundarajan Srinivasanb7e7e942014-01-08 14:08:04 -0800482 bam_status = ADD_WRITE_DESC(&dev->bam, buffer, total_bytes_to_write, wr_flags);
Sundarajan Srinivasan61d046a2014-01-02 17:26:03 -0800483 }
484 else
485 {
Sundarajan Srinivasanb7e7e942014-01-08 14:08:04 -0800486 arch_clean_invalidate_cache_range((addr_t) data_ptr, total_bytes_to_write);
487 bam_status = ADD_WRITE_DESC(&dev->bam, data_ptr, total_bytes_to_write, wr_flags);
Sundarajan Srinivasan61d046a2014-01-02 17:26:03 -0800488 }
Deepa Dinamani0a976552012-11-28 17:01:27 -0800489
490 if (bam_status)
491 {
492 dprintf(CRITICAL, "Crypto send data failed\n");
493 ret_status = CRYPTO_ERR_FAIL;
494 goto CRYPTO_SEND_DATA_ERR;
495 }
496
497 arch_clean_invalidate_cache_range((addr_t) (dev->dump), sizeof(struct output_dump));
498
499 bam_status = ADD_READ_DESC(&dev->bam,
500 (unsigned char *)PA((addr_t)(dev->dump)),
501 sizeof(struct output_dump),
502 BAM_DESC_INT_FLAG);
503
504 if (bam_status)
505 {
506 dprintf(CRITICAL, "Crypto send data failed\n");
507 ret_status = CRYPTO_ERR_FAIL;
508 goto CRYPTO_SEND_DATA_ERR;
509 }
510
511 crypto_wait_for_data(&dev->bam, CRYPTO_WRITE_PIPE_INDEX);
512
513 crypto_wait_for_data(&dev->bam, CRYPTO_READ_PIPE_INDEX);
514
515 arch_clean_invalidate_cache_range((addr_t) (dev->dump), sizeof(struct output_dump));
516
517 ret_status = CRYPTO_ERR_NONE;
518
519CRYPTO_SEND_DATA_ERR:
520
521 return ret_status;
522}
523
524void crypto5_cleanup(struct crypto_dev *dev)
525{
526 CLEAR_STATUS(dev);
527
Deepa Dinamania74fc8d2013-07-29 13:10:01 -0700528 /* reset the pipes. */
529 bam_pipe_reset(&(dev->bam), CRYPTO_READ_PIPE_INDEX);
530 bam_pipe_reset(&(dev->bam), CRYPTO_WRITE_PIPE_INDEX);
531
Deepa Dinamani0a976552012-11-28 17:01:27 -0800532 /* Free all related memory. */
533 free(dev->dump);
534 free(dev->ce_array);
535 free(dev->bam.pipe[CRYPTO_READ_PIPE_INDEX].fifo.head);
536 free(dev->bam.pipe[CRYPTO_WRITE_PIPE_INDEX].fifo.head);
537}
538
539uint32_t crypto5_get_digest(struct crypto_dev *dev,
540 uint8_t *digest_ptr,
541 crypto_auth_alg_type auth_alg)
542{
543 uint32_t ce_status = 0;
544 uint32_t ce_status2 = 0;
545 uint32_t ce_err_bmsk = 0;
546 uint32_t i = 0;
547 uint32_t digest_len = 0;
548 uint32_t auth_iv;
549
550 /* Check status register for errors. */
551 ce_err_bmsk = (AXI_ERR | SW_ERR | HSD_ERR);
552 ce_status = BE32(dev->dump->status);
553
554 /* Check status register for errors. */
555 ce_status2 = BE32(dev->dump->status2);
556
557 if ((ce_status & ce_err_bmsk) || (ce_status2 & AXI_EXTRA))
558 {
559 crypto_reset(dev);
560 dprintf(CRITICAL, "crypto_get_digest status error");
561 dprintf(CRITICAL, "status = %x status2 = %x\n", ce_status, ce_status2);
562 return CRYPTO_ERR_FAIL;
563 }
564
565 /* Digest length depends on auth_alg */
566 if (auth_alg == CRYPTO_AUTH_ALG_SHA1)
567 {
568 digest_len = SHA1_INIT_VECTOR_SIZE;
569 }
570 else if (auth_alg == CRYPTO_AUTH_ALG_SHA256)
571 {
572 digest_len = SHA256_INIT_VECTOR_SIZE;
573 }
574
575 /* Retrieve digest from CRYPTO */
576 for (i = 0; i < digest_len; i++)
577 {
578 auth_iv = (dev->dump->auth_iv[i]);
579
580 *((unsigned int *)digest_ptr + i) = auth_iv;
581 }
582
583 return CRYPTO_ERR_NONE;
584}
585
586void crypto5_get_ctx(struct crypto_dev *dev, void *ctx_ptr)
587{
588 ((crypto_SHA1_ctx *) ctx_ptr)->auth_bytecnt[0] = BE32(dev->dump->auth_bytcnt[0]);
589 ((crypto_SHA1_ctx *) ctx_ptr)->auth_bytecnt[1] = BE32(dev->dump->auth_bytcnt[1]);
590}
591
592uint32_t crypto5_get_max_auth_blk_size(struct crypto_dev *dev)
593{
594 return (dev->bam.max_desc_len * (dev->bam.pipe[CRYPTO_WRITE_PIPE_INDEX].fifo.size - 2));
595}