Terence Hampson | 711a9c2 | 2013-06-18 14:35:43 -0400 | [diff] [blame] | 1 | /* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. |
Deepa Dinamani | 7dc3d4b | 2013-02-08 16:40:38 -0800 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <assert.h> |
| 30 | #include <reg.h> |
| 31 | #include <err.h> |
| 32 | #include <clock.h> |
| 33 | #include <clock_pll.h> |
| 34 | #include <clock_lib2.h> |
| 35 | #include <platform/clock.h> |
| 36 | #include <platform/iomap.h> |
| 37 | |
| 38 | |
| 39 | /* Mux source select values */ |
| 40 | #define cxo_source_val 0 |
| 41 | #define gpll0_source_val 1 |
| 42 | #define cxo_mm_source_val 0 |
| 43 | #define mmpll0_mm_source_val 1 |
| 44 | #define mmpll1_mm_source_val 2 |
| 45 | #define mmpll3_mm_source_val 3 |
| 46 | #define gpll0_mm_source_val 5 |
| 47 | |
| 48 | struct clk_freq_tbl rcg_dummy_freq = F_END; |
| 49 | |
| 50 | |
| 51 | /* Clock Operations */ |
| 52 | static struct clk_ops clk_ops_branch = |
| 53 | { |
| 54 | .enable = clock_lib2_branch_clk_enable, |
| 55 | .disable = clock_lib2_branch_clk_disable, |
| 56 | .set_rate = clock_lib2_branch_set_rate, |
| 57 | }; |
| 58 | |
| 59 | static struct clk_ops clk_ops_rcg_mnd = |
| 60 | { |
| 61 | .enable = clock_lib2_rcg_enable, |
| 62 | .set_rate = clock_lib2_rcg_set_rate, |
| 63 | }; |
| 64 | |
| 65 | static struct clk_ops clk_ops_rcg = |
| 66 | { |
| 67 | .enable = clock_lib2_rcg_enable, |
| 68 | .set_rate = clock_lib2_rcg_set_rate, |
| 69 | }; |
| 70 | |
| 71 | static struct clk_ops clk_ops_cxo = |
| 72 | { |
| 73 | .enable = cxo_clk_enable, |
| 74 | .disable = cxo_clk_disable, |
| 75 | }; |
| 76 | |
| 77 | static struct clk_ops clk_ops_pll_vote = |
| 78 | { |
| 79 | .enable = pll_vote_clk_enable, |
| 80 | .disable = pll_vote_clk_disable, |
| 81 | .auto_off = pll_vote_clk_disable, |
| 82 | .is_enabled = pll_vote_clk_is_enabled, |
| 83 | }; |
| 84 | |
| 85 | static struct clk_ops clk_ops_vote = |
| 86 | { |
| 87 | .enable = clock_lib2_vote_clk_enable, |
| 88 | .disable = clock_lib2_vote_clk_disable, |
| 89 | }; |
| 90 | |
Deepa Dinamani | e1666ac | 2013-03-20 16:19:38 -0700 | [diff] [blame] | 91 | /* Clock Sources */ |
| 92 | static struct fixed_clk cxo_clk_src = |
| 93 | { |
| 94 | .c = { |
| 95 | .rate = 19200000, |
| 96 | .dbg_name = "cxo_clk_src", |
| 97 | .ops = &clk_ops_cxo, |
| 98 | }, |
| 99 | }; |
| 100 | |
| 101 | static struct pll_vote_clk gpll0_clk_src = |
| 102 | { |
| 103 | .en_reg = (void *) APCS_GPLL_ENA_VOTE, |
| 104 | .en_mask = BIT(0), |
| 105 | .status_reg = (void *) GPLL0_STATUS, |
| 106 | .status_mask = BIT(17), |
| 107 | .parent = &cxo_clk_src.c, |
| 108 | |
| 109 | .c = { |
| 110 | .rate = 600000000, |
| 111 | .dbg_name = "gpll0_clk_src", |
| 112 | .ops = &clk_ops_pll_vote, |
| 113 | }, |
| 114 | }; |
| 115 | |
| 116 | /* SDCC Clocks */ |
| 117 | static struct clk_freq_tbl ftbl_gcc_sdcc1_2_apps_clk[] = |
| 118 | { |
| 119 | F( 144000, cxo, 16, 3, 25), |
| 120 | F( 400000, cxo, 12, 1, 4), |
| 121 | F( 20000000, gpll0, 15, 1, 2), |
| 122 | F( 25000000, gpll0, 12, 1, 2), |
| 123 | F( 50000000, gpll0, 12, 0, 0), |
| 124 | F(100000000, gpll0, 6, 0, 0), |
| 125 | F(200000000, gpll0, 3, 0, 0), |
| 126 | F_END |
| 127 | }; |
| 128 | |
| 129 | static struct rcg_clk sdcc1_apps_clk_src = |
| 130 | { |
| 131 | .cmd_reg = (uint32_t *) SDCC1_CMD_RCGR, |
| 132 | .cfg_reg = (uint32_t *) SDCC1_CFG_RCGR, |
| 133 | .m_reg = (uint32_t *) SDCC1_M, |
| 134 | .n_reg = (uint32_t *) SDCC1_N, |
| 135 | .d_reg = (uint32_t *) SDCC1_D, |
| 136 | |
| 137 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 138 | .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk, |
| 139 | .current_freq = &rcg_dummy_freq, |
| 140 | |
| 141 | .c = { |
| 142 | .dbg_name = "sdc1_clk", |
| 143 | .ops = &clk_ops_rcg_mnd, |
| 144 | }, |
| 145 | }; |
| 146 | |
| 147 | static struct branch_clk gcc_sdcc1_apps_clk = |
| 148 | { |
| 149 | .cbcr_reg = (uint32_t *) SDCC1_APPS_CBCR, |
| 150 | .parent = &sdcc1_apps_clk_src.c, |
| 151 | |
| 152 | .c = { |
| 153 | .dbg_name = "gcc_sdcc1_apps_clk", |
| 154 | .ops = &clk_ops_branch, |
| 155 | }, |
| 156 | }; |
| 157 | |
| 158 | static struct branch_clk gcc_sdcc1_ahb_clk = |
| 159 | { |
| 160 | .cbcr_reg = (uint32_t *) SDCC1_AHB_CBCR, |
| 161 | .has_sibling = 1, |
| 162 | |
| 163 | .c = { |
| 164 | .dbg_name = "gcc_sdcc1_ahb_clk", |
| 165 | .ops = &clk_ops_branch, |
| 166 | }, |
| 167 | }; |
| 168 | |
Channagoud Kadabi | 8320800 | 2013-05-09 15:50:45 -0700 | [diff] [blame] | 169 | /* SDCC2 clocks */ |
| 170 | |
| 171 | static struct rcg_clk sdcc2_apps_clk_src = |
| 172 | { |
| 173 | .cmd_reg = (uint32_t *) SDCC2_CMD_RCGR, |
| 174 | .cfg_reg = (uint32_t *) SDCC2_CFG_RCGR, |
| 175 | .m_reg = (uint32_t *) SDCC2_M, |
| 176 | .n_reg = (uint32_t *) SDCC2_N, |
| 177 | .d_reg = (uint32_t *) SDCC2_D, |
| 178 | |
| 179 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 180 | .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk, |
| 181 | .current_freq = &rcg_dummy_freq, |
| 182 | |
| 183 | .c = { |
| 184 | .dbg_name = "sdc2_clk", |
| 185 | .ops = &clk_ops_rcg_mnd, |
| 186 | }, |
| 187 | }; |
| 188 | |
| 189 | static struct branch_clk gcc_sdcc2_apps_clk = |
| 190 | { |
| 191 | .cbcr_reg = (uint32_t *) SDCC2_APPS_CBCR, |
| 192 | .parent = &sdcc2_apps_clk_src.c, |
| 193 | |
| 194 | .c = { |
| 195 | .dbg_name = "gcc_sdcc2_apps_clk", |
| 196 | .ops = &clk_ops_branch, |
| 197 | }, |
| 198 | }; |
| 199 | |
| 200 | static struct branch_clk gcc_sdcc2_ahb_clk = |
| 201 | { |
| 202 | .cbcr_reg = (uint32_t *) SDCC2_AHB_CBCR, |
| 203 | .has_sibling = 1, |
| 204 | |
| 205 | .c = { |
| 206 | .dbg_name = "gcc_sdcc2_ahb_clk", |
| 207 | .ops = &clk_ops_branch, |
| 208 | }, |
| 209 | }; |
| 210 | |
Deepa Dinamani | e1666ac | 2013-03-20 16:19:38 -0700 | [diff] [blame] | 211 | /* UART Clocks */ |
| 212 | static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = |
| 213 | { |
| 214 | F( 3686400, gpll0, 1, 96, 15625), |
| 215 | F( 7372800, gpll0, 1, 192, 15625), |
| 216 | F(14745600, gpll0, 1, 384, 15625), |
| 217 | F(16000000, gpll0, 5, 2, 15), |
| 218 | F(19200000, cxo, 1, 0, 0), |
| 219 | F(24000000, gpll0, 5, 1, 5), |
| 220 | F(32000000, gpll0, 1, 4, 75), |
| 221 | F(40000000, gpll0, 15, 0, 0), |
| 222 | F(46400000, gpll0, 1, 29, 375), |
| 223 | F(48000000, gpll0, 12.5, 0, 0), |
| 224 | F(51200000, gpll0, 1, 32, 375), |
| 225 | F(56000000, gpll0, 1, 7, 75), |
| 226 | F(58982400, gpll0, 1, 1536, 15625), |
| 227 | F(60000000, gpll0, 10, 0, 0), |
| 228 | F_END |
| 229 | }; |
| 230 | |
| 231 | static struct rcg_clk blsp1_uart2_apps_clk_src = |
| 232 | { |
| 233 | .cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR, |
| 234 | .cfg_reg = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR, |
| 235 | .m_reg = (uint32_t *) BLSP1_UART2_APPS_M, |
| 236 | .n_reg = (uint32_t *) BLSP1_UART2_APPS_N, |
| 237 | .d_reg = (uint32_t *) BLSP1_UART2_APPS_D, |
| 238 | |
| 239 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 240 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
| 241 | .current_freq = &rcg_dummy_freq, |
| 242 | |
| 243 | .c = { |
| 244 | .dbg_name = "blsp1_uart2_apps_clk", |
| 245 | .ops = &clk_ops_rcg_mnd, |
| 246 | }, |
| 247 | }; |
| 248 | |
| 249 | static struct branch_clk gcc_blsp1_uart2_apps_clk = |
| 250 | { |
| 251 | .cbcr_reg = (uint32_t *) BLSP1_UART2_APPS_CBCR, |
| 252 | .parent = &blsp1_uart2_apps_clk_src.c, |
| 253 | |
| 254 | .c = { |
| 255 | .dbg_name = "gcc_blsp1_uart2_apps_clk", |
| 256 | .ops = &clk_ops_branch, |
| 257 | }, |
| 258 | }; |
| 259 | |
| 260 | static struct vote_clk gcc_blsp1_ahb_clk = { |
| 261 | .cbcr_reg = (uint32_t *) BLSP1_AHB_CBCR, |
| 262 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 263 | .en_mask = BIT(17), |
| 264 | |
| 265 | .c = { |
| 266 | .dbg_name = "gcc_blsp1_ahb_clk", |
| 267 | .ops = &clk_ops_vote, |
| 268 | }, |
| 269 | }; |
| 270 | |
| 271 | /* USB Clocks */ |
| 272 | static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = |
| 273 | { |
| 274 | F(75000000, gpll0, 8, 0, 0), |
| 275 | F_END |
| 276 | }; |
| 277 | |
| 278 | static struct rcg_clk usb_hs_system_clk_src = |
| 279 | { |
| 280 | .cmd_reg = (uint32_t *) USB_HS_SYSTEM_CMD_RCGR, |
| 281 | .cfg_reg = (uint32_t *) USB_HS_SYSTEM_CFG_RCGR, |
| 282 | |
| 283 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 284 | .freq_tbl = ftbl_gcc_usb_hs_system_clk, |
| 285 | .current_freq = &rcg_dummy_freq, |
| 286 | |
| 287 | .c = { |
| 288 | .dbg_name = "usb_hs_system_clk", |
| 289 | .ops = &clk_ops_rcg, |
| 290 | }, |
| 291 | }; |
| 292 | |
| 293 | static struct branch_clk gcc_usb_hs_system_clk = |
| 294 | { |
| 295 | .cbcr_reg = (uint32_t *) USB_HS_SYSTEM_CBCR, |
| 296 | .parent = &usb_hs_system_clk_src.c, |
| 297 | |
| 298 | .c = { |
| 299 | .dbg_name = "gcc_usb_hs_system_clk", |
| 300 | .ops = &clk_ops_branch, |
| 301 | }, |
| 302 | }; |
| 303 | |
| 304 | static struct branch_clk gcc_usb_hs_ahb_clk = |
| 305 | { |
| 306 | .cbcr_reg = (uint32_t *) USB_HS_AHB_CBCR, |
| 307 | .has_sibling = 1, |
| 308 | |
| 309 | .c = { |
| 310 | .dbg_name = "gcc_usb_hs_ahb_clk", |
| 311 | .ops = &clk_ops_branch, |
| 312 | }, |
| 313 | }; |
| 314 | |
Terence Hampson | 711a9c2 | 2013-06-18 14:35:43 -0400 | [diff] [blame] | 315 | /* Diplay related clock LUT */ |
| 316 | static struct clk_freq_tbl ftbl_mmss_axi_clk[] = { |
| 317 | F_MM(19200000, cxo, 1, 0, 0), |
| 318 | F_MM(100000000, gpll0, 6, 0, 0), |
Terence Hampson | fc832c1 | 2013-08-21 16:21:39 -0400 | [diff] [blame] | 319 | F_MM(200000000, gpll0, 3, 0, 0), |
Terence Hampson | 711a9c2 | 2013-06-18 14:35:43 -0400 | [diff] [blame] | 320 | F_END |
| 321 | }; |
| 322 | |
| 323 | static struct clk_freq_tbl ftbl_mdss_vsync_clk[] = { |
| 324 | F_MM(19200000, cxo, 1, 0, 0), |
| 325 | F_END |
| 326 | }; |
| 327 | |
| 328 | static struct rcg_clk vsync_clk_src = { |
| 329 | .cmd_reg = (uint32_t *) VSYNC_CMD_RCGR, |
| 330 | .cfg_reg = (uint32_t *) VSYNC_CFG_RCGR, |
| 331 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 332 | .freq_tbl = ftbl_mdss_vsync_clk, |
| 333 | .c = { |
| 334 | .dbg_name = "vsync_clk_src", |
| 335 | .ops = &clk_ops_rcg, |
| 336 | }, |
| 337 | }; |
| 338 | |
| 339 | static struct rcg_clk axi_clk_src = { |
| 340 | .cmd_reg = (uint32_t *) AXI_CMD_RCGR, |
| 341 | .cfg_reg = (uint32_t *) AXI_CFG_RCGR, |
| 342 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 343 | .freq_tbl = ftbl_mmss_axi_clk, |
| 344 | .c = { |
| 345 | .dbg_name = "axi_clk_src", |
| 346 | .ops = &clk_ops_rcg, |
| 347 | }, |
| 348 | }; |
| 349 | |
| 350 | static struct branch_clk mdp_ahb_clk = { |
| 351 | .cbcr_reg = (uint32_t *) MDP_AHB_CBCR, |
| 352 | .has_sibling = 1, |
| 353 | .c = { |
| 354 | .dbg_name = "mdp_ahb_clk", |
| 355 | .ops = &clk_ops_branch, |
| 356 | }, |
| 357 | }; |
| 358 | |
| 359 | static struct branch_clk mdp_axi_clk = { |
| 360 | .cbcr_reg = (uint32_t *) MDP_AXI_CBCR, |
| 361 | .parent = &axi_clk_src.c, |
| 362 | .c = { |
| 363 | .dbg_name = "mdp_axi_clk", |
| 364 | .ops = &clk_ops_branch, |
| 365 | }, |
| 366 | }; |
| 367 | |
| 368 | static struct branch_clk mdp_dsi_clk = { |
| 369 | .cbcr_reg = (uint32_t *) MDP_DSI_CBCR, |
| 370 | .c = { |
| 371 | .dbg_name = "mdp_dsi_clk", |
| 372 | .ops = &clk_ops_branch, |
| 373 | }, |
| 374 | }; |
| 375 | |
| 376 | static struct branch_clk mmss_mmssnoc_axi_clk = { |
| 377 | .cbcr_reg = (uint32_t *) MMSS_MMSSNOC_AXI_CBCR, |
| 378 | .parent = &axi_clk_src.c, |
| 379 | .c = { |
| 380 | .dbg_name = "mmss_mmssnoc_axi_clk", |
| 381 | .ops = &clk_ops_branch, |
| 382 | }, |
| 383 | }; |
| 384 | |
| 385 | static struct branch_clk mmss_s0_axi_clk = { |
| 386 | .cbcr_reg = (uint32_t *) MMSS_S0_AXI_CBCR, |
| 387 | .parent = &axi_clk_src.c, |
| 388 | .c = { |
| 389 | .dbg_name = "mmss_s0_axi_clk", |
| 390 | .ops = &clk_ops_branch, |
| 391 | }, |
| 392 | }; |
| 393 | |
| 394 | static struct branch_clk mdp_vsync_clk = { |
| 395 | .cbcr_reg = MDP_VSYNC_CBCR, |
| 396 | .parent = &vsync_clk_src.c, |
| 397 | .c = { |
| 398 | .dbg_name = "mdp_vsync_clk", |
| 399 | .ops = &clk_ops_branch, |
| 400 | }, |
| 401 | }; |
| 402 | |
| 403 | static struct branch_clk mdp_lcdc_clk = { |
| 404 | .cbcr_reg = MDP_LCDC_CBCR, |
| 405 | .parent = &axi_clk_src.c, |
| 406 | .c = { |
| 407 | .dbg_name = "mdp_lcdc_clk", |
| 408 | .ops = &clk_ops_branch, |
| 409 | }, |
| 410 | }; |
| 411 | |
| 412 | static struct branch_clk dsi_clk = { |
| 413 | .cbcr_reg = DSI_CBCR, |
| 414 | .c = { |
| 415 | .dbg_name = "dsi_clk", |
| 416 | .ops = &clk_ops_branch, |
| 417 | }, |
| 418 | }; |
| 419 | |
| 420 | static struct branch_clk dsi_ahb_clk = { |
| 421 | .cbcr_reg = DSI_AHB_CBCR, |
| 422 | .has_sibling = 1, |
| 423 | .c = { |
| 424 | .dbg_name = "dsi_ahb_clk", |
| 425 | .ops = &clk_ops_branch, |
| 426 | }, |
| 427 | }; |
| 428 | |
| 429 | static struct branch_clk dsi_byte_clk = { |
| 430 | .cbcr_reg = DSI_BYTE_CBCR, |
| 431 | .c = { |
| 432 | .dbg_name = "dsi_byte_clk", |
| 433 | .ops = &clk_ops_branch, |
| 434 | }, |
| 435 | }; |
| 436 | |
| 437 | static struct branch_clk dsi_esc_clk = { |
| 438 | .cbcr_reg = DSI_ESC_CBCR, |
| 439 | .c = { |
| 440 | .dbg_name = "dsi_esc_clk", |
| 441 | .ops = &clk_ops_branch, |
| 442 | }, |
| 443 | }; |
| 444 | |
| 445 | static struct branch_clk dsi_pclk_clk = { |
| 446 | .cbcr_reg = DSI_PCLK_CBCR, |
| 447 | .c = { |
| 448 | .dbg_name = "dsi_pclk_clk", |
| 449 | .ops = &clk_ops_branch, |
| 450 | }, |
| 451 | }; |
| 452 | |
Amol Jadi | f213901 | 2013-08-23 18:44:10 -0700 | [diff] [blame] | 453 | static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = { |
| 454 | F( 50000000, gpll0, 12, 0, 0), |
| 455 | F(100000000, gpll0, 6, 0, 0), |
| 456 | F_END |
| 457 | }; |
| 458 | |
| 459 | static struct rcg_clk ce1_clk_src = { |
| 460 | .cmd_reg = (uint32_t *) GCC_CE1_CMD_RCGR, |
| 461 | .cfg_reg = (uint32_t *) GCC_CE1_CFG_RCGR, |
| 462 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 463 | .freq_tbl = ftbl_gcc_ce1_clk, |
| 464 | .current_freq = &rcg_dummy_freq, |
| 465 | |
| 466 | .c = { |
| 467 | .dbg_name = "ce1_clk_src", |
| 468 | .ops = &clk_ops_rcg, |
| 469 | }, |
| 470 | }; |
| 471 | |
| 472 | static struct vote_clk gcc_ce1_clk = { |
| 473 | .cbcr_reg = (uint32_t *) GCC_CE1_CBCR, |
| 474 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 475 | .en_mask = BIT(5), |
| 476 | |
| 477 | .c = { |
| 478 | .dbg_name = "gcc_ce1_clk", |
| 479 | .ops = &clk_ops_vote, |
| 480 | }, |
| 481 | }; |
| 482 | |
| 483 | static struct vote_clk gcc_ce1_ahb_clk = { |
| 484 | .cbcr_reg = (uint32_t *) GCC_CE1_AHB_CBCR, |
| 485 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 486 | .en_mask = BIT(3), |
| 487 | |
| 488 | .c = { |
| 489 | .dbg_name = "gcc_ce1_ahb_clk", |
| 490 | .ops = &clk_ops_vote, |
| 491 | }, |
| 492 | }; |
| 493 | |
| 494 | static struct vote_clk gcc_ce1_axi_clk = { |
| 495 | .cbcr_reg = (uint32_t *) GCC_CE1_AXI_CBCR, |
| 496 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 497 | .en_mask = BIT(4), |
| 498 | |
| 499 | .c = { |
| 500 | .dbg_name = "gcc_ce1_axi_clk", |
| 501 | .ops = &clk_ops_vote, |
| 502 | }, |
| 503 | }; |
| 504 | |
Deepa Dinamani | 7dc3d4b | 2013-02-08 16:40:38 -0800 | [diff] [blame] | 505 | /* Clock lookup table */ |
| 506 | static struct clk_lookup msm_clocks_8610[] = |
| 507 | { |
Deepa Dinamani | e1666ac | 2013-03-20 16:19:38 -0700 | [diff] [blame] | 508 | CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c), |
| 509 | CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c), |
| 510 | |
Channagoud Kadabi | 8320800 | 2013-05-09 15:50:45 -0700 | [diff] [blame] | 511 | CLK_LOOKUP("sdc2_iface_clk", gcc_sdcc2_ahb_clk.c), |
| 512 | CLK_LOOKUP("sdc2_core_clk", gcc_sdcc2_apps_clk.c), |
| 513 | |
Deepa Dinamani | e1666ac | 2013-03-20 16:19:38 -0700 | [diff] [blame] | 514 | CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c), |
| 515 | CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c), |
| 516 | |
| 517 | CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c), |
| 518 | CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c), |
Terence Hampson | 711a9c2 | 2013-06-18 14:35:43 -0400 | [diff] [blame] | 519 | |
| 520 | CLK_LOOKUP("axi_clk_src", axi_clk_src.c), |
| 521 | CLK_LOOKUP("mmss_mmssnoc_axi_clk", mmss_mmssnoc_axi_clk.c), |
| 522 | CLK_LOOKUP("mmss_s0_axi_clk", mmss_s0_axi_clk.c), |
| 523 | CLK_LOOKUP("mdp_axi_clk", mdp_axi_clk.c), |
| 524 | CLK_LOOKUP("mdp_dsi_clk", mdp_dsi_clk.c), |
| 525 | CLK_LOOKUP("mdp_vsync_clk", mdp_vsync_clk.c), |
| 526 | CLK_LOOKUP("mdp_lcdc_clk", mdp_lcdc_clk.c), |
| 527 | CLK_LOOKUP("mdp_ahb_clk", mdp_ahb_clk.c), |
| 528 | |
| 529 | CLK_LOOKUP("dsi_clk", dsi_clk.c), |
| 530 | CLK_LOOKUP("dsi_ahb_clk", dsi_ahb_clk.c), |
| 531 | CLK_LOOKUP("dsi_byte_clk", dsi_byte_clk.c), |
| 532 | CLK_LOOKUP("dsi_esc_clk", dsi_esc_clk.c), |
| 533 | CLK_LOOKUP("dsi_pclk_clk", dsi_pclk_clk.c), |
Amol Jadi | f213901 | 2013-08-23 18:44:10 -0700 | [diff] [blame] | 534 | |
| 535 | CLK_LOOKUP("ce1_ahb_clk", gcc_ce1_ahb_clk.c), |
| 536 | CLK_LOOKUP("ce1_axi_clk", gcc_ce1_axi_clk.c), |
| 537 | CLK_LOOKUP("ce1_core_clk", gcc_ce1_clk.c), |
| 538 | CLK_LOOKUP("ce1_src_clk", ce1_clk_src.c), |
Deepa Dinamani | 7dc3d4b | 2013-02-08 16:40:38 -0800 | [diff] [blame] | 539 | }; |
| 540 | |
| 541 | void platform_clock_init(void) |
| 542 | { |
| 543 | clk_init(msm_clocks_8610, ARRAY_SIZE(msm_clocks_8610)); |
| 544 | } |