Ujwal Patel | 42c4cae | 2013-12-18 20:40:38 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are met: |
| 5 | * * Redistributions of source code must retain the above copyright |
| 6 | * notice, this list of conditions and the following disclaimer. |
| 7 | * * Redistributions in binary form must reproduce the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer in the |
| 9 | * documentation and/or other materials provided with the distribution. |
| 10 | * * Neither the name of The Linux Foundation nor |
| 11 | * the names of its contributors may be used to endorse or promote |
| 12 | * products derived from this software without specific prior written |
| 13 | * permission. |
| 14 | * |
| 15 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 16 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 17 | * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 18 | * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 19 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 20 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 21 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; |
| 22 | * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 23 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR |
| 24 | * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF |
| 25 | * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 26 | */ |
| 27 | |
| 28 | #include <mdp5.h> |
| 29 | #include <debug.h> |
| 30 | #include <reg.h> |
| 31 | #include <target/display.h> |
| 32 | #include <platform/timer.h> |
| 33 | #include <platform/iomap.h> |
| 34 | #include <dev/lcdc.h> |
| 35 | #include <dev/fbcon.h> |
| 36 | #include <bits.h> |
| 37 | #include <msm_panel.h> |
| 38 | #include <mipi_dsi.h> |
| 39 | #include <err.h> |
| 40 | #include <clock.h> |
Siddhartha Agrawal | 8d69082 | 2013-01-28 12:18:58 -0800 | [diff] [blame] | 41 | #include <scm.h> |
| 42 | |
| 43 | int restore_secure_cfg(uint32_t id); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 44 | |
| 45 | static int mdp_rev; |
| 46 | |
| 47 | void mdp_set_revision(int rev) |
| 48 | { |
| 49 | mdp_rev = rev; |
| 50 | } |
| 51 | |
| 52 | int mdp_get_revision() |
| 53 | { |
| 54 | return mdp_rev; |
| 55 | } |
| 56 | |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 57 | uint32_t mdss_mdp_intf_offset() |
| 58 | { |
| 59 | uint32_t mdss_mdp_intf_off; |
| 60 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 61 | |
Chandan Uddaraju | aab5851 | 2013-06-25 17:47:39 -0700 | [diff] [blame] | 62 | if (mdss_mdp_rev >= MDSS_MDP_HW_REV_102) |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 63 | mdss_mdp_intf_off = 0; |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 64 | else |
Chandan Uddaraju | aab5851 | 2013-06-25 17:47:39 -0700 | [diff] [blame] | 65 | mdss_mdp_intf_off = 0xEC00; |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 66 | |
| 67 | return mdss_mdp_intf_off; |
| 68 | } |
| 69 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 70 | void mdp_clk_gating_ctrl(void) |
| 71 | { |
| 72 | writel(0x40000000, MDP_CLK_CTRL0); |
| 73 | udelay(20); |
| 74 | writel(0x40000040, MDP_CLK_CTRL0); |
| 75 | writel(0x40000000, MDP_CLK_CTRL1); |
| 76 | writel(0x00400000, MDP_CLK_CTRL3); |
| 77 | udelay(20); |
| 78 | writel(0x00404000, MDP_CLK_CTRL3); |
| 79 | writel(0x40000000, MDP_CLK_CTRL4); |
| 80 | } |
| 81 | |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 82 | static void mdss_rgb_pipe_config(struct fbcon_config *fb, struct msm_panel_info |
| 83 | *pinfo, uint32_t pipe_base) |
| 84 | { |
| 85 | uint32_t src_size, out_size, stride; |
Siddhartha Agrawal | 6ef1e22 | 2013-06-12 18:24:58 -0700 | [diff] [blame] | 86 | uint32_t fb_off = 0; |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 87 | |
| 88 | /* write active region size*/ |
| 89 | src_size = (fb->height << 16) + fb->width; |
| 90 | out_size = src_size; |
| 91 | |
| 92 | if (pinfo->lcdc.dual_pipe) { |
| 93 | out_size = (fb->height << 16) + (fb->width / 2); |
Siddhartha Agrawal | 6ef1e22 | 2013-06-12 18:24:58 -0700 | [diff] [blame] | 94 | if ((pinfo->lcdc.pipe_swap == TRUE) && (pipe_base == |
| 95 | MDP_VP_0_RGB_0_BASE)) |
| 96 | fb_off = (pinfo->xres / 2); |
| 97 | else if ((pinfo->lcdc.pipe_swap != TRUE) && (pipe_base == |
| 98 | MDP_VP_0_RGB_1_BASE)) |
| 99 | fb_off = (pinfo->xres / 2); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 100 | } |
| 101 | |
| 102 | stride = (fb->stride * fb->bpp/8); |
| 103 | |
| 104 | writel(fb->base, pipe_base + PIPE_SSPP_SRC0_ADDR); |
| 105 | writel(stride, pipe_base + PIPE_SSPP_SRC_YSTRIDE); |
| 106 | writel(src_size, pipe_base + PIPE_SSPP_SRC_IMG_SIZE); |
| 107 | writel(out_size, pipe_base + PIPE_SSPP_SRC_SIZE); |
| 108 | writel(out_size, pipe_base + PIPE_SSPP_SRC_OUT_SIZE); |
Siddhartha Agrawal | 6ef1e22 | 2013-06-12 18:24:58 -0700 | [diff] [blame] | 109 | writel(fb_off, pipe_base + PIPE_SSPP_SRC_XY); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 110 | writel(0x00, pipe_base + PIPE_SSPP_OUT_XY); |
| 111 | |
| 112 | /* Tight Packing 3bpp 0-Alpha 8-bit R B G */ |
| 113 | writel(0x0002243F, pipe_base + PIPE_SSPP_SRC_FORMAT); |
| 114 | writel(0x00020001, pipe_base + PIPE_SSPP_SRC_UNPACK_PATTERN); |
| 115 | writel(0x00, pipe_base + PIPE_SSPP_SRC_OP_MODE); |
| 116 | } |
| 117 | |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 118 | static void mdss_vbif_setup() |
| 119 | { |
| 120 | int access_secure = restore_secure_cfg(SECURE_DEVICE_MDSS); |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 121 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 122 | |
| 123 | /* TZ returns an errornous ret val even if the VBIF registers were |
| 124 | * successfully unlocked. Ignore TZ return value till it's fixed */ |
| 125 | if (!access_secure || 1) { |
| 126 | dprintf(SPEW, "MDSS VBIF registers unlocked by TZ.\n"); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 127 | |
Ujwal Patel | 42c4cae | 2013-12-18 20:40:38 -0800 | [diff] [blame] | 128 | /* Force VBIF Clocks on */ |
| 129 | if (mdp_hw_rev < MDSS_MDP_HW_REV_103) |
| 130 | writel(0x1, VBIF_VBIF_DDR_FORCE_CLK_ON); |
| 131 | |
| 132 | /* |
| 133 | * Following configuration is needed because on some versions, |
| 134 | * recommended reset values are not stored. |
| 135 | */ |
| 136 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 137 | MDSS_MDP_HW_REV_100)) { |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 138 | writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST); |
| 139 | writel(0x00000030, VBIF_VBIF_DDR_ARB_CTRL ); |
| 140 | writel(0x00000001, VBIF_VBIF_DDR_RND_RBN_QOS_ARB); |
| 141 | writel(0x00000FFF, VBIF_VBIF_DDR_OUT_AOOO_AXI_EN); |
| 142 | writel(0x0FFF0FFF, VBIF_VBIF_DDR_OUT_AX_AOOO); |
| 143 | writel(0x22222222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0); |
| 144 | writel(0x00002222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1); |
Ujwal Patel | 42c4cae | 2013-12-18 20:40:38 -0800 | [diff] [blame] | 145 | } else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 146 | MDSS_MDP_HW_REV_101)) { |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 147 | writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST); |
| 148 | writel(0x00000003, VBIF_VBIF_DDR_ARB_CTRL); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 149 | } |
| 150 | } |
| 151 | } |
| 152 | |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 153 | void mdss_smp_setup(struct msm_panel_info *pinfo) |
| 154 | { |
| 155 | uint32_t smp_cnt = 0, reg_rgb0 = 0, reg_rgb1 = 0, shift = 0; |
| 156 | uint32_t xres, bpp; |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 157 | uint32_t rgb0_client_id = MMSS_MDP_CLIENT_ID_UNUSED; |
| 158 | uint32_t rgb1_client_id = MMSS_MDP_1_2_CLIENT_ID_RGB1; |
| 159 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 160 | |
| 161 | xres = pinfo->xres; |
| 162 | bpp = pinfo->bpp; |
| 163 | |
Chandan Uddaraju | aab5851 | 2013-06-25 17:47:39 -0700 | [diff] [blame] | 164 | if (mdss_mdp_rev == MDSS_MDP_HW_REV_100 |
| 165 | || mdss_mdp_rev >= MDSS_MDP_HW_REV_102) |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 166 | rgb0_client_id = MMSS_MDP_1_2_CLIENT_ID_RGB0; |
Chandan Uddaraju | aab5851 | 2013-06-25 17:47:39 -0700 | [diff] [blame] | 167 | else if (mdss_mdp_rev >= MDSS_MDP_HW_REV_101) |
| 168 | rgb0_client_id = MMSS_MDP_1_1_CLIENT_ID_RGB0; |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 169 | |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 170 | if (pinfo->lcdc.dual_pipe) { |
| 171 | /* Each pipe driving half the screen */ |
| 172 | xres /= 2; |
| 173 | } |
| 174 | |
| 175 | smp_cnt = ((xres) * (bpp / 8) * 2) + |
| 176 | MMSS_MDP_MAX_SMP_SIZE - 1; |
| 177 | |
| 178 | smp_cnt /= MMSS_MDP_MAX_SMP_SIZE; |
| 179 | |
| 180 | if (smp_cnt > 4) { |
| 181 | dprintf(CRITICAL, "ERROR: %s: Out of SMP's, cnt=%d! \n", __func__, |
| 182 | smp_cnt); |
| 183 | ASSERT(0); /* Max 4 SMPs can be allocated per client */ |
| 184 | } |
| 185 | |
Dhaval Patel | 58dac45 | 2013-10-18 18:58:09 -0700 | [diff] [blame] | 186 | writel(smp_cnt * 0x40, MDP_VP_0_RGB_0_BASE + REQPRIORITY_FIFO_WATERMARK0); |
| 187 | writel(smp_cnt * 0x80, MDP_VP_0_RGB_0_BASE + REQPRIORITY_FIFO_WATERMARK1); |
| 188 | writel(smp_cnt * 0xc0, MDP_VP_0_RGB_0_BASE + REQPRIORITY_FIFO_WATERMARK2); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 189 | |
| 190 | if (pinfo->lcdc.dual_pipe) { |
Dhaval Patel | 58dac45 | 2013-10-18 18:58:09 -0700 | [diff] [blame] | 191 | writel(smp_cnt * 0x40, MDP_VP_0_RGB_1_BASE + REQPRIORITY_FIFO_WATERMARK0); |
| 192 | writel(smp_cnt * 0x80, MDP_VP_0_RGB_1_BASE + REQPRIORITY_FIFO_WATERMARK1); |
| 193 | writel(smp_cnt * 0xc0, MDP_VP_0_RGB_1_BASE + REQPRIORITY_FIFO_WATERMARK2); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 194 | } |
| 195 | |
| 196 | while((smp_cnt > 0) && !(shift > 16)) { |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 197 | reg_rgb0 |= ((rgb0_client_id) << (shift)); |
| 198 | reg_rgb1 |= ((rgb1_client_id) << (shift)); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 199 | smp_cnt--; |
| 200 | shift += 8; |
| 201 | } |
| 202 | |
| 203 | /* Allocate SMP blocks */ |
| 204 | writel(reg_rgb0, MMSS_MDP_SMP_ALLOC_W_0); |
| 205 | writel(reg_rgb0, MMSS_MDP_SMP_ALLOC_R_0); |
| 206 | |
| 207 | if (pinfo->lcdc.dual_pipe) { |
| 208 | writel(reg_rgb1, MMSS_MDP_SMP_ALLOC_W_1); |
| 209 | writel(reg_rgb1, MMSS_MDP_SMP_ALLOC_R_1); |
| 210 | } |
| 211 | } |
| 212 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 213 | void mdss_intf_tg_setup(struct msm_panel_info *pinfo, uint32_t intf_base) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 214 | { |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 215 | uint32_t hsync_period, vsync_period; |
| 216 | uint32_t hsync_start_x, hsync_end_x; |
| 217 | uint32_t display_hctl, active_hctl, hsync_ctl, display_vstart, display_vend; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 218 | uint32_t mdss_mdp_intf_off; |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 219 | uint32_t adjust_xres = 0; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 220 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 221 | struct lcdc_panel_info *lcdc = NULL; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 222 | |
| 223 | if (pinfo == NULL) |
| 224 | return ERR_INVALID_ARGS; |
| 225 | |
| 226 | lcdc = &(pinfo->lcdc); |
| 227 | if (lcdc == NULL) |
| 228 | return ERR_INVALID_ARGS; |
| 229 | |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 230 | adjust_xres = pinfo->xres; |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 231 | if (pinfo->lcdc.split_display) { |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 232 | adjust_xres /= 2; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 233 | if (intf_base == MDP_INTF_1_BASE) { |
Dhaval Patel | cbdfdf8 | 2014-01-03 17:33:39 -0800 | [diff] [blame^] | 234 | writel(BIT(8), MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 235 | writel(0x0, MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL); |
| 236 | writel(0x1, MDP_REG_SPLIT_DISPLAY_EN); |
| 237 | } |
| 238 | } |
| 239 | |
| 240 | mdss_mdp_intf_off = intf_base + mdss_mdp_intf_offset(); |
| 241 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 242 | hsync_period = lcdc->h_pulse_width + |
| 243 | lcdc->h_back_porch + |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 244 | adjust_xres + lcdc->xres_pad + lcdc->h_front_porch; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 245 | vsync_period = (lcdc->v_pulse_width + |
| 246 | lcdc->v_back_porch + |
| 247 | pinfo->yres + lcdc->yres_pad + |
| 248 | lcdc->v_front_porch); |
| 249 | |
| 250 | hsync_start_x = |
| 251 | lcdc->h_pulse_width + |
| 252 | lcdc->h_back_porch; |
| 253 | hsync_end_x = |
| 254 | hsync_period - lcdc->h_front_porch - 1; |
| 255 | |
| 256 | display_vstart = (lcdc->v_pulse_width + |
| 257 | lcdc->v_back_porch) |
| 258 | * hsync_period + lcdc->hsync_skew; |
| 259 | display_vend = ((vsync_period - lcdc->v_front_porch) * hsync_period) |
| 260 | +lcdc->hsync_skew - 1; |
| 261 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 262 | if (intf_base == MDP_INTF_0_BASE) { /* eDP */ |
| 263 | display_vstart += lcdc->h_pulse_width + lcdc->h_back_porch; |
| 264 | display_vend -= lcdc->h_front_porch; |
| 265 | } |
| 266 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 267 | hsync_ctl = (hsync_period << 16) | lcdc->h_pulse_width; |
| 268 | display_hctl = (hsync_end_x << 16) | hsync_start_x; |
| 269 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 270 | writel(hsync_ctl, MDP_HSYNC_CTL + mdss_mdp_intf_off); |
| 271 | writel(vsync_period*hsync_period, MDP_VSYNC_PERIOD_F0 + |
| 272 | mdss_mdp_intf_off); |
| 273 | writel(0x00, MDP_VSYNC_PERIOD_F1 + mdss_mdp_intf_off); |
| 274 | writel(lcdc->v_pulse_width*hsync_period, |
| 275 | MDP_VSYNC_PULSE_WIDTH_F0 + |
| 276 | mdss_mdp_intf_off); |
| 277 | writel(0x00, MDP_VSYNC_PULSE_WIDTH_F1 + mdss_mdp_intf_off); |
| 278 | writel(display_hctl, MDP_DISPLAY_HCTL + mdss_mdp_intf_off); |
| 279 | writel(display_vstart, MDP_DISPLAY_V_START_F0 + |
| 280 | mdss_mdp_intf_off); |
| 281 | writel(0x00, MDP_DISPLAY_V_START_F1 + mdss_mdp_intf_off); |
| 282 | writel(display_vend, MDP_DISPLAY_V_END_F0 + |
| 283 | mdss_mdp_intf_off); |
| 284 | writel(0x00, MDP_DISPLAY_V_END_F1 + mdss_mdp_intf_off); |
| 285 | writel(0x00, MDP_ACTIVE_HCTL + mdss_mdp_intf_off); |
| 286 | writel(0x00, MDP_ACTIVE_V_START_F0 + mdss_mdp_intf_off); |
| 287 | writel(0x00, MDP_ACTIVE_V_START_F1 + mdss_mdp_intf_off); |
| 288 | writel(0x00, MDP_ACTIVE_V_END_F0 + mdss_mdp_intf_off); |
| 289 | writel(0x00, MDP_ACTIVE_V_END_F1 + mdss_mdp_intf_off); |
| 290 | writel(0xFF, MDP_UNDERFFLOW_COLOR + mdss_mdp_intf_off); |
| 291 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 292 | if (intf_base == MDP_INTF_0_BASE) /* eDP */ |
| 293 | writel(0x212A, MDP_PANEL_FORMAT + mdss_mdp_intf_off); |
| 294 | else |
| 295 | writel(0x213F, MDP_PANEL_FORMAT + mdss_mdp_intf_off); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 296 | } |
| 297 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 298 | void mdss_layer_mixer_setup(struct fbcon_config *fb, struct msm_panel_info |
| 299 | *pinfo) |
| 300 | { |
| 301 | uint32_t mdp_rgb_size, height, width; |
| 302 | |
Dhaval Patel | 0386811 | 2013-10-25 10:25:06 -0700 | [diff] [blame] | 303 | height = fb->height; |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 304 | width = fb->width; |
| 305 | |
| 306 | if (pinfo->lcdc.dual_pipe) |
| 307 | width /= 2; |
| 308 | |
| 309 | /* write active region size*/ |
| 310 | mdp_rgb_size = (height << 16) | width; |
| 311 | |
| 312 | writel(mdp_rgb_size, MDP_VP_0_MIXER_0_BASE + LAYER_0_OUT_SIZE); |
| 313 | writel(0x00, MDP_VP_0_MIXER_0_BASE + LAYER_0_OP_MODE); |
| 314 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_0_BLEND_OP); |
| 315 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_0_BLEND0_FG_ALPHA); |
| 316 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_1_BLEND_OP); |
| 317 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_1_BLEND0_FG_ALPHA); |
| 318 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_2_BLEND_OP); |
| 319 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_2_BLEND0_FG_ALPHA); |
| 320 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_3_BLEND_OP); |
| 321 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_3_BLEND0_FG_ALPHA); |
| 322 | |
| 323 | /* Baselayer for layer mixer 0 */ |
| 324 | writel(0x0000200, MDP_CTL_0_BASE + CTL_LAYER_0); |
| 325 | |
| 326 | if (pinfo->lcdc.dual_pipe) { |
| 327 | writel(mdp_rgb_size, MDP_VP_0_MIXER_1_BASE + LAYER_0_OUT_SIZE); |
| 328 | writel(0x00, MDP_VP_0_MIXER_1_BASE + LAYER_0_OP_MODE); |
| 329 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_0_BLEND_OP); |
| 330 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_0_BLEND0_FG_ALPHA); |
| 331 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_1_BLEND_OP); |
| 332 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_1_BLEND0_FG_ALPHA); |
| 333 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_2_BLEND_OP); |
| 334 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_2_BLEND0_FG_ALPHA); |
| 335 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND_OP); |
| 336 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND0_FG_ALPHA); |
| 337 | |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 338 | /* Baselayer for layer mixer 1 */ |
| 339 | if (pinfo->lcdc.split_display) |
Dhaval Patel | 0386811 | 2013-10-25 10:25:06 -0700 | [diff] [blame] | 340 | writel(0x1000, MDP_CTL_1_BASE + CTL_LAYER_1); |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 341 | else |
| 342 | writel(0x01000, MDP_CTL_0_BASE + CTL_LAYER_1); |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 343 | } |
| 344 | } |
| 345 | |
Dhaval Patel | d6c54b5 | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 346 | void mdss_qos_remapper_setup(void) |
| 347 | { |
| 348 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
| 349 | uint32_t map; |
| 350 | |
| 351 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_100) || |
| 352 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 353 | MDSS_MDP_HW_REV_102)) |
| 354 | map = 0xE9; |
| 355 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 356 | MDSS_MDP_HW_REV_101)) |
| 357 | map = 0xA5; |
| 358 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 359 | MDSS_MDP_HW_REV_103)) |
| 360 | map = 0xFA; |
| 361 | else |
| 362 | return; |
| 363 | |
| 364 | writel(map, MDP_QOS_REMAPPER_CLASS_0); |
| 365 | } |
| 366 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 367 | int mdp_dsi_video_config(struct msm_panel_info *pinfo, |
| 368 | struct fbcon_config *fb) |
| 369 | { |
| 370 | int ret = NO_ERROR; |
| 371 | struct lcdc_panel_info *lcdc = NULL; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 372 | uint32_t intf_sel = 0x100; |
| 373 | |
| 374 | mdss_intf_tg_setup(pinfo, MDP_INTF_1_BASE); |
| 375 | |
| 376 | if (pinfo->mipi.dual_dsi) |
| 377 | mdss_intf_tg_setup(pinfo, MDP_INTF_2_BASE); |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 378 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 379 | mdp_clk_gating_ctrl(); |
| 380 | |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 381 | mdss_vbif_setup(); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 382 | mdss_smp_setup(pinfo); |
Siddhartha Agrawal | b1b5a1f | 2013-04-17 19:53:41 -0700 | [diff] [blame] | 383 | |
Dhaval Patel | d6c54b5 | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 384 | mdss_qos_remapper_setup(); |
Siddhartha Agrawal | b1b5a1f | 2013-04-17 19:53:41 -0700 | [diff] [blame] | 385 | |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 386 | mdss_rgb_pipe_config(fb, pinfo, MDP_VP_0_RGB_0_BASE); |
| 387 | if (pinfo->lcdc.dual_pipe) |
| 388 | mdss_rgb_pipe_config(fb, pinfo, MDP_VP_0_RGB_1_BASE); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 389 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 390 | mdss_layer_mixer_setup(fb, pinfo); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 391 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 392 | writel(0x1F20, MDP_CTL_0_BASE + CTL_TOP); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 393 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 394 | if (pinfo->mipi.dual_dsi) { |
| 395 | writel(0x1F30, MDP_CTL_1_BASE + CTL_TOP); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 396 | intf_sel |= BIT(16); /* INTF 2 enable */ |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 397 | } |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 398 | |
| 399 | writel(intf_sel, MDP_DISP_INTF_SEL); |
| 400 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 401 | writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); |
| 402 | writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); |
| 403 | writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); |
| 404 | |
| 405 | return 0; |
| 406 | } |
| 407 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 408 | int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb) |
| 409 | { |
| 410 | int ret = NO_ERROR; |
| 411 | struct lcdc_panel_info *lcdc = NULL; |
| 412 | |
| 413 | mdss_intf_tg_setup(pinfo, MDP_INTF_0_BASE); |
| 414 | |
| 415 | mdp_clk_gating_ctrl(); |
| 416 | |
| 417 | mdss_vbif_setup(); |
| 418 | mdss_smp_setup(pinfo); |
| 419 | |
Dhaval Patel | d6c54b5 | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 420 | mdss_qos_remapper_setup(); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 421 | |
| 422 | mdss_rgb_pipe_config(fb, pinfo, MDP_VP_0_RGB_0_BASE); |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 423 | if (pinfo->lcdc.dual_pipe) |
| 424 | mdss_rgb_pipe_config(fb, pinfo, MDP_VP_0_RGB_1_BASE); |
| 425 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 426 | |
| 427 | mdss_layer_mixer_setup(fb, pinfo); |
| 428 | |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 429 | |
| 430 | if (pinfo->lcdc.dual_pipe) |
| 431 | writel(0x181F10, MDP_CTL_0_BASE + CTL_TOP); |
| 432 | else |
| 433 | writel(0x1F10, MDP_CTL_0_BASE + CTL_TOP); |
| 434 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 435 | writel(0x9, MDP_DISP_INTF_SEL); |
| 436 | writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); |
| 437 | writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); |
| 438 | writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); |
| 439 | |
| 440 | return 0; |
| 441 | } |
| 442 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 443 | int mdp_dsi_cmd_config(struct msm_panel_info *pinfo, |
| 444 | struct fbcon_config *fb) |
| 445 | { |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 446 | int ret = NO_ERROR; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 447 | |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 448 | struct lcdc_panel_info *lcdc = NULL; |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 449 | uint32_t mdss_mdp_intf_off = 0; |
| 450 | |
| 451 | if (pinfo == NULL) |
| 452 | return ERR_INVALID_ARGS; |
| 453 | |
| 454 | lcdc = &(pinfo->lcdc); |
| 455 | if (lcdc == NULL) |
| 456 | return ERR_INVALID_ARGS; |
| 457 | |
| 458 | mdss_mdp_intf_off = mdss_mdp_intf_offset(); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 459 | |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 460 | mdp_clk_gating_ctrl(); |
| 461 | |
| 462 | writel(0x0100, MDP_DISP_INTF_SEL); |
| 463 | |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 464 | mdss_vbif_setup(); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 465 | mdss_smp_setup(pinfo); |
Dhaval Patel | d6c54b5 | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 466 | mdss_qos_remapper_setup(); |
| 467 | |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 468 | mdss_rgb_pipe_config(fb, pinfo, MDP_VP_0_RGB_0_BASE); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 469 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 470 | mdss_layer_mixer_setup(fb, pinfo); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 471 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 472 | writel(0x213F, MDP_INTF_1_BASE + MDP_PANEL_FORMAT + mdss_mdp_intf_off); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 473 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 474 | writel(0x20020, MDP_CTL_0_BASE + CTL_TOP); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 475 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 476 | return ret; |
| 477 | } |
| 478 | |
| 479 | int mdp_dsi_video_on(void) |
| 480 | { |
| 481 | int ret = NO_ERROR; |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 482 | writel(0x32048, MDP_CTL_0_BASE + CTL_FLUSH); |
| 483 | writel(0x32090, MDP_CTL_1_BASE + CTL_FLUSH); |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 484 | writel(0x01, MDP_INTF_1_TIMING_ENGINE_EN + mdss_mdp_intf_offset()); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 485 | return ret; |
| 486 | } |
| 487 | |
| 488 | int mdp_dsi_video_off() |
| 489 | { |
| 490 | if(!target_cont_splash_screen()) |
| 491 | { |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 492 | writel(0x00000000, MDP_INTF_1_TIMING_ENGINE_EN + |
| 493 | mdss_mdp_intf_offset()); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 494 | mdelay(60); |
| 495 | /* Ping-Pong done Tear Check Read/Write */ |
| 496 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 497 | writel(0xFF777713, MDP_INTR_CLEAR); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 498 | } |
| 499 | |
Siddhartha Agrawal | 6a59822 | 2013-02-17 18:33:27 -0800 | [diff] [blame] | 500 | writel(0x00000000, MDP_INTR_EN); |
| 501 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 502 | return NO_ERROR; |
| 503 | } |
| 504 | |
| 505 | int mdp_dsi_cmd_off() |
| 506 | { |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 507 | if(!target_cont_splash_screen()) |
| 508 | { |
| 509 | /* Ping-Pong done Tear Check Read/Write */ |
| 510 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 511 | writel(0xFF777713, MDP_INTR_CLEAR); |
| 512 | } |
| 513 | writel(0x00000000, MDP_INTR_EN); |
| 514 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 515 | return NO_ERROR; |
| 516 | } |
| 517 | |
| 518 | int mdp_dma_on(void) |
| 519 | { |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 520 | writel(0x32048, MDP_CTL_0_BASE + CTL_FLUSH); |
| 521 | writel(0x01, MDP_CTL_0_BASE + CTL_START); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 522 | return NO_ERROR; |
| 523 | } |
| 524 | |
| 525 | void mdp_disable(void) |
| 526 | { |
| 527 | |
| 528 | } |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 529 | |
| 530 | int mdp_edp_on(void) |
| 531 | { |
| 532 | writel(0x32048, MDP_CTL_0_BASE + CTL_FLUSH); |
| 533 | writel(0x01, MDP_INTF_0_TIMING_ENGINE_EN + mdss_mdp_intf_offset()); |
| 534 | return NO_ERROR; |
| 535 | } |
| 536 | |
| 537 | int mdp_edp_off(void) |
| 538 | { |
| 539 | if (!target_cont_splash_screen()) { |
| 540 | |
| 541 | writel(0x00000000, MDP_INTF_0_TIMING_ENGINE_EN + |
| 542 | mdss_mdp_intf_offset()); |
| 543 | mdelay(60); |
| 544 | /* Ping-Pong done Tear Check Read/Write */ |
| 545 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 546 | writel(0xFF777713, MDP_INTR_CLEAR); |
| 547 | writel(0x00000000, MDP_INTR_EN); |
| 548 | } |
| 549 | |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 550 | writel(0x00000000, MDP_INTR_EN); |
| 551 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 552 | return NO_ERROR; |
| 553 | } |