Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2010-2014, The Linux Foundation. All rights reserved. |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 12 | * * Neither the name of The Linux Foundation nor the names of its |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #include <reg.h> |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 31 | #include <endian.h> |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 32 | #include <mipi_dsi.h> |
| 33 | #include <dev/fbcon.h> |
Greg Grisco | d625055 | 2011-06-29 14:40:23 -0700 | [diff] [blame] | 34 | #include <stdlib.h> |
Greg Grisco | 1073a5e | 2011-07-28 18:59:18 -0700 | [diff] [blame] | 35 | #include <string.h> |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 36 | #include <debug.h> |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 37 | #include <target/display.h> |
| 38 | #include <platform/iomap.h> |
| 39 | #include <platform/clock.h> |
Greg Grisco | 1073a5e | 2011-07-28 18:59:18 -0700 | [diff] [blame] | 40 | #include <platform/timer.h> |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 41 | #include <err.h> |
| 42 | #include <msm_panel.h> |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 43 | |
| 44 | extern void mdp_disable(void); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 45 | extern int mipi_dsi_cmd_config(struct fbcon_config mipi_fb_cfg, |
| 46 | unsigned short num_of_lanes); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 47 | extern void mdp_shutdown(void); |
| 48 | extern void mdp_start_dma(void); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 49 | |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 50 | #if (DISPLAY_TYPE_MDSS == 0) |
| 51 | #define MIPI_DSI0_BASE MIPI_DSI_BASE |
| 52 | #define MIPI_DSI1_BASE MIPI_DSI_BASE |
| 53 | #endif |
| 54 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 55 | #if DISPLAY_MIPI_PANEL_TOSHIBA |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 56 | static struct fbcon_config mipi_fb_cfg = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 57 | .height = TSH_MIPI_FB_HEIGHT, |
| 58 | .width = TSH_MIPI_FB_WIDTH, |
| 59 | .stride = TSH_MIPI_FB_WIDTH, |
| 60 | .format = FB_FORMAT_RGB888, |
| 61 | .bpp = 24, |
| 62 | .update_start = NULL, |
| 63 | .update_done = NULL, |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 64 | }; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 65 | |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 66 | struct mipi_dsi_panel_config toshiba_panel_info = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 67 | .mode = MIPI_VIDEO_MODE, |
| 68 | .num_of_lanes = 1, |
| 69 | .dsi_phy_config = &mipi_dsi_toshiba_panel_phy_ctrl, |
| 70 | .panel_cmds = toshiba_panel_video_mode_cmds, |
| 71 | .num_of_panel_cmds = ARRAY_SIZE(toshiba_panel_video_mode_cmds), |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 72 | }; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 73 | #elif DISPLAY_MIPI_PANEL_NOVATEK_BLUE |
| 74 | static struct fbcon_config mipi_fb_cfg = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 75 | .height = NOV_MIPI_FB_HEIGHT, |
| 76 | .width = NOV_MIPI_FB_WIDTH, |
| 77 | .stride = NOV_MIPI_FB_WIDTH, |
| 78 | .format = FB_FORMAT_RGB888, |
| 79 | .bpp = 24, |
| 80 | .update_start = NULL, |
| 81 | .update_done = NULL, |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 82 | }; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 83 | |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 84 | struct mipi_dsi_panel_config novatek_panel_info = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 85 | .mode = MIPI_CMD_MODE, |
| 86 | .num_of_lanes = 2, |
| 87 | .dsi_phy_config = &mipi_dsi_novatek_panel_phy_ctrl, |
| 88 | .panel_cmds = novatek_panel_cmd_mode_cmds, |
| 89 | .num_of_panel_cmds = ARRAY_SIZE(novatek_panel_cmd_mode_cmds), |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 90 | }; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 91 | #else |
| 92 | static struct fbcon_config mipi_fb_cfg = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 93 | .height = 0, |
| 94 | .width = 0, |
| 95 | .stride = 0, |
| 96 | .format = 0, |
| 97 | .bpp = 0, |
| 98 | .update_start = NULL, |
| 99 | .update_done = NULL, |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 100 | }; |
| 101 | #endif |
| 102 | |
| 103 | static int cmd_mode_status = 0; |
Greg Grisco | d625055 | 2011-06-29 14:40:23 -0700 | [diff] [blame] | 104 | void secure_writel(uint32_t, uint32_t); |
| 105 | uint32_t secure_readl(uint32_t); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 106 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 107 | struct mipi_dsi_panel_config *get_panel_info(void) |
| 108 | { |
| 109 | #if DISPLAY_MIPI_PANEL_TOSHIBA |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 110 | return &toshiba_panel_info; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 111 | #elif DISPLAY_MIPI_PANEL_NOVATEK_BLUE |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 112 | return &novatek_panel_info; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 113 | #endif |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 114 | return NULL; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 115 | } |
| 116 | |
Shivaraj Shetty | 6460403 | 2013-11-14 16:44:10 +0530 | [diff] [blame] | 117 | static uint32_t response_value = 0; |
| 118 | |
| 119 | uint32_t mdss_dsi_read_panel_signature(uint32_t panel_signature) |
| 120 | { |
| 121 | uint32_t rec_buf[1]; |
| 122 | uint32_t *lp = rec_buf, data; |
| 123 | int ret = response_value; |
| 124 | |
| 125 | #if (DISPLAY_TYPE_MDSS == 1) |
| 126 | if (ret && ret != panel_signature) |
| 127 | goto exit_read_signature; |
| 128 | |
| 129 | ret = mipi_dsi_cmds_tx(&read_ddb_start_cmd, 1); |
| 130 | if (ret) |
| 131 | goto exit_read_signature; |
| 132 | if (!mdss_dsi_cmds_rx(&lp, 1, 1)) |
| 133 | goto exit_read_signature; |
| 134 | |
| 135 | data = ntohl(*lp); |
| 136 | data = data >> 8; |
| 137 | response_value = data; |
| 138 | if (response_value != panel_signature) |
| 139 | ret = response_value; |
| 140 | |
| 141 | exit_read_signature: |
| 142 | /* Keep the non detectable panel at the end and set panel signature 0xFFFF */ |
| 143 | if (panel_signature == 0xFFFF) |
| 144 | ret = 0; |
| 145 | #endif |
| 146 | return ret; |
| 147 | } |
| 148 | |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 149 | int mdss_dual_dsi_cmd_dma_trigger_for_panel() |
| 150 | { |
| 151 | uint32_t ReadValue; |
| 152 | uint32_t count = 0; |
| 153 | int status = 0; |
| 154 | |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 155 | #if (DISPLAY_TYPE_MDSS == 1) |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 156 | writel(0x03030303, MIPI_DSI0_BASE + INT_CTRL); |
| 157 | writel(0x1, MIPI_DSI0_BASE + CMD_MODE_DMA_SW_TRIGGER); |
| 158 | dsb(); |
| 159 | |
| 160 | writel(0x03030303, MIPI_DSI1_BASE + INT_CTRL); |
| 161 | writel(0x1, MIPI_DSI1_BASE + CMD_MODE_DMA_SW_TRIGGER); |
| 162 | dsb(); |
| 163 | |
| 164 | ReadValue = readl(MIPI_DSI1_BASE + INT_CTRL) & 0x00000001; |
| 165 | while (ReadValue != 0x00000001) { |
| 166 | ReadValue = readl(MIPI_DSI1_BASE + INT_CTRL) & 0x00000001; |
| 167 | count++; |
| 168 | if (count > 0xffff) { |
| 169 | status = FAIL; |
| 170 | dprintf(CRITICAL, |
| 171 | "Panel CMD: command mode dma test failed\n"); |
| 172 | return status; |
| 173 | } |
| 174 | } |
| 175 | |
| 176 | writel((readl(MIPI_DSI1_BASE + INT_CTRL) | 0x01000001), |
| 177 | MIPI_DSI1_BASE + INT_CTRL); |
| 178 | dprintf(SPEW, "Panel CMD: command mode dma tested successfully\n"); |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 179 | #endif |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 180 | return status; |
| 181 | } |
| 182 | |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 183 | int dsi_cmd_dma_trigger_for_panel() |
| 184 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 185 | unsigned long ReadValue; |
| 186 | unsigned long count = 0; |
| 187 | int status = 0; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 188 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 189 | writel(0x03030303, DSI_INT_CTRL); |
| 190 | writel(0x1, DSI_CMD_MODE_DMA_SW_TRIGGER); |
| 191 | dsb(); |
| 192 | ReadValue = readl(DSI_INT_CTRL) & 0x00000001; |
| 193 | while (ReadValue != 0x00000001) { |
| 194 | ReadValue = readl(DSI_INT_CTRL) & 0x00000001; |
| 195 | count++; |
| 196 | if (count > 0xffff) { |
| 197 | status = FAIL; |
| 198 | dprintf(CRITICAL, |
| 199 | "Panel CMD: command mode dma test failed\n"); |
| 200 | return status; |
| 201 | } |
| 202 | } |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 203 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 204 | writel((readl(DSI_INT_CTRL) | 0x01000001), DSI_INT_CTRL); |
| 205 | dprintf(SPEW, "Panel CMD: command mode dma tested successfully\n"); |
| 206 | return status; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 207 | } |
| 208 | |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 209 | int mdss_dual_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count) |
| 210 | { |
| 211 | int ret = 0; |
| 212 | struct mipi_dsi_cmd *cm; |
| 213 | int i = 0; |
| 214 | char pload[256]; |
| 215 | uint32_t off; |
| 216 | |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 217 | #if (DISPLAY_TYPE_MDSS == 1) |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 218 | /* Align pload at 8 byte boundry */ |
| 219 | off = pload; |
| 220 | off &= 0x07; |
| 221 | if (off) |
| 222 | off = 8 - off; |
| 223 | off += pload; |
| 224 | |
| 225 | cm = cmds; |
| 226 | for (i = 0; i < count; i++) { |
| 227 | memcpy((void *)off, (cm->payload), cm->size); |
| 228 | writel(off, MIPI_DSI0_BASE + DMA_CMD_OFFSET); |
| 229 | writel(cm->size, MIPI_DSI0_BASE + DMA_CMD_LENGTH); // reg 0x48 for this build |
| 230 | writel(off, MIPI_DSI1_BASE + DMA_CMD_OFFSET); |
| 231 | writel(cm->size, MIPI_DSI1_BASE + DMA_CMD_LENGTH); // reg 0x48 for this build |
| 232 | dsb(); |
| 233 | ret += mdss_dual_dsi_cmd_dma_trigger_for_panel(); |
Dhaval Patel | 607a624 | 2013-10-29 12:37:24 -0700 | [diff] [blame] | 234 | if (cm->wait) |
| 235 | mdelay(cm->wait); |
| 236 | else |
| 237 | udelay(80); |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 238 | cm++; |
| 239 | } |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 240 | #endif |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 241 | return ret; |
| 242 | } |
| 243 | |
Casey Piper | 8403675 | 2013-09-05 14:56:37 -0700 | [diff] [blame] | 244 | int mdss_dsi_cmds_rx(uint32_t **rp, int rp_len, int rdbk_len) |
| 245 | { |
| 246 | uint32_t *lp, data; |
| 247 | char *dp; |
| 248 | int i, off; |
| 249 | int rlen, res; |
| 250 | |
| 251 | if (rdbk_len > rp_len) { |
| 252 | return 0; |
| 253 | } |
| 254 | |
| 255 | if (rdbk_len <= 2) |
| 256 | rlen = 4; /* short read */ |
| 257 | else |
| 258 | rlen = MIPI_DSI_MRPS + 6; /* 4 bytes header + 2 bytes crc */ |
| 259 | |
| 260 | if (rlen > MIPI_DSI_REG_LEN) { |
| 261 | return 0; |
| 262 | } |
| 263 | |
| 264 | res = rlen & 0x03; |
| 265 | |
| 266 | rlen += res; /* 4 byte align */ |
| 267 | lp = *rp; |
| 268 | |
| 269 | rlen += 3; |
| 270 | rlen >>= 2; |
| 271 | |
| 272 | if (rlen > 4) |
| 273 | rlen = 4; /* 4 x 32 bits registers only */ |
| 274 | |
Shivaraj Shetty | 3c77da6 | 2013-12-09 15:58:16 +0530 | [diff] [blame] | 275 | off = RDBK_DATA0; |
Casey Piper | 8403675 | 2013-09-05 14:56:37 -0700 | [diff] [blame] | 276 | off += ((rlen - 1) * 4); |
| 277 | |
| 278 | for (i = 0; i < rlen; i++) { |
| 279 | data = readl(MIPI_DSI_BASE + off); |
| 280 | *lp = ntohl(data); /* to network byte order */ |
| 281 | lp++; |
| 282 | |
| 283 | off -= 4; |
| 284 | } |
| 285 | |
| 286 | if (rdbk_len > 2) { |
| 287 | /*First 4 bytes + paded bytes will be header next len bytes would be payload */ |
| 288 | for (i = 0; i < rdbk_len; i++) { |
| 289 | dp = *rp; |
| 290 | dp[i] = dp[(res + i) >> 2]; |
| 291 | } |
| 292 | } |
| 293 | return rdbk_len; |
| 294 | } |
| 295 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 296 | int mipi_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count) |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 297 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 298 | int ret = 0; |
| 299 | struct mipi_dsi_cmd *cm; |
| 300 | int i = 0; |
| 301 | char pload[256]; |
| 302 | uint32_t off; |
Deepa Dinamani | a080a40 | 2011-11-05 18:59:26 -0700 | [diff] [blame] | 303 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 304 | /* Align pload at 8 byte boundry */ |
| 305 | off = pload; |
| 306 | off &= 0x07; |
| 307 | if (off) |
| 308 | off = 8 - off; |
| 309 | off += pload; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 310 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 311 | cm = cmds; |
| 312 | for (i = 0; i < count; i++) { |
| 313 | memcpy((void *)off, (cm->payload), cm->size); |
| 314 | writel(off, DSI_DMA_CMD_OFFSET); |
| 315 | writel(cm->size, DSI_DMA_CMD_LENGTH); // reg 0x48 for this build |
| 316 | dsb(); |
| 317 | ret += dsi_cmd_dma_trigger_for_panel(); |
Sangani Suryanarayana Raju | 769f9ac | 2013-04-30 19:05:06 +0530 | [diff] [blame] | 318 | dsb(); |
| 319 | if (cm->wait) |
| 320 | mdelay(cm->wait); |
| 321 | else |
| 322 | udelay(80); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 323 | cm++; |
| 324 | } |
| 325 | return ret; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 326 | } |
| 327 | |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 328 | /* |
| 329 | * mipi_dsi_cmd_rx: can receive at most 16 bytes |
| 330 | * per transaction since it only have 4 32bits reigsters |
| 331 | * to hold data. |
| 332 | * therefore Maximum Return Packet Size need to be set to 16. |
| 333 | * any return data more than MRPS need to be break down |
| 334 | * to multiple transactions. |
| 335 | */ |
| 336 | int mipi_dsi_cmds_rx(char **rp, int len) |
| 337 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 338 | uint32_t *lp, data; |
| 339 | char *dp; |
| 340 | int i, off, cnt; |
| 341 | int rlen, res; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 342 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 343 | if (len <= 2) |
| 344 | rlen = 4; /* short read */ |
| 345 | else |
| 346 | rlen = MIPI_DSI_MRPS + 6; /* 4 bytes header + 2 bytes crc */ |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 347 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 348 | if (rlen > MIPI_DSI_REG_LEN) { |
| 349 | return 0; |
| 350 | } |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 351 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 352 | res = rlen & 0x03; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 353 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 354 | rlen += res; /* 4 byte align */ |
| 355 | lp = (uint32_t *) (*rp); |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 356 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 357 | cnt = rlen; |
| 358 | cnt += 3; |
| 359 | cnt >>= 2; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 360 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 361 | if (cnt > 4) |
| 362 | cnt = 4; /* 4 x 32 bits registers only */ |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 363 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 364 | off = 0x068; /* DSI_RDBK_DATA0 */ |
| 365 | off += ((cnt - 1) * 4); |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 366 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 367 | for (i = 0; i < cnt; i++) { |
| 368 | data = (uint32_t) readl(MIPI_DSI_BASE + off); |
| 369 | *lp++ = ntohl(data); /* to network byte order */ |
| 370 | off -= 4; |
| 371 | } |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 372 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 373 | if (len > 2) { |
| 374 | /*First 4 bytes + paded bytes will be header next len bytes would be payload */ |
| 375 | for (i = 0; i < len; i++) { |
| 376 | dp = *rp; |
| 377 | dp[i] = dp[4 + res + i]; |
| 378 | } |
| 379 | } |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 380 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 381 | return len; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 382 | } |
| 383 | |
| 384 | static int mipi_dsi_cmd_bta_sw_trigger(void) |
| 385 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 386 | uint32_t data; |
| 387 | int cnt = 0; |
| 388 | int err = 0; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 389 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 390 | writel(0x01, MIPI_DSI_BASE + 0x094); /* trigger */ |
| 391 | while (cnt < 10000) { |
| 392 | data = readl(MIPI_DSI_BASE + 0x0004); /*DSI_STATUS */ |
| 393 | if ((data & 0x0010) == 0) |
| 394 | break; |
| 395 | cnt++; |
| 396 | } |
| 397 | if (cnt == 10000) |
| 398 | err = 1; |
| 399 | return err; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 400 | } |
| 401 | |
| 402 | static uint32_t mipi_novatek_manufacture_id(void) |
| 403 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 404 | char rec_buf[24]; |
| 405 | char *rp = rec_buf; |
| 406 | uint32_t *lp, data; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 407 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 408 | mipi_dsi_cmds_tx(&novatek_panel_manufacture_id_cmd, 1); |
| 409 | mipi_dsi_cmds_rx(&rp, 3); |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 410 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 411 | lp = (uint32_t *) rp; |
| 412 | data = (uint32_t) * lp; |
| 413 | data = ntohl(data); |
| 414 | data = data >> 8; |
| 415 | return data; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 416 | } |
| 417 | |
Ray Zhang | 4c7e37f | 2013-12-03 17:04:55 +0800 | [diff] [blame] | 418 | int mdss_dsi_host_init(struct mipi_dsi_panel_config *pinfo, uint32_t |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 419 | broadcast) |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 420 | { |
| 421 | uint8_t DMA_STREAM1 = 0; // for mdp display processor path |
| 422 | uint8_t EMBED_MODE1 = 1; // from frame buffer |
| 423 | uint8_t POWER_MODE2 = 1; // from frame buffer |
| 424 | uint8_t PACK_TYPE1; // long packet |
| 425 | uint8_t VC1 = 0; |
| 426 | uint8_t DT1 = 0; // non embedded mode |
| 427 | uint8_t WC1 = 0; // for non embedded mode only |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 428 | uint8_t DLNx_EN; |
Siddhartha Agrawal | 2679a82 | 2013-05-31 19:15:12 -0700 | [diff] [blame] | 429 | uint8_t lane_swap = 0; |
Siddhartha Agrawal | b6c861f | 2013-05-31 19:36:44 -0700 | [diff] [blame] | 430 | uint32_t timing_ctl = 0; |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 431 | |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 432 | #if (DISPLAY_TYPE_MDSS == 1) |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 433 | switch (pinfo->num_of_lanes) { |
| 434 | default: |
| 435 | case 1: |
| 436 | DLNx_EN = 1; // 1 lane |
| 437 | break; |
| 438 | case 2: |
| 439 | DLNx_EN = 3; // 2 lane |
| 440 | break; |
| 441 | case 3: |
| 442 | DLNx_EN = 7; // 3 lane |
| 443 | break; |
| 444 | case 4: |
| 445 | DLNx_EN = 0x0F; /* 4 lanes */ |
| 446 | break; |
| 447 | } |
| 448 | |
| 449 | PACK_TYPE1 = pinfo->pack; |
Siddhartha Agrawal | 2679a82 | 2013-05-31 19:15:12 -0700 | [diff] [blame] | 450 | lane_swap = pinfo->lane_swap; |
Siddhartha Agrawal | b6c861f | 2013-05-31 19:36:44 -0700 | [diff] [blame] | 451 | timing_ctl = ((pinfo->t_clk_post << 8) | pinfo->t_clk_pre); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 452 | |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 453 | if (broadcast) { |
| 454 | writel(0x0001, MIPI_DSI1_BASE + SOFT_RESET); |
| 455 | writel(0x0000, MIPI_DSI1_BASE + SOFT_RESET); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 456 | |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 457 | writel((0 << 16) | 0x3f, MIPI_DSI1_BASE + CLK_CTRL); /* Turn on all DSI Clks */ |
| 458 | writel(DMA_STREAM1 << 8 | 0x04, MIPI_DSI1_BASE + TRIG_CTRL); // reg 0x80 dma trigger: sw |
| 459 | // trigger 0x4; dma stream1 |
| 460 | |
| 461 | writel(0 << 30 | DLNx_EN << 4 | 0x105, MIPI_DSI1_BASE + CTRL); // reg 0x00 for this |
| 462 | // build |
| 463 | writel(broadcast << 31 | EMBED_MODE1 << 28 | POWER_MODE2 << 26 |
| 464 | | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1, |
| 465 | MIPI_DSI1_BASE + COMMAND_MODE_DMA_CTRL); |
Siddhartha Agrawal | 2679a82 | 2013-05-31 19:15:12 -0700 | [diff] [blame] | 466 | |
| 467 | writel(lane_swap, MIPI_DSI1_BASE + LANE_SWAP_CTL); |
Siddhartha Agrawal | b6c861f | 2013-05-31 19:36:44 -0700 | [diff] [blame] | 468 | writel(timing_ctl, MIPI_DSI1_BASE + TIMING_CTL); |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 469 | } |
| 470 | |
| 471 | writel(0x0001, MIPI_DSI0_BASE + SOFT_RESET); |
| 472 | writel(0x0000, MIPI_DSI0_BASE + SOFT_RESET); |
| 473 | |
| 474 | writel((0 << 16) | 0x3f, MIPI_DSI0_BASE + CLK_CTRL); /* Turn on all DSI Clks */ |
| 475 | writel(DMA_STREAM1 << 8 | 0x04, MIPI_DSI0_BASE + TRIG_CTRL); // reg 0x80 dma trigger: sw |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 476 | // trigger 0x4; dma stream1 |
| 477 | |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 478 | writel(0 << 30 | DLNx_EN << 4 | 0x105, MIPI_DSI0_BASE + CTRL); // reg 0x00 for this |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 479 | // build |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 480 | writel(broadcast << 31 | EMBED_MODE1 << 28 | POWER_MODE2 << 26 |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 481 | | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1, |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 482 | MIPI_DSI0_BASE + COMMAND_MODE_DMA_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 483 | |
Siddhartha Agrawal | 2679a82 | 2013-05-31 19:15:12 -0700 | [diff] [blame] | 484 | writel(lane_swap, MIPI_DSI0_BASE + LANE_SWAP_CTL); |
Siddhartha Agrawal | b6c861f | 2013-05-31 19:36:44 -0700 | [diff] [blame] | 485 | writel(timing_ctl, MIPI_DSI0_BASE + TIMING_CTL); |
Ray Zhang | 4c7e37f | 2013-12-03 17:04:55 +0800 | [diff] [blame] | 486 | #endif |
Siddhartha Agrawal | 2679a82 | 2013-05-31 19:15:12 -0700 | [diff] [blame] | 487 | |
Ray Zhang | 4c7e37f | 2013-12-03 17:04:55 +0800 | [diff] [blame] | 488 | return 0; |
| 489 | } |
| 490 | |
| 491 | int mdss_dsi_panel_initialize(struct mipi_dsi_panel_config *pinfo, uint32_t |
| 492 | broadcast) |
| 493 | { |
| 494 | int status = 0; |
| 495 | |
| 496 | #if (DISPLAY_TYPE_MDSS == 1) |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 497 | if (pinfo->panel_cmds) { |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 498 | |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 499 | if (broadcast) { |
| 500 | status = mdss_dual_dsi_cmds_tx(pinfo->panel_cmds, |
| 501 | pinfo->num_of_panel_cmds); |
| 502 | |
| 503 | } else { |
| 504 | status = mipi_dsi_cmds_tx(pinfo->panel_cmds, |
| 505 | pinfo->num_of_panel_cmds); |
Casey Piper | 8403675 | 2013-09-05 14:56:37 -0700 | [diff] [blame] | 506 | if (!status && target_panel_auto_detect_enabled()) |
| 507 | status = |
Shivaraj Shetty | 6460403 | 2013-11-14 16:44:10 +0530 | [diff] [blame] | 508 | mdss_dsi_read_panel_signature(pinfo->signature); |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 509 | } |
| 510 | } |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 511 | #endif |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 512 | return status; |
| 513 | } |
| 514 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 515 | int mipi_dsi_panel_initialize(struct mipi_dsi_panel_config *pinfo) |
| 516 | { |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 517 | uint8_t DMA_STREAM1 = 0; // for mdp display processor path |
| 518 | uint8_t EMBED_MODE1 = 1; // from frame buffer |
| 519 | uint8_t POWER_MODE2 = 1; // from frame buffer |
| 520 | uint8_t PACK_TYPE1; // long packet |
| 521 | uint8_t VC1 = 0; |
| 522 | uint8_t DT1 = 0; // non embedded mode |
| 523 | uint8_t WC1 = 0; // for non embedded mode only |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 524 | int status = 0; |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 525 | uint8_t DLNx_EN; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 526 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 527 | switch (pinfo->num_of_lanes) { |
| 528 | default: |
| 529 | case 1: |
| 530 | DLNx_EN = 1; // 1 lane |
| 531 | break; |
| 532 | case 2: |
| 533 | DLNx_EN = 3; // 2 lane |
| 534 | break; |
| 535 | case 3: |
| 536 | DLNx_EN = 7; // 3 lane |
| 537 | break; |
Amir Samuelov | 2d4ba16 | 2012-07-22 11:53:14 +0300 | [diff] [blame] | 538 | case 4: |
| 539 | DLNx_EN = 0x0F; /* 4 lanes */ |
| 540 | break; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 541 | } |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 542 | |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 543 | PACK_TYPE1 = pinfo->pack; |
| 544 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 545 | writel(0x0001, DSI_SOFT_RESET); |
| 546 | writel(0x0000, DSI_SOFT_RESET); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 547 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 548 | writel((0 << 16) | 0x3f, DSI_CLK_CTRL); /* Turn on all DSI Clks */ |
| 549 | writel(DMA_STREAM1 << 8 | 0x04, DSI_TRIG_CTRL); // reg 0x80 dma trigger: sw |
| 550 | // trigger 0x4; dma stream1 |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 551 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 552 | writel(0 << 30 | DLNx_EN << 4 | 0x105, DSI_CTRL); // reg 0x00 for this |
| 553 | // build |
| 554 | writel(EMBED_MODE1 << 28 | POWER_MODE2 << 26 |
| 555 | | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1, |
| 556 | DSI_COMMAND_MODE_DMA_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 557 | |
Amir Samuelov | 2d4ba16 | 2012-07-22 11:53:14 +0300 | [diff] [blame] | 558 | if (pinfo->panel_cmds) |
| 559 | status = mipi_dsi_cmds_tx(pinfo->panel_cmds, |
| 560 | pinfo->num_of_panel_cmds); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 561 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 562 | return status; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 563 | } |
| 564 | |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 565 | //TODO: Clean up arguments being passed in not being used |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 566 | int |
| 567 | config_dsi_video_mode(unsigned short disp_width, unsigned short disp_height, |
| 568 | unsigned short img_width, unsigned short img_height, |
| 569 | unsigned short hsync_porch0_fp, |
| 570 | unsigned short hsync_porch0_bp, |
| 571 | unsigned short vsync_porch0_fp, |
| 572 | unsigned short vsync_porch0_bp, |
| 573 | unsigned short hsync_width, |
| 574 | unsigned short vsync_width, unsigned short dst_format, |
| 575 | unsigned short traffic_mode, unsigned short datalane_num) |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 576 | { |
| 577 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 578 | unsigned char DST_FORMAT; |
| 579 | unsigned char TRAFIC_MODE; |
| 580 | unsigned char DLNx_EN; |
| 581 | // video mode data ctrl |
| 582 | int status = 0; |
| 583 | unsigned long low_pwr_stop_mode = 0; |
| 584 | unsigned char eof_bllp_pwr = 0x9; |
| 585 | unsigned char interleav = 0; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 586 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 587 | // disable mdp first |
| 588 | mdp_disable(); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 589 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 590 | writel(0x00000000, DSI_CLK_CTRL); |
| 591 | writel(0x00000000, DSI_CLK_CTRL); |
| 592 | writel(0x00000000, DSI_CLK_CTRL); |
| 593 | writel(0x00000000, DSI_CLK_CTRL); |
| 594 | writel(0x00000002, DSI_CLK_CTRL); |
| 595 | writel(0x00000006, DSI_CLK_CTRL); |
| 596 | writel(0x0000000e, DSI_CLK_CTRL); |
| 597 | writel(0x0000001e, DSI_CLK_CTRL); |
| 598 | writel(0x0000003e, DSI_CLK_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 599 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 600 | writel(0, DSI_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 601 | |
Padmanabhan Komanduru | 7860be5 | 2014-03-18 19:07:36 +0530 | [diff] [blame] | 602 | writel(0x13ff3fe0, DSI_ERR_INT_MASK0); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 603 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 604 | DST_FORMAT = 0; // RGB565 |
| 605 | dprintf(SPEW, "DSI_Video_Mode - Dst Format: RGB565\n"); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 606 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 607 | DLNx_EN = 1; // 1 lane with clk programming |
| 608 | dprintf(SPEW, "Data Lane: 1 lane\n"); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 609 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 610 | TRAFIC_MODE = 0; // non burst mode with sync pulses |
| 611 | dprintf(SPEW, "Traffic mode: non burst mode with sync pulses\n"); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 612 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 613 | writel(0x02020202, DSI_INT_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 614 | |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 615 | writel(((hsync_width + img_width + hsync_porch0_bp) << 16) |
| 616 | | (hsync_width + hsync_porch0_bp), |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 617 | DSI_VIDEO_MODE_ACTIVE_H); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 618 | |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 619 | writel(((vsync_width + img_height + vsync_porch0_bp) << 16) |
| 620 | | (vsync_width + vsync_porch0_bp), |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 621 | DSI_VIDEO_MODE_ACTIVE_V); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 622 | |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 623 | writel(((vsync_width + img_height + vsync_porch0_fp + vsync_porch0_bp - 1) << 16) |
| 624 | | (hsync_width + img_width + hsync_porch0_fp + hsync_porch0_bp - 1), |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 625 | DSI_VIDEO_MODE_TOTAL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 626 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 627 | writel((hsync_width << 16) | 0, DSI_VIDEO_MODE_HSYNC); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 628 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 629 | writel(0 << 16 | 0, DSI_VIDEO_MODE_VSYNC); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 630 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 631 | writel(vsync_width << 16 | 0, DSI_VIDEO_MODE_VSYNC_VPOS); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 632 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 633 | writel(1, DSI_EOT_PACKET_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 634 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 635 | writel(0x00000100, DSI_MISR_VIDEO_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 636 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 637 | writel(low_pwr_stop_mode << 16 | eof_bllp_pwr << 12 | TRAFIC_MODE << 8 |
| 638 | | DST_FORMAT << 4 | 0x0, DSI_VIDEO_MODE_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 639 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 640 | writel(0x67, DSI_CAL_STRENGTH_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 641 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 642 | writel(0x80006711, DSI_CAL_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 643 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 644 | writel(0x00010100, DSI_MISR_VIDEO_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 645 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 646 | writel(0x00010100, DSI_INT_CTRL); |
| 647 | writel(0x02010202, DSI_INT_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 648 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 649 | writel(0x02030303, DSI_INT_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 650 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 651 | writel(interleav << 30 | 0 << 24 | 0 << 20 | DLNx_EN << 4 |
| 652 | | 0x103, DSI_CTRL); |
| 653 | mdelay(10); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 654 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 655 | return status; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 656 | } |
| 657 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 658 | int |
| 659 | config_dsi_cmd_mode(unsigned short disp_width, unsigned short disp_height, |
| 660 | unsigned short img_width, unsigned short img_height, |
| 661 | unsigned short dst_format, |
| 662 | unsigned short traffic_mode, unsigned short datalane_num) |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 663 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 664 | unsigned char DST_FORMAT; |
| 665 | unsigned char TRAFIC_MODE; |
| 666 | unsigned char DLNx_EN; |
| 667 | // video mode data ctrl |
| 668 | int status = 0; |
Greg Grisco | d625055 | 2011-06-29 14:40:23 -0700 | [diff] [blame] | 669 | unsigned char interleav = 0; |
| 670 | unsigned char ystride = 0x03; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 671 | // disable mdp first |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 672 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 673 | writel(0x00000000, DSI_CLK_CTRL); |
| 674 | writel(0x00000000, DSI_CLK_CTRL); |
| 675 | writel(0x00000000, DSI_CLK_CTRL); |
| 676 | writel(0x00000000, DSI_CLK_CTRL); |
| 677 | writel(0x00000002, DSI_CLK_CTRL); |
| 678 | writel(0x00000006, DSI_CLK_CTRL); |
| 679 | writel(0x0000000e, DSI_CLK_CTRL); |
| 680 | writel(0x0000001e, DSI_CLK_CTRL); |
| 681 | writel(0x0000003e, DSI_CLK_CTRL); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 682 | |
Padmanabhan Komanduru | 7860be5 | 2014-03-18 19:07:36 +0530 | [diff] [blame] | 683 | writel(0x13ff3fe0, DSI_ERR_INT_MASK0); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 684 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 685 | // writel(0, DSI_CTRL); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 686 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 687 | // writel(0, DSI_ERR_INT_MASK0); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 688 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 689 | DST_FORMAT = 8; // RGB888 |
| 690 | dprintf(SPEW, "DSI_Cmd_Mode - Dst Format: RGB888\n"); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 691 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 692 | DLNx_EN = 3; // 2 lane with clk programming |
| 693 | dprintf(SPEW, "Data Lane: 2 lane\n"); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 694 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 695 | TRAFIC_MODE = 0; // non burst mode with sync pulses |
| 696 | dprintf(SPEW, "Traffic mode: non burst mode with sync pulses\n"); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 697 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 698 | writel(0x02020202, DSI_INT_CTRL); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 699 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 700 | writel(0x00100000 | DST_FORMAT, DSI_COMMAND_MODE_MDP_CTRL); |
| 701 | writel((img_width * ystride + 1) << 16 | 0x0039, |
| 702 | DSI_COMMAND_MODE_MDP_STREAM0_CTRL); |
| 703 | writel((img_width * ystride + 1) << 16 | 0x0039, |
| 704 | DSI_COMMAND_MODE_MDP_STREAM1_CTRL); |
| 705 | writel(img_height << 16 | img_width, |
| 706 | DSI_COMMAND_MODE_MDP_STREAM0_TOTAL); |
| 707 | writel(img_height << 16 | img_width, |
| 708 | DSI_COMMAND_MODE_MDP_STREAM1_TOTAL); |
| 709 | writel(0xEE, DSI_CAL_STRENGTH_CTRL); |
| 710 | writel(0x80000000, DSI_CAL_CTRL); |
| 711 | writel(0x40, DSI_TRIG_CTRL); |
| 712 | writel(0x13c2c, DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL); |
| 713 | writel(interleav << 30 | 0 << 24 | 0 << 20 | DLNx_EN << 4 | 0x105, |
| 714 | DSI_CTRL); |
| 715 | mdelay(10); |
Padmanabhan Komanduru | 7860be5 | 2014-03-18 19:07:36 +0530 | [diff] [blame] | 716 | writel(0x14000000, DSI_COMMAND_MODE_DMA_CTRL); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 717 | writel(0x10000000, DSI_MISR_CMD_CTRL); |
Padmanabhan Komanduru | 7860be5 | 2014-03-18 19:07:36 +0530 | [diff] [blame] | 718 | writel(0x13ff3fe0, DSI_ERR_INT_MASK0); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 719 | writel(0x1, DSI_EOT_PACKET_CTRL); |
| 720 | // writel(0x0, MDP_OVERLAYPROC0_START); |
| 721 | mdp_start_dma(); |
| 722 | mdelay(10); |
| 723 | writel(0x1, DSI_CMD_MODE_MDP_SW_TRIGGER); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 724 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 725 | status = 1; |
| 726 | return status; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 727 | } |
| 728 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 729 | int mipi_dsi_video_config(unsigned short num_of_lanes) |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 730 | { |
| 731 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 732 | int status = 0; |
| 733 | unsigned long ReadValue; |
| 734 | unsigned long count = 0; |
| 735 | unsigned long low_pwr_stop_mode = 0; // low power mode 0x1111 start from |
| 736 | // bit16, high spd mode 0x0 |
| 737 | unsigned char eof_bllp_pwr = 0x9; // bit 12, 15, 1:low power stop mode or |
| 738 | // let cmd mode eng send packets in hs |
| 739 | // or lp mode |
| 740 | unsigned short image_wd = mipi_fb_cfg.width; |
| 741 | unsigned short image_ht = mipi_fb_cfg.height; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 742 | unsigned short display_wd = mipi_fb_cfg.width; |
| 743 | unsigned short display_ht = mipi_fb_cfg.height; |
| 744 | unsigned short hsync_porch_fp = MIPI_HSYNC_FRONT_PORCH_DCLK; |
| 745 | unsigned short hsync_porch_bp = MIPI_HSYNC_BACK_PORCH_DCLK; |
| 746 | unsigned short vsync_porch_fp = MIPI_VSYNC_FRONT_PORCH_LINES; |
| 747 | unsigned short vsync_porch_bp = MIPI_VSYNC_BACK_PORCH_LINES; |
| 748 | unsigned short hsync_width = MIPI_HSYNC_PULSE_WIDTH; |
| 749 | unsigned short vsync_width = MIPI_VSYNC_PULSE_WIDTH; |
| 750 | unsigned short dst_format = 0; |
| 751 | unsigned short traffic_mode = 0; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 752 | unsigned short pack_pattern = 0x12; //BGR |
| 753 | unsigned char ystride = 3; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 754 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 755 | low_pwr_stop_mode = 0x1111; // low pwr mode bit16:HSA, bit20:HBA, |
| 756 | // bit24:HFP, bit28:PULSE MODE, need enough |
| 757 | // time for swithc from LP to HS |
| 758 | eof_bllp_pwr = 0x9; // low power stop mode or let cmd mode eng send |
| 759 | // packets in hs or lp mode |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 760 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 761 | status += |
| 762 | config_dsi_video_mode(display_wd, display_ht, image_wd, image_ht, |
| 763 | hsync_porch_fp, hsync_porch_bp, |
| 764 | vsync_porch_fp, vsync_porch_bp, hsync_width, |
| 765 | vsync_width, dst_format, traffic_mode, |
| 766 | num_of_lanes); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 767 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 768 | status += |
| 769 | mdp_setup_dma_p_video_mode(display_wd, display_ht, image_wd, |
| 770 | image_ht, hsync_porch_fp, hsync_porch_bp, |
| 771 | vsync_porch_fp, vsync_porch_bp, |
| 772 | hsync_width, vsync_width, MIPI_FB_ADDR, |
| 773 | image_wd, pack_pattern, ystride); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 774 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 775 | ReadValue = readl(DSI_INT_CTRL) & 0x00010000; |
| 776 | while (ReadValue != 0x00010000) { |
| 777 | ReadValue = readl(DSI_INT_CTRL) & 0x00010000; |
| 778 | count++; |
| 779 | if (count > 0xffff) { |
| 780 | status = FAIL; |
| 781 | dprintf(CRITICAL, "Video lane test failed\n"); |
| 782 | return status; |
| 783 | } |
| 784 | } |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 785 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 786 | dprintf(SPEW, "Video lane tested successfully\n"); |
| 787 | return status; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 788 | } |
| 789 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 790 | int is_cmd_mode_enabled(void) |
| 791 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 792 | return cmd_mode_status; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 793 | } |
| 794 | |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 795 | #if DISPLAY_MIPI_PANEL_NOVATEK_BLUE |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 796 | void mipi_dsi_cmd_mode_trigger(void) |
| 797 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 798 | int status = 0; |
| 799 | unsigned short display_wd = mipi_fb_cfg.width; |
| 800 | unsigned short display_ht = mipi_fb_cfg.height; |
| 801 | unsigned short image_wd = mipi_fb_cfg.width; |
| 802 | unsigned short image_ht = mipi_fb_cfg.height; |
| 803 | unsigned short dst_format = 0; |
| 804 | unsigned short traffic_mode = 0; |
| 805 | struct mipi_dsi_panel_config *panel_info = &novatek_panel_info; |
| 806 | status += mipi_dsi_cmd_config(mipi_fb_cfg, panel_info->num_of_lanes); |
| 807 | mdelay(50); |
| 808 | config_dsi_cmd_mode(display_wd, display_ht, image_wd, image_ht, |
| 809 | dst_format, traffic_mode, |
| 810 | panel_info->num_of_lanes /* num_of_lanes */ ); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 811 | } |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 812 | #endif |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 813 | |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 814 | void mipi_dsi_shutdown(void) |
| 815 | { |
Amol Jadi | 6834f1a | 2012-06-29 14:42:59 -0700 | [diff] [blame] | 816 | if(!target_cont_splash_screen()) |
| 817 | { |
| 818 | mdp_shutdown(); |
| 819 | writel(0x01010101, DSI_INT_CTRL); |
| 820 | writel(0x13FF3BFF, DSI_ERR_INT_MASK0); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 821 | |
| 822 | #if (DISPLAY_MIPI_PANEL_NOVATEK_BLUE \ |
Amol Jadi | 6834f1a | 2012-06-29 14:42:59 -0700 | [diff] [blame] | 823 | || DISPLAY_MIPI_PANEL_TOSHIBA) |
| 824 | secure_writel(0x0, DSI_CC_REG); |
| 825 | secure_writel(0x0, DSI_PIXEL_CC_REG); |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 826 | #endif |
Amol Jadi | 6834f1a | 2012-06-29 14:42:59 -0700 | [diff] [blame] | 827 | |
| 828 | writel(0, DSI_CLK_CTRL); |
| 829 | writel(0, DSI_CTRL); |
| 830 | writel(0, DSIPHY_PLL_CTRL(0)); |
| 831 | } |
| 832 | else |
| 833 | { |
Chandan Uddaraju | 4877d37 | 2011-07-21 12:51:51 -0700 | [diff] [blame] | 834 | /* To keep the splash screen displayed till kernel driver takes |
| 835 | control, do not turn off the video mode engine and clocks. |
| 836 | Only disabling the MIPI DSI IRQs */ |
| 837 | writel(0x01010101, DSI_INT_CTRL); |
| 838 | writel(0x13FF3BFF, DSI_ERR_INT_MASK0); |
Amol Jadi | 6834f1a | 2012-06-29 14:42:59 -0700 | [diff] [blame] | 839 | } |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 840 | } |
| 841 | |
| 842 | struct fbcon_config *mipi_init(void) |
| 843 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 844 | int status = 0; |
| 845 | struct mipi_dsi_panel_config *panel_info = get_panel_info(); |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 846 | |
| 847 | if (panel_info == NULL) { |
| 848 | dprintf(CRITICAL, "Panel info is null\n"); |
| 849 | return NULL; |
| 850 | } |
| 851 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 852 | /* Enable MMSS_AHB_ARB_MATER_PORT_E for arbiter master0 and master 1 request */ |
Terence Hampson | f49ff4e | 2013-06-18 15:11:31 -0400 | [diff] [blame] | 853 | #if (!DISPLAY_MIPI_PANEL_RENESAS && !DISPLAY_TYPE_DSI6G && !DISPLAY_TYPE_8610) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 854 | writel(0x00001800, MMSS_SFPB_GPREG); |
Aparna Mallavarapu | f712f5e | 2011-08-04 21:11:00 +0530 | [diff] [blame] | 855 | #endif |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 856 | |
| 857 | #if DISPLAY_MIPI_PANEL_TOSHIBA_MDT61 |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 858 | mipi_dsi_phy_init(panel_info); |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 859 | #else |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 860 | mipi_dsi_phy_ctrl_config(panel_info); |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 861 | #endif |
| 862 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 863 | status += mipi_dsi_panel_initialize(panel_info); |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 864 | |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 865 | #if DISPLAY_MIPI_PANEL_NOVATEK_BLUE |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 866 | mipi_dsi_cmd_bta_sw_trigger(); |
| 867 | mipi_novatek_manufacture_id(); |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 868 | #endif |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 869 | mipi_fb_cfg.base = MIPI_FB_ADDR; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 870 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 871 | if (panel_info->mode == MIPI_VIDEO_MODE) |
| 872 | status += mipi_dsi_video_config(panel_info->num_of_lanes); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 873 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 874 | if (panel_info->mode == MIPI_CMD_MODE) |
| 875 | cmd_mode_status = 1; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 876 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 877 | return &mipi_fb_cfg; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 878 | } |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 879 | |
| 880 | int mipi_config(struct msm_fb_panel_data *panel) |
| 881 | { |
| 882 | int ret = NO_ERROR; |
| 883 | struct msm_panel_info *pinfo; |
| 884 | struct mipi_dsi_panel_config mipi_pinfo; |
| 885 | |
| 886 | if (!panel) |
| 887 | return ERR_INVALID_ARGS; |
| 888 | |
| 889 | pinfo = &(panel->panel_info); |
| 890 | mipi_pinfo.mode = pinfo->mipi.mode; |
| 891 | mipi_pinfo.num_of_lanes = pinfo->mipi.num_of_lanes; |
| 892 | mipi_pinfo.dsi_phy_config = pinfo->mipi.dsi_phy_db; |
| 893 | mipi_pinfo.panel_cmds = pinfo->mipi.panel_cmds; |
| 894 | mipi_pinfo.num_of_panel_cmds = pinfo->mipi.num_of_panel_cmds; |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 895 | mipi_pinfo.lane_swap = pinfo->mipi.lane_swap; |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 896 | mipi_pinfo.pack = 1; |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 897 | |
| 898 | /* Enable MMSS_AHB_ARB_MATER_PORT_E for |
| 899 | arbiter master0 and master 1 request */ |
Terence Hampson | f49ff4e | 2013-06-18 15:11:31 -0400 | [diff] [blame] | 900 | #if (!DISPLAY_MIPI_PANEL_RENESAS && !DISPLAY_TYPE_DSI6G && !DISPLAY_TYPE_8610) |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 901 | writel(0x00001800, MMSS_SFPB_GPREG); |
| 902 | #endif |
| 903 | |
| 904 | mipi_dsi_phy_init(&mipi_pinfo); |
| 905 | |
| 906 | ret += mipi_dsi_panel_initialize(&mipi_pinfo); |
| 907 | |
Channagoud Kadabi | 01c9182 | 2012-06-06 15:53:30 +0530 | [diff] [blame] | 908 | if (pinfo->rotate && panel->rotate) |
| 909 | pinfo->rotate(); |
| 910 | |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 911 | return ret; |
| 912 | } |
| 913 | |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 914 | int mdss_dsi_video_mode_config(uint16_t disp_width, |
| 915 | uint16_t disp_height, |
| 916 | uint16_t img_width, |
| 917 | uint16_t img_height, |
| 918 | uint16_t hsync_porch0_fp, |
| 919 | uint16_t hsync_porch0_bp, |
| 920 | uint16_t vsync_porch0_fp, |
| 921 | uint16_t vsync_porch0_bp, |
| 922 | uint16_t hsync_width, |
| 923 | uint16_t vsync_width, |
| 924 | uint16_t dst_format, |
| 925 | uint16_t traffic_mode, |
| 926 | uint8_t lane_en, |
| 927 | uint16_t low_pwr_stop_mode, |
| 928 | uint8_t eof_bllp_pwr, |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 929 | uint8_t interleav, |
| 930 | uint32_t ctl_base) |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 931 | { |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 932 | int status = 0; |
| 933 | |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 934 | #if (DISPLAY_TYPE_MDSS == 1) |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 935 | /* disable mdp first */ |
| 936 | mdp_disable(); |
| 937 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 938 | writel(0x00000000, ctl_base + CLK_CTRL); |
| 939 | writel(0x00000002, ctl_base + CLK_CTRL); |
| 940 | writel(0x00000006, ctl_base + CLK_CTRL); |
| 941 | writel(0x0000000e, ctl_base + CLK_CTRL); |
| 942 | writel(0x0000001e, ctl_base + CLK_CTRL); |
| 943 | writel(0x0000023f, ctl_base + CLK_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 944 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 945 | writel(0, ctl_base + CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 946 | |
Padmanabhan Komanduru | 7860be5 | 2014-03-18 19:07:36 +0530 | [diff] [blame] | 947 | writel(0x13ff3fe0, ctl_base + ERR_INT_MASK0); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 948 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 949 | writel(0x02020202, ctl_base + INT_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 950 | |
| 951 | writel(((disp_width + hsync_porch0_bp) << 16) | hsync_porch0_bp, |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 952 | ctl_base + VIDEO_MODE_ACTIVE_H); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 953 | |
| 954 | writel(((disp_height + vsync_porch0_bp) << 16) | (vsync_porch0_bp), |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 955 | ctl_base + VIDEO_MODE_ACTIVE_V); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 956 | |
Terence Hampson | 7385f6a | 2013-08-16 15:31:25 -0400 | [diff] [blame] | 957 | if (mdp_get_revision() >= MDP_REV_41 || |
| 958 | mdp_get_revision() == MDP_REV_304) { |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 959 | writel(((disp_height + vsync_porch0_fp |
| 960 | + vsync_porch0_bp - 1) << 16) |
| 961 | | (disp_width + hsync_porch0_fp |
| 962 | + hsync_porch0_bp - 1), |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 963 | ctl_base + VIDEO_MODE_TOTAL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 964 | } else { |
| 965 | writel(((disp_height + vsync_porch0_fp |
| 966 | + vsync_porch0_bp) << 16) |
| 967 | | (disp_width + hsync_porch0_fp |
| 968 | + hsync_porch0_bp), |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 969 | ctl_base + VIDEO_MODE_TOTAL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 970 | } |
| 971 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 972 | writel((hsync_width << 16) | 0, ctl_base + VIDEO_MODE_HSYNC); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 973 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 974 | writel(0 << 16 | 0, ctl_base + VIDEO_MODE_VSYNC); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 975 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 976 | writel(vsync_width << 16 | 0, ctl_base + VIDEO_MODE_VSYNC_VPOS); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 977 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 978 | writel(0x0, ctl_base + EOT_PACKET_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 979 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 980 | writel(0x00000100, ctl_base + MISR_VIDEO_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 981 | |
| 982 | if (mdp_get_revision() >= MDP_REV_41) { |
| 983 | writel(low_pwr_stop_mode << 16 | |
| 984 | eof_bllp_pwr << 12 | traffic_mode << 8 |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 985 | | dst_format << 4 | 0x0, ctl_base + VIDEO_MODE_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 986 | } else { |
| 987 | writel(1 << 28 | 1 << 24 | 1 << 20 | low_pwr_stop_mode << 16 | |
| 988 | eof_bllp_pwr << 12 | traffic_mode << 8 |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 989 | | dst_format << 4 | 0x0, ctl_base + VIDEO_MODE_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 990 | } |
| 991 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 992 | writel(0x3fd08, ctl_base + HS_TIMER_CTRL); |
| 993 | writel(0x00010100, ctl_base + MISR_VIDEO_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 994 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 995 | writel(0x00010100, ctl_base + INT_CTRL); |
| 996 | writel(0x02010202, ctl_base + INT_CTRL); |
| 997 | writel(0x02030303, ctl_base + INT_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 998 | |
| 999 | writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4 |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 1000 | | 0x103, ctl_base + CTRL); |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 1001 | #endif |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 1002 | |
| 1003 | return status; |
| 1004 | } |
| 1005 | |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 1006 | int mdss_dsi_config(struct msm_fb_panel_data *panel) |
| 1007 | { |
| 1008 | int ret = NO_ERROR; |
| 1009 | struct msm_panel_info *pinfo; |
| 1010 | struct mipi_dsi_panel_config mipi_pinfo; |
| 1011 | |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 1012 | #if (DISPLAY_TYPE_MDSS == 1) |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 1013 | if (!panel) |
| 1014 | return ERR_INVALID_ARGS; |
| 1015 | |
| 1016 | pinfo = &(panel->panel_info); |
| 1017 | mipi_pinfo.mode = pinfo->mipi.mode; |
| 1018 | mipi_pinfo.num_of_lanes = pinfo->mipi.num_of_lanes; |
| 1019 | mipi_pinfo.mdss_dsi_phy_config = pinfo->mipi.mdss_dsi_phy_db; |
| 1020 | mipi_pinfo.panel_cmds = pinfo->mipi.panel_cmds; |
| 1021 | mipi_pinfo.num_of_panel_cmds = pinfo->mipi.num_of_panel_cmds; |
| 1022 | mipi_pinfo.lane_swap = pinfo->mipi.lane_swap; |
| 1023 | mipi_pinfo.pack = 0; |
Siddhartha Agrawal | b6c861f | 2013-05-31 19:36:44 -0700 | [diff] [blame] | 1024 | mipi_pinfo.t_clk_pre = pinfo->mipi.t_clk_pre; |
| 1025 | mipi_pinfo.t_clk_post = pinfo->mipi.t_clk_post; |
Casey Piper | 8403675 | 2013-09-05 14:56:37 -0700 | [diff] [blame] | 1026 | mipi_pinfo.signature = pinfo->mipi.signature; |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 1027 | |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame^] | 1028 | mdss_dsi_phy_init(&mipi_pinfo, MIPI_DSI0_BASE, DSI0_PHY_BASE); |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 1029 | if (pinfo->mipi.dual_dsi) |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame^] | 1030 | mdss_dsi_phy_init(&mipi_pinfo, MIPI_DSI1_BASE, DSI1_PHY_BASE); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 1031 | |
Ray Zhang | 4c7e37f | 2013-12-03 17:04:55 +0800 | [diff] [blame] | 1032 | ret = mdss_dsi_host_init(&mipi_pinfo, pinfo->mipi.broadcast); |
| 1033 | if (ret) { |
| 1034 | dprintf(CRITICAL, "dsi host init error\n"); |
| 1035 | goto error; |
| 1036 | } |
| 1037 | |
| 1038 | if (panel->pre_init_func) { |
| 1039 | ret = panel->pre_init_func(); |
| 1040 | if (ret) { |
| 1041 | dprintf(CRITICAL, "pre_init_func error\n"); |
| 1042 | goto error; |
| 1043 | } |
| 1044 | } |
| 1045 | |
| 1046 | ret = mdss_dsi_panel_initialize(&mipi_pinfo, pinfo->mipi.broadcast); |
| 1047 | if (ret) { |
| 1048 | dprintf(CRITICAL, "dsi panel init error\n"); |
| 1049 | goto error; |
| 1050 | } |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 1051 | |
| 1052 | if (pinfo->rotate && panel->rotate) |
| 1053 | pinfo->rotate(); |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 1054 | #endif |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 1055 | |
Ray Zhang | 4c7e37f | 2013-12-03 17:04:55 +0800 | [diff] [blame] | 1056 | error: |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 1057 | return ret; |
| 1058 | } |
| 1059 | |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 1060 | int mipi_dsi_video_mode_config(unsigned short disp_width, |
| 1061 | unsigned short disp_height, |
| 1062 | unsigned short img_width, |
| 1063 | unsigned short img_height, |
| 1064 | unsigned short hsync_porch0_fp, |
| 1065 | unsigned short hsync_porch0_bp, |
| 1066 | unsigned short vsync_porch0_fp, |
| 1067 | unsigned short vsync_porch0_bp, |
| 1068 | unsigned short hsync_width, |
| 1069 | unsigned short vsync_width, |
| 1070 | unsigned short dst_format, |
| 1071 | unsigned short traffic_mode, |
| 1072 | unsigned char lane_en, |
| 1073 | unsigned low_pwr_stop_mode, |
| 1074 | unsigned char eof_bllp_pwr, |
| 1075 | unsigned char interleav) |
| 1076 | { |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 1077 | int status = 0; |
| 1078 | |
| 1079 | /* disable mdp first */ |
| 1080 | mdp_disable(); |
| 1081 | |
| 1082 | writel(0x00000000, DSI_CLK_CTRL); |
| 1083 | writel(0x00000000, DSI_CLK_CTRL); |
| 1084 | writel(0x00000000, DSI_CLK_CTRL); |
| 1085 | writel(0x00000000, DSI_CLK_CTRL); |
| 1086 | writel(0x00000002, DSI_CLK_CTRL); |
| 1087 | writel(0x00000006, DSI_CLK_CTRL); |
| 1088 | writel(0x0000000e, DSI_CLK_CTRL); |
| 1089 | writel(0x0000001e, DSI_CLK_CTRL); |
Chandan Uddaraju | eb1decb | 2013-04-23 14:27:49 -0700 | [diff] [blame] | 1090 | writel(0x0000023f, DSI_CLK_CTRL); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 1091 | |
| 1092 | writel(0, DSI_CTRL); |
| 1093 | |
Padmanabhan Komanduru | 7860be5 | 2014-03-18 19:07:36 +0530 | [diff] [blame] | 1094 | writel(0x13ff3fe0, DSI_ERR_INT_MASK0); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 1095 | |
| 1096 | writel(0x02020202, DSI_INT_CTRL); |
| 1097 | |
| 1098 | writel(((disp_width + hsync_porch0_bp) << 16) | hsync_porch0_bp, |
| 1099 | DSI_VIDEO_MODE_ACTIVE_H); |
| 1100 | |
| 1101 | writel(((disp_height + vsync_porch0_bp) << 16) | (vsync_porch0_bp), |
| 1102 | DSI_VIDEO_MODE_ACTIVE_V); |
| 1103 | |
| 1104 | if (mdp_get_revision() >= MDP_REV_41) { |
| 1105 | writel(((disp_height + vsync_porch0_fp |
| 1106 | + vsync_porch0_bp - 1) << 16) |
| 1107 | | (disp_width + hsync_porch0_fp |
| 1108 | + hsync_porch0_bp - 1), |
| 1109 | DSI_VIDEO_MODE_TOTAL); |
| 1110 | } else { |
| 1111 | writel(((disp_height + vsync_porch0_fp |
| 1112 | + vsync_porch0_bp) << 16) |
| 1113 | | (disp_width + hsync_porch0_fp |
| 1114 | + hsync_porch0_bp), |
| 1115 | DSI_VIDEO_MODE_TOTAL); |
| 1116 | } |
| 1117 | |
| 1118 | writel((hsync_width << 16) | 0, DSI_VIDEO_MODE_HSYNC); |
| 1119 | |
| 1120 | writel(0 << 16 | 0, DSI_VIDEO_MODE_VSYNC); |
| 1121 | |
| 1122 | writel(vsync_width << 16 | 0, DSI_VIDEO_MODE_VSYNC_VPOS); |
| 1123 | |
Chandan Uddaraju | eb1decb | 2013-04-23 14:27:49 -0700 | [diff] [blame] | 1124 | writel(0x0, DSI_EOT_PACKET_CTRL); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 1125 | |
| 1126 | writel(0x00000100, DSI_MISR_VIDEO_CTRL); |
| 1127 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 1128 | if (mdp_get_revision() >= MDP_REV_41) { |
| 1129 | writel(low_pwr_stop_mode << 16 | |
| 1130 | eof_bllp_pwr << 12 | traffic_mode << 8 |
| 1131 | | dst_format << 4 | 0x0, DSI_VIDEO_MODE_CTRL); |
| 1132 | } else { |
| 1133 | writel(1 << 28 | 1 << 24 | 1 << 20 | low_pwr_stop_mode << 16 | |
| 1134 | eof_bllp_pwr << 12 | traffic_mode << 8 |
| 1135 | | dst_format << 4 | 0x0, DSI_VIDEO_MODE_CTRL); |
| 1136 | } |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 1137 | |
Chandan Uddaraju | eb1decb | 2013-04-23 14:27:49 -0700 | [diff] [blame] | 1138 | writel(0x3fd08, DSI_HS_TIMER_CTRL); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 1139 | writel(0x67, DSI_CAL_STRENGTH_CTRL); |
| 1140 | writel(0x80006711, DSI_CAL_CTRL); |
| 1141 | writel(0x00010100, DSI_MISR_VIDEO_CTRL); |
| 1142 | |
| 1143 | writel(0x00010100, DSI_INT_CTRL); |
| 1144 | writel(0x02010202, DSI_INT_CTRL); |
| 1145 | writel(0x02030303, DSI_INT_CTRL); |
| 1146 | |
| 1147 | writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4 |
| 1148 | | 0x103, DSI_CTRL); |
| 1149 | |
| 1150 | return status; |
| 1151 | } |
| 1152 | |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 1153 | int mdss_dsi_cmd_mode_config(uint16_t disp_width, |
| 1154 | uint16_t disp_height, |
| 1155 | uint16_t img_width, |
| 1156 | uint16_t img_height, |
| 1157 | uint16_t dst_format, |
Xiaoming Zhou | 8d534dd | 2013-07-29 15:49:19 -0400 | [diff] [blame] | 1158 | uint8_t ystride, |
| 1159 | uint8_t lane_en, |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 1160 | uint8_t interleav, |
| 1161 | uint32_t ctl_base) |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 1162 | { |
Xiaoming Zhou | 8d534dd | 2013-07-29 15:49:19 -0400 | [diff] [blame] | 1163 | uint16_t dst_fmt = 0; |
| 1164 | |
| 1165 | switch (dst_format) { |
| 1166 | case DSI_VIDEO_DST_FORMAT_RGB565: |
| 1167 | dst_fmt = DSI_CMD_DST_FORMAT_RGB565; |
| 1168 | break; |
| 1169 | case DSI_VIDEO_DST_FORMAT_RGB666: |
| 1170 | case DSI_VIDEO_DST_FORMAT_RGB666_LOOSE: |
| 1171 | dst_fmt = DSI_CMD_DST_FORMAT_RGB666; |
| 1172 | break; |
| 1173 | case DSI_VIDEO_DST_FORMAT_RGB888: |
| 1174 | dst_fmt = DSI_CMD_DST_FORMAT_RGB888; |
| 1175 | break; |
| 1176 | default: |
| 1177 | dprintf(CRITICAL, "unsupported dst format\n"); |
| 1178 | return ERROR; |
| 1179 | } |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 1180 | |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 1181 | #if (DISPLAY_TYPE_MDSS == 1) |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 1182 | writel(0x00000000, ctl_base + CLK_CTRL); |
| 1183 | writel(0x00000000, ctl_base + CLK_CTRL); |
| 1184 | writel(0x00000000, ctl_base + CLK_CTRL); |
| 1185 | writel(0x00000000, ctl_base + CLK_CTRL); |
| 1186 | writel(0x00000002, ctl_base + CLK_CTRL); |
| 1187 | writel(0x00000006, ctl_base + CLK_CTRL); |
| 1188 | writel(0x0000000e, ctl_base + CLK_CTRL); |
| 1189 | writel(0x0000001e, ctl_base + CLK_CTRL); |
| 1190 | writel(0x0000023f, ctl_base + CLK_CTRL); |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 1191 | |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 1192 | writel(0, ctl_base + CTRL); |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 1193 | |
Padmanabhan Komanduru | 7860be5 | 2014-03-18 19:07:36 +0530 | [diff] [blame] | 1194 | writel(0x13ff3fe0, ctl_base + ERR_INT_MASK0); |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 1195 | |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 1196 | writel(0x02020202, ctl_base + INT_CTRL); |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 1197 | |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 1198 | writel(dst_fmt, ctl_base + COMMAND_MODE_MDP_CTRL); |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 1199 | writel((img_width * ystride + 1) << 16 | 0x0039, |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 1200 | ctl_base + COMMAND_MODE_MDP_STREAM0_CTRL); |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 1201 | writel((img_width * ystride + 1) << 16 | 0x0039, |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 1202 | ctl_base + COMMAND_MODE_MDP_STREAM1_CTRL); |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 1203 | writel(img_height << 16 | img_width, |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 1204 | ctl_base + COMMAND_MODE_MDP_STREAM0_TOTAL); |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 1205 | writel(img_height << 16 | img_width, |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 1206 | ctl_base + COMMAND_MODE_MDP_STREAM1_TOTAL); |
| 1207 | writel(0x13c2c, ctl_base + COMMAND_MODE_MDP_DCS_CMD_CTRL); |
Xiaoming Zhou | 8d534dd | 2013-07-29 15:49:19 -0400 | [diff] [blame] | 1208 | writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4 | 0x105, |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 1209 | ctl_base + CTRL); |
Padmanabhan Komanduru | 7860be5 | 2014-03-18 19:07:36 +0530 | [diff] [blame] | 1210 | writel(0x14000000, ctl_base + COMMAND_MODE_DMA_CTRL); |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 1211 | writel(0x10000000, ctl_base + MISR_CMD_CTRL); |
Xiaoming Zhou | a046933 | 2014-03-04 18:34:24 -0500 | [diff] [blame] | 1212 | writel(0x1, ctl_base + EOT_PACKET_CTRL); |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 1213 | #endif |
Xiaoming Zhou | 8d534dd | 2013-07-29 15:49:19 -0400 | [diff] [blame] | 1214 | return 0; |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 1215 | } |
| 1216 | |
Channagoud Kadabi | 10189fd | 2012-05-25 13:33:39 +0530 | [diff] [blame] | 1217 | int mipi_dsi_cmd_mode_config(unsigned short disp_width, |
| 1218 | unsigned short disp_height, |
| 1219 | unsigned short img_width, |
| 1220 | unsigned short img_height, |
| 1221 | unsigned short dst_format, |
| 1222 | unsigned short traffic_mode) |
| 1223 | { |
| 1224 | unsigned char DST_FORMAT; |
| 1225 | unsigned char TRAFIC_MODE; |
| 1226 | unsigned char DLNx_EN; |
| 1227 | // video mode data ctrl |
| 1228 | int status = 0; |
| 1229 | unsigned char interleav = 0; |
| 1230 | unsigned char ystride = 0x03; |
| 1231 | // disable mdp first |
| 1232 | |
| 1233 | writel(0x00000000, DSI_CLK_CTRL); |
| 1234 | writel(0x00000000, DSI_CLK_CTRL); |
| 1235 | writel(0x00000000, DSI_CLK_CTRL); |
| 1236 | writel(0x00000000, DSI_CLK_CTRL); |
| 1237 | writel(0x00000002, DSI_CLK_CTRL); |
| 1238 | writel(0x00000006, DSI_CLK_CTRL); |
| 1239 | writel(0x0000000e, DSI_CLK_CTRL); |
| 1240 | writel(0x0000001e, DSI_CLK_CTRL); |
| 1241 | writel(0x0000003e, DSI_CLK_CTRL); |
| 1242 | |
Padmanabhan Komanduru | 7860be5 | 2014-03-18 19:07:36 +0530 | [diff] [blame] | 1243 | writel(0x13ff3fe0, DSI_ERR_INT_MASK0); |
Channagoud Kadabi | 10189fd | 2012-05-25 13:33:39 +0530 | [diff] [blame] | 1244 | |
| 1245 | |
| 1246 | DST_FORMAT = 8; // RGB888 |
| 1247 | dprintf(SPEW, "DSI_Cmd_Mode - Dst Format: RGB888\n"); |
| 1248 | |
| 1249 | DLNx_EN = 3; // 2 lane with clk programming |
| 1250 | dprintf(SPEW, "Data Lane: 2 lane\n"); |
| 1251 | |
| 1252 | TRAFIC_MODE = 0; // non burst mode with sync pulses |
| 1253 | dprintf(SPEW, "Traffic mode: non burst mode with sync pulses\n"); |
| 1254 | |
| 1255 | writel(0x02020202, DSI_INT_CTRL); |
| 1256 | |
| 1257 | writel(0x00100000 | DST_FORMAT, DSI_COMMAND_MODE_MDP_CTRL); |
| 1258 | writel((img_width * ystride + 1) << 16 | 0x0039, |
| 1259 | DSI_COMMAND_MODE_MDP_STREAM0_CTRL); |
| 1260 | writel((img_width * ystride + 1) << 16 | 0x0039, |
| 1261 | DSI_COMMAND_MODE_MDP_STREAM1_CTRL); |
| 1262 | writel(img_height << 16 | img_width, |
| 1263 | DSI_COMMAND_MODE_MDP_STREAM0_TOTAL); |
| 1264 | writel(img_height << 16 | img_width, |
| 1265 | DSI_COMMAND_MODE_MDP_STREAM1_TOTAL); |
| 1266 | writel(0xEE, DSI_CAL_STRENGTH_CTRL); |
| 1267 | writel(0x80000000, DSI_CAL_CTRL); |
| 1268 | writel(0x40, DSI_TRIG_CTRL); |
| 1269 | writel(0x13c2c, DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL); |
| 1270 | writel(interleav << 30 | 0 << 24 | 0 << 20 | DLNx_EN << 4 | 0x105, |
| 1271 | DSI_CTRL); |
Padmanabhan Komanduru | 7860be5 | 2014-03-18 19:07:36 +0530 | [diff] [blame] | 1272 | writel(0x14000000, DSI_COMMAND_MODE_DMA_CTRL); |
Channagoud Kadabi | 10189fd | 2012-05-25 13:33:39 +0530 | [diff] [blame] | 1273 | writel(0x10000000, DSI_MISR_CMD_CTRL); |
Padmanabhan Komanduru | 7860be5 | 2014-03-18 19:07:36 +0530 | [diff] [blame] | 1274 | writel(0x13ff3fe0, DSI_ERR_INT_MASK0); |
Channagoud Kadabi | 10189fd | 2012-05-25 13:33:39 +0530 | [diff] [blame] | 1275 | writel(0x1, DSI_EOT_PACKET_CTRL); |
| 1276 | |
| 1277 | return NO_ERROR; |
| 1278 | } |
| 1279 | |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 1280 | int mipi_dsi_on() |
| 1281 | { |
| 1282 | int ret = NO_ERROR; |
| 1283 | unsigned long ReadValue; |
| 1284 | unsigned long count = 0; |
| 1285 | |
| 1286 | ReadValue = readl(DSI_INT_CTRL) & 0x00010000; |
| 1287 | |
| 1288 | mdelay(10); |
| 1289 | |
| 1290 | while (ReadValue != 0x00010000) { |
| 1291 | ReadValue = readl(DSI_INT_CTRL) & 0x00010000; |
| 1292 | count++; |
| 1293 | if (count > 0xffff) { |
| 1294 | dprintf(CRITICAL, "Video lane test failed\n"); |
| 1295 | return ERROR; |
| 1296 | } |
| 1297 | } |
| 1298 | |
Amir Samuelov | 2d4ba16 | 2012-07-22 11:53:14 +0300 | [diff] [blame] | 1299 | dprintf(INFO, "Video lane tested successfully\n"); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 1300 | return ret; |
| 1301 | } |
| 1302 | |
Siddhartha Agrawal | 24d81b5 | 2013-07-01 11:13:32 -0700 | [diff] [blame] | 1303 | int mipi_dsi_off(struct msm_panel_info *pinfo) |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 1304 | { |
Amol Jadi | 6834f1a | 2012-06-29 14:42:59 -0700 | [diff] [blame] | 1305 | if(!target_cont_splash_screen()) |
| 1306 | { |
| 1307 | writel(0, DSI_CLK_CTRL); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 1308 | writel(0x1F1, DSI_CTRL); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 1309 | mdelay(10); |
| 1310 | writel(0x0001, DSI_SOFT_RESET); |
| 1311 | writel(0x0000, DSI_SOFT_RESET); |
Siddhartha Agrawal | e0033a1 | 2013-02-23 15:37:42 -0800 | [diff] [blame] | 1312 | writel(0x1115501, DSI_INT_CTRL); |
Amol Jadi | 6834f1a | 2012-06-29 14:42:59 -0700 | [diff] [blame] | 1313 | writel(0, DSI_CTRL); |
Siddhartha Agrawal | e0033a1 | 2013-02-23 15:37:42 -0800 | [diff] [blame] | 1314 | } |
| 1315 | |
| 1316 | writel(0x1115501, DSI_INT_CTRL); |
Siddhartha Agrawal | 24d81b5 | 2013-07-01 11:13:32 -0700 | [diff] [blame] | 1317 | if (pinfo->mipi.broadcast) |
| 1318 | writel(0x1115501, DSI_INT_CTRL + 0x600); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 1319 | |
| 1320 | return NO_ERROR; |
| 1321 | } |
Channagoud Kadabi | 10189fd | 2012-05-25 13:33:39 +0530 | [diff] [blame] | 1322 | |
| 1323 | int mipi_cmd_trigger() |
| 1324 | { |
| 1325 | writel(0x1, DSI_CMD_MODE_MDP_SW_TRIGGER); |
| 1326 | |
| 1327 | return NO_ERROR; |
| 1328 | } |