Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2009-2012, The Linux Foundation. All rights reserved. |
Shashank Mittal | 23b8f42 | 2010-04-16 19:27:21 -0700 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
Shashank Mittal | 23b8f42 | 2010-04-16 19:27:21 -0700 | [diff] [blame] | 15 | * |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Shashank Mittal | 23b8f42 | 2010-04-16 19:27:21 -0700 | [diff] [blame] | 27 | */ |
| 28 | |
| 29 | #include <stdint.h> |
| 30 | #include <debug.h> |
Amol Jadi | c52c8a3 | 2011-07-12 11:27:04 -0700 | [diff] [blame] | 31 | #include <reg.h> |
Shashank Mittal | 23b8f42 | 2010-04-16 19:27:21 -0700 | [diff] [blame] | 32 | #include <kernel/thread.h> |
| 33 | #include <platform/iomap.h> |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 34 | #include <platform/clock.h> |
Ajay Dudani | 8534b1a | 2011-01-26 11:35:39 -0800 | [diff] [blame] | 35 | #include <platform/scm-io.h> |
Amol Jadi | c52c8a3 | 2011-07-12 11:27:04 -0700 | [diff] [blame] | 36 | #include <uart_dm.h> |
| 37 | #include <gsbi.h> |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 38 | #include <mmc.h> |
Shashank Mittal | 23b8f42 | 2010-04-16 19:27:21 -0700 | [diff] [blame] | 39 | |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 40 | /* Read, modify, then write-back a register. */ |
| 41 | static void rmwreg(uint32_t val, uint32_t reg, uint32_t mask) |
| 42 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 43 | uint32_t regval = readl(reg); |
| 44 | regval &= ~mask; |
| 45 | regval |= val; |
| 46 | writel(regval, reg); |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 47 | } |
| 48 | |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 49 | /* Enable/disable for non-shared NT PLLs. */ |
| 50 | int nt_pll_enable(uint8_t src, uint8_t enable) |
| 51 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 52 | static const struct { |
| 53 | uint32_t const mode_reg; |
| 54 | uint32_t const status_reg; |
| 55 | } pll_reg[] = { |
| 56 | [PLL_1] = { |
| 57 | MM_PLL0_MODE_REG, MM_PLL0_STATUS_REG},[PLL_2] = { |
| 58 | MM_PLL1_MODE_REG, MM_PLL1_STATUS_REG},[PLL_3] = { |
| 59 | MM_PLL2_MODE_REG, MM_PLL2_STATUS_REG},}; |
| 60 | uint32_t pll_mode; |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 61 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 62 | pll_mode = secure_readl(pll_reg[src].mode_reg); |
| 63 | if (enable) { |
| 64 | /* Disable PLL bypass mode. */ |
| 65 | pll_mode |= (1 << 1); |
| 66 | secure_writel(pll_mode, pll_reg[src].mode_reg); |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 67 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 68 | /* H/W requires a 5us delay between disabling the bypass and |
| 69 | * de-asserting the reset. Delay 10us just to be safe. */ |
| 70 | udelay(10); |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 71 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 72 | /* De-assert active-low PLL reset. */ |
| 73 | pll_mode |= (1 << 2); |
| 74 | secure_writel(pll_mode, pll_reg[src].mode_reg); |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 75 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 76 | /* Enable PLL output. */ |
| 77 | pll_mode |= (1 << 0); |
| 78 | secure_writel(pll_mode, pll_reg[src].mode_reg); |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 79 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 80 | /* Wait until PLL is enabled. */ |
| 81 | while (!secure_readl(pll_reg[src].status_reg)) ; |
| 82 | } else { |
| 83 | /* Disable the PLL output, disable test mode, enable |
| 84 | * the bypass mode, and assert the reset. */ |
| 85 | pll_mode &= 0xFFFFFFF0; |
| 86 | secure_writel(pll_mode, pll_reg[src].mode_reg); |
| 87 | } |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 88 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 89 | return 0; |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 90 | } |
| 91 | |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 92 | /* Write the M,N,D values and enable the MDP Core Clock */ |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 93 | void config_mdp_clk(uint32_t ns, |
| 94 | uint32_t md, |
| 95 | uint32_t cc, |
| 96 | uint32_t ns_addr, uint32_t md_addr, uint32_t cc_addr) |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 97 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 98 | unsigned int val = 0; |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 99 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 100 | /* MN counter reset */ |
| 101 | val = 1 << 31; |
| 102 | secure_writel(val, ns_addr); |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 103 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 104 | /* Write the MD and CC register values */ |
| 105 | secure_writel(md, md_addr); |
| 106 | secure_writel(cc, cc_addr); |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 107 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 108 | /* Reset the clk control, and Write ns val */ |
| 109 | val = 1 << 31; |
| 110 | val |= ns; |
| 111 | secure_writel(val, ns_addr); |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 112 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 113 | /* Clear MN counter reset */ |
| 114 | val = 1 << 31; |
| 115 | val = ~val; |
| 116 | val = val & secure_readl(ns_addr); |
| 117 | secure_writel(val, ns_addr); |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 118 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 119 | /* Enable MND counter */ |
| 120 | val = 1 << 8; |
| 121 | val = val | secure_readl(cc_addr); |
| 122 | secure_writel(val, cc_addr); |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 123 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 124 | /* Enable the root of the clock tree */ |
| 125 | val = 1 << 2; |
| 126 | val = val | secure_readl(cc_addr); |
| 127 | secure_writel(val, cc_addr); |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 128 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 129 | /* Enable the MDP Clock */ |
| 130 | val = 1 << 0; |
| 131 | val = val | secure_readl(cc_addr); |
| 132 | secure_writel(val, cc_addr); |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 133 | } |
| 134 | |
| 135 | /* Write the M,N,D values and enable the Pixel Core Clock */ |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 136 | void config_pixel_clk(uint32_t ns, |
| 137 | uint32_t md, |
| 138 | uint32_t cc, |
| 139 | uint32_t ns_addr, uint32_t md_addr, uint32_t cc_addr) |
| 140 | { |
| 141 | unsigned int val = 0; |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 142 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 143 | /* Activate the reset for the M/N Counter */ |
| 144 | val = 1 << 7; |
| 145 | secure_writel(val, ns_addr); |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 146 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 147 | /* Write the MD and CC register values */ |
| 148 | secure_writel(md, md_addr); |
| 149 | secure_writel(cc, cc_addr); |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 150 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 151 | /* Write the ns value, and active reset for M/N Counter, again */ |
| 152 | val = 1 << 7; |
| 153 | val |= ns; |
| 154 | secure_writel(val, ns_addr); |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 155 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 156 | /* De-activate the reset for M/N Counter */ |
| 157 | val = 1 << 7; |
| 158 | val = ~val; |
| 159 | val = val & secure_readl(ns_addr); |
| 160 | secure_writel(val, ns_addr); |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 161 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 162 | /* Enable MND counter */ |
| 163 | val = 1 << 5; |
| 164 | val = val | secure_readl(cc_addr); |
| 165 | secure_writel(val, cc_addr); |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 166 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 167 | /* Enable the root of the clock tree */ |
| 168 | val = 1 << 2; |
| 169 | val = val | secure_readl(cc_addr); |
| 170 | secure_writel(val, cc_addr); |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 171 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 172 | /* Enable the MDP Clock */ |
| 173 | val = 1 << 0; |
| 174 | val = val | secure_readl(cc_addr); |
| 175 | secure_writel(val, cc_addr); |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 176 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 177 | /* Enable the LCDC Clock */ |
| 178 | val = 1 << 8; |
| 179 | val = val | secure_readl(cc_addr); |
| 180 | secure_writel(val, cc_addr); |
Shashank Mittal | 402d097 | 2010-09-29 10:09:52 -0700 | [diff] [blame] | 181 | } |
| 182 | |
Shashank Mittal | c69512e | 2010-09-22 16:40:48 -0700 | [diff] [blame] | 183 | /* Set rate and enable the clock */ |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 184 | void clock_config(uint32_t ns, uint32_t md, uint32_t ns_addr, uint32_t md_addr) |
Shashank Mittal | c69512e | 2010-09-22 16:40:48 -0700 | [diff] [blame] | 185 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 186 | unsigned int val = 0; |
Shashank Mittal | c69512e | 2010-09-22 16:40:48 -0700 | [diff] [blame] | 187 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 188 | /* Activate the reset for the M/N Counter */ |
| 189 | val = 1 << 7; |
| 190 | writel(val, ns_addr); |
Shashank Mittal | c69512e | 2010-09-22 16:40:48 -0700 | [diff] [blame] | 191 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 192 | /* Write the MD value into the MD register */ |
| 193 | writel(md, md_addr); |
Shashank Mittal | c69512e | 2010-09-22 16:40:48 -0700 | [diff] [blame] | 194 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 195 | /* Write the ns value, and active reset for M/N Counter, again */ |
| 196 | val = 1 << 7; |
| 197 | val |= ns; |
| 198 | writel(val, ns_addr); |
Shashank Mittal | c69512e | 2010-09-22 16:40:48 -0700 | [diff] [blame] | 199 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 200 | /* De-activate the reset for M/N Counter */ |
| 201 | val = 1 << 7; |
| 202 | val = ~val; |
| 203 | val = val & readl(ns_addr); |
| 204 | writel(val, ns_addr); |
Shashank Mittal | c69512e | 2010-09-22 16:40:48 -0700 | [diff] [blame] | 205 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 206 | /* Enable the M/N Counter */ |
| 207 | val = 1 << 8; |
| 208 | val = val | readl(ns_addr); |
| 209 | writel(val, ns_addr); |
Shashank Mittal | c69512e | 2010-09-22 16:40:48 -0700 | [diff] [blame] | 210 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 211 | /* Enable the Clock Root */ |
| 212 | val = 1 << 11; |
| 213 | val = val | readl(ns_addr); |
| 214 | writel(val, ns_addr); |
Shashank Mittal | c69512e | 2010-09-22 16:40:48 -0700 | [diff] [blame] | 215 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 216 | /* Enable the Clock Branch */ |
| 217 | val = 1 << 9; |
| 218 | val = val | readl(ns_addr); |
| 219 | writel(val, ns_addr); |
Shashank Mittal | c69512e | 2010-09-22 16:40:48 -0700 | [diff] [blame] | 220 | } |
| 221 | |
Shashank Mittal | ed17773 | 2011-05-06 19:12:59 -0700 | [diff] [blame] | 222 | void pll8_enable(void) |
Shashank Mittal | 23b8f42 | 2010-04-16 19:27:21 -0700 | [diff] [blame] | 223 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 224 | /* Currently both UART and USB depend on this PLL8 clock initialization. */ |
| 225 | unsigned int curr_value = 0; |
Shashank Mittal | ed17773 | 2011-05-06 19:12:59 -0700 | [diff] [blame] | 226 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 227 | /* Vote for PLL8 to be enabled */ |
| 228 | curr_value = readl(MSM_BOOT_PLL_ENABLE_SC0); |
| 229 | curr_value |= (1 << 8); |
| 230 | writel(curr_value, MSM_BOOT_PLL_ENABLE_SC0); |
Shashank Mittal | ed17773 | 2011-05-06 19:12:59 -0700 | [diff] [blame] | 231 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 232 | /* Proceed only after PLL is enabled */ |
| 233 | while (!(readl(MSM_BOOT_PLL8_STATUS) & (1 << 16))) ; |
Shashank Mittal | ed17773 | 2011-05-06 19:12:59 -0700 | [diff] [blame] | 234 | } |
| 235 | |
| 236 | void uart_clock_init(void) |
| 237 | { |
| 238 | /* Enable PLL8 */ |
| 239 | pll8_enable(); |
Shashank Mittal | 23b8f42 | 2010-04-16 19:27:21 -0700 | [diff] [blame] | 240 | } |
Ajay Dudani | 7d60552 | 2010-10-01 19:52:37 -0700 | [diff] [blame] | 241 | |
| 242 | void hsusb_clock_init(void) |
| 243 | { |
| 244 | int val; |
Shashank Mittal | ed17773 | 2011-05-06 19:12:59 -0700 | [diff] [blame] | 245 | |
| 246 | /* Enable PLL8 */ |
| 247 | pll8_enable(); |
Ajay Dudani | 7d60552 | 2010-10-01 19:52:37 -0700 | [diff] [blame] | 248 | |
| 249 | //Set 7th bit in NS Register |
| 250 | val = 1 << 7; |
Shashank Mittal | ed17773 | 2011-05-06 19:12:59 -0700 | [diff] [blame] | 251 | writel(val, USB_HS1_XCVR_FS_CLK_NS); |
Ajay Dudani | 7d60552 | 2010-10-01 19:52:37 -0700 | [diff] [blame] | 252 | |
| 253 | //Set rate specific value in MD |
Shashank Mittal | ed17773 | 2011-05-06 19:12:59 -0700 | [diff] [blame] | 254 | writel(0x000500DF, USB_HS1_XCVR_FS_CLK_MD); |
Ajay Dudani | 7d60552 | 2010-10-01 19:52:37 -0700 | [diff] [blame] | 255 | |
| 256 | //Set value in NS register |
| 257 | val = 1 << 7; |
| 258 | val |= 0x00E400C3; |
Shashank Mittal | ed17773 | 2011-05-06 19:12:59 -0700 | [diff] [blame] | 259 | writel(val, USB_HS1_XCVR_FS_CLK_NS); |
Ajay Dudani | 7d60552 | 2010-10-01 19:52:37 -0700 | [diff] [blame] | 260 | |
| 261 | // Clear 7th bit |
| 262 | val = 1 << 7; |
| 263 | val = ~val; |
Shashank Mittal | ed17773 | 2011-05-06 19:12:59 -0700 | [diff] [blame] | 264 | val = val & readl(USB_HS1_XCVR_FS_CLK_NS); |
| 265 | writel(val, USB_HS1_XCVR_FS_CLK_NS); |
Ajay Dudani | 7d60552 | 2010-10-01 19:52:37 -0700 | [diff] [blame] | 266 | |
| 267 | //set 11th bit |
| 268 | val = 1 << 11; |
Shashank Mittal | ed17773 | 2011-05-06 19:12:59 -0700 | [diff] [blame] | 269 | val |= readl(USB_HS1_XCVR_FS_CLK_NS); |
| 270 | writel(val, USB_HS1_XCVR_FS_CLK_NS); |
Ajay Dudani | 7d60552 | 2010-10-01 19:52:37 -0700 | [diff] [blame] | 271 | |
| 272 | //set 9th bit |
| 273 | val = 1 << 9; |
Shashank Mittal | ed17773 | 2011-05-06 19:12:59 -0700 | [diff] [blame] | 274 | val |= readl(USB_HS1_XCVR_FS_CLK_NS); |
| 275 | writel(val, USB_HS1_XCVR_FS_CLK_NS); |
Ajay Dudani | 7d60552 | 2010-10-01 19:52:37 -0700 | [diff] [blame] | 276 | |
| 277 | //set 8th bit |
| 278 | val = 1 << 8; |
Shashank Mittal | ed17773 | 2011-05-06 19:12:59 -0700 | [diff] [blame] | 279 | val |= readl(USB_HS1_XCVR_FS_CLK_NS); |
| 280 | writel(val, USB_HS1_XCVR_FS_CLK_NS); |
Ajay Dudani | 7d60552 | 2010-10-01 19:52:37 -0700 | [diff] [blame] | 281 | } |
| 282 | |
Subbaraman Narayanamurthy | 05872db | 2011-02-28 11:34:58 -0800 | [diff] [blame] | 283 | void ce_clock_init(void) |
| 284 | { |
| 285 | /* Enable clock branch for CE2 */ |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 286 | writel((1 << 4), CE2_HCLK_CTL); |
Subbaraman Narayanamurthy | 05872db | 2011-02-28 11:34:58 -0800 | [diff] [blame] | 287 | return; |
| 288 | } |
Amol Jadi | c52c8a3 | 2011-07-12 11:27:04 -0700 | [diff] [blame] | 289 | |
| 290 | /* Configure UART clock - based on the gsbi id */ |
| 291 | void clock_config_uart_dm(uint8_t id) |
| 292 | { |
| 293 | uint32_t ns = UART_DM_CLK_NS_115200; |
| 294 | uint32_t md = UART_DM_CLK_MD_115200; |
| 295 | |
| 296 | /* Enable PLL8 */ |
| 297 | pll8_enable(); |
| 298 | |
| 299 | /* Enable gsbi_uart_clk */ |
| 300 | clock_config(ns, md, GSBIn_UART_APPS_NS(id), GSBIn_UART_APPS_MD(id)); |
| 301 | |
| 302 | /* Enable the GSBI HCLK */ |
| 303 | writel(GSBI_HCLK_CTL_CLK_ENA << GSBI_HCLK_CTL_S, GSBIn_HCLK_CTL(id)); |
| 304 | } |
| 305 | |
| 306 | /* Configure i2c clock */ |
| 307 | void clock_config_i2c(uint8_t id, uint32_t freq) |
| 308 | { |
| 309 | uint32_t ns; |
| 310 | uint32_t md; |
| 311 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 312 | switch (freq) { |
Amol Jadi | c52c8a3 | 2011-07-12 11:27:04 -0700 | [diff] [blame] | 313 | case 24000000: |
| 314 | ns = I2C_CLK_NS_24MHz; |
| 315 | md = I2C_CLK_MD_24MHz; |
| 316 | break; |
| 317 | default: |
| 318 | ASSERT(0); |
| 319 | } |
| 320 | |
| 321 | clock_config(ns, md, GSBIn_QUP_APPS_NS(id), GSBIn_QUP_APPS_MD(id)); |
| 322 | |
| 323 | /* Enable the GSBI HCLK */ |
| 324 | writel(GSBI_HCLK_CTL_CLK_ENA << GSBI_HCLK_CTL_S, GSBIn_HCLK_CTL(id)); |
| 325 | } |
| 326 | |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 327 | /* Intialize MMC clock */ |
| 328 | void clock_init_mmc(uint32_t interface) |
| 329 | { |
| 330 | /* Nothing to be done. */ |
| 331 | } |
| 332 | |
| 333 | /* Configure MMC clock */ |
| 334 | void clock_config_mmc(uint32_t interface, uint32_t freq) |
| 335 | { |
| 336 | uint32_t reg = 0; |
| 337 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 338 | switch (freq) { |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 339 | case MMC_CLK_400KHZ: |
| 340 | clock_config(SDC_CLK_NS_400KHZ, |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 341 | SDC_CLK_MD_400KHZ, |
| 342 | SDC_NS(interface), SDC_MD(interface)); |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 343 | break; |
| 344 | case MMC_CLK_48MHZ: |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 345 | case MMC_CLK_50MHZ: /* Max supported is 48MHZ */ |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 346 | clock_config(SDC_CLK_NS_48MHZ, |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 347 | SDC_CLK_MD_48MHZ, |
| 348 | SDC_NS(interface), SDC_MD(interface)); |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 349 | break; |
| 350 | default: |
| 351 | ASSERT(0); |
| 352 | |
| 353 | } |
| 354 | |
| 355 | reg |= MMC_BOOT_MCI_CLK_ENABLE; |
| 356 | reg |= MMC_BOOT_MCI_CLK_ENA_FLOW; |
| 357 | reg |= MMC_BOOT_MCI_CLK_IN_FEEDBACK; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 358 | writel(reg, MMC_BOOT_MCI_CLK); |
Channagoud Kadabi | 672c4c4 | 2012-12-20 17:51:45 -0800 | [diff] [blame] | 359 | |
| 360 | /* Wait for the MMC_BOOT_MCI_CLK write to go through. */ |
| 361 | mmc_mclk_reg_wr_delay(); |
| 362 | |
| 363 | /* Wait 1 ms to provide the free running SD CLK to the card. */ |
| 364 | mdelay(1); |
Amol Jadi | 8225456 | 2011-06-27 11:25:48 -0700 | [diff] [blame] | 365 | } |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 366 | |
| 367 | void mdp_clock_init(void) |
| 368 | { |
| 369 | /* Turn on the PLL2, to ramp up the MDP clock to max (200MHz) */ |
| 370 | nt_pll_enable(PLL_2, 1); |
| 371 | |
| 372 | config_mdp_clk(MDP_NS_VAL, MDP_MD_VAL, |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 373 | MDP_CC_VAL, MDP_NS_REG, MDP_MD_REG, MDP_CC_REG); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 374 | } |
| 375 | |
Wentao Xu | 8d6150c | 2011-06-22 11:03:18 -0400 | [diff] [blame] | 376 | void mmss_pixel_clock_configure(uint32_t pclk_id) |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 377 | { |
Wentao Xu | 8d6150c | 2011-06-22 11:03:18 -0400 | [diff] [blame] | 378 | if (pclk_id == PIXEL_CLK_INDEX_25M) { |
| 379 | config_pixel_clk(PIXEL_NS_VAL_25M, PIXEL_MD_VAL_25M, |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 380 | PIXEL_CC_VAL_25M, MMSS_PIXEL_NS_REG, |
| 381 | MMSS_PIXEL_MD_REG, MMSS_PIXEL_CC_REG); |
| 382 | } else { |
Wentao Xu | 8d6150c | 2011-06-22 11:03:18 -0400 | [diff] [blame] | 383 | config_pixel_clk(PIXEL_NS_VAL, PIXEL_MD_VAL, |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 384 | PIXEL_CC_VAL, MMSS_PIXEL_NS_REG, |
| 385 | MMSS_PIXEL_MD_REG, MMSS_PIXEL_CC_REG); |
Wentao Xu | 8d6150c | 2011-06-22 11:03:18 -0400 | [diff] [blame] | 386 | } |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 387 | } |
| 388 | |
| 389 | void configure_dsicore_dsiclk() |
| 390 | { |
| 391 | unsigned char mnd_mode, root_en, clk_en; |
| 392 | unsigned long src_sel = 0x3; // dsi_phy_pll0_src |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 393 | unsigned long pre_div_func = 0x00; // predivide by 1 |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 394 | unsigned long pmxo_sel; |
| 395 | |
| 396 | secure_writel(pre_div_func << 14 | src_sel, DSI_NS_REG); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 397 | mnd_mode = 0; // Bypass MND |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 398 | root_en = 1; |
| 399 | clk_en = 1; |
| 400 | pmxo_sel = 0; |
| 401 | |
| 402 | secure_writel((pmxo_sel << 8) | (mnd_mode << 6), DSI_CC_REG); |
| 403 | secure_writel(secure_readl(DSI_CC_REG) | root_en << 2, DSI_CC_REG); |
| 404 | secure_writel(secure_readl(DSI_CC_REG) | clk_en, DSI_CC_REG); |
| 405 | } |
| 406 | |
| 407 | void configure_dsicore_byteclk(void) |
| 408 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 409 | secure_writel(0x00400401, MISC_CC2_REG); // select pxo |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 410 | } |
| 411 | |
| 412 | void configure_dsicore_pclk(void) |
| 413 | { |
| 414 | unsigned char mnd_mode, root_en, clk_en; |
| 415 | unsigned long src_sel = 0x3; // dsi_phy_pll0_src |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 416 | unsigned long pre_div_func = 0x01; // predivide by 2 |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 417 | |
Shashank Mittal | 3026290 | 2012-02-21 15:37:24 -0800 | [diff] [blame] | 418 | secure_writel(pre_div_func << 12 | src_sel, DSI_PIXEL_NS_REG); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 419 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 420 | mnd_mode = 0; // Bypass MND |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 421 | root_en = 1; |
| 422 | clk_en = 1; |
Shashank Mittal | 3026290 | 2012-02-21 15:37:24 -0800 | [diff] [blame] | 423 | secure_writel(mnd_mode << 6, DSI_PIXEL_CC_REG); |
| 424 | secure_writel(secure_readl(DSI_PIXEL_CC_REG) | root_en << 2, DSI_PIXEL_CC_REG); |
| 425 | secure_writel(secure_readl(DSI_PIXEL_CC_REG) | clk_en, DSI_PIXEL_CC_REG); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 426 | } |
Channagoud Kadabi | 56cd966 | 2012-05-04 13:32:51 +0530 | [diff] [blame] | 427 | /* Async Reset CE2 */ |
| 428 | void ce_async_reset() |
| 429 | { |
| 430 | /* Enable Async reset bit for HCLK CE2 */ |
| 431 | writel((1<<7) | (1 << 4), CE2_HCLK_CTL); |
| 432 | |
| 433 | /* Add a small delay between switching the |
| 434 | * async intput from high to low |
| 435 | */ |
| 436 | udelay(2); |
| 437 | |
| 438 | /* Disable Async reset bit for HCLK for CE2 */ |
| 439 | writel((1 << 4), CE2_HCLK_CTL); |
| 440 | |
| 441 | return; |
| 442 | } |