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Sachin Bhayarea8deb5c2015-07-16 11:49:08 +05301/* Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +05302 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
Padmanabhan Komandurufa4be752012-10-08 16:51:56 +053012 * * Neither the name of The Linux Foundation, Inc. nor the names of its
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +053013 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 */
29#include <mdp3.h>
30#include <debug.h>
31#include <reg.h>
Channagoud Kadabi539ef722012-03-29 16:02:50 +053032#include <msm_panel.h>
33#include <err.h>
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +053034#include <target/display.h>
35#include <platform/timer.h>
36#include <platform/iomap.h>
37
Shashank Mittal4bfb2e32012-04-16 10:56:27 -070038static int mdp_rev;
39
Channagoud Kadabi539ef722012-03-29 16:02:50 +053040int mdp_dsi_video_config(struct msm_panel_info *pinfo,
41 struct fbcon_config *fb)
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +053042{
Ajay Dudanib01e5062011-12-03 23:23:42 -080043 unsigned long hsync_period;
44 unsigned long vsync_period;
45 unsigned long vsync_period_intmd;
Channagoud Kadabi539ef722012-03-29 16:02:50 +053046 struct lcdc_panel_info *lcdc = NULL;
47 int ystride = 3;
Terence Hampson7385f6a2013-08-16 15:31:25 -040048 int mdp_rev = mdp_get_revision();
Channagoud Kadabi539ef722012-03-29 16:02:50 +053049
50 if (pinfo == NULL)
51 return ERR_INVALID_ARGS;
52
53 lcdc = &(pinfo->lcdc);
54 if (lcdc == NULL)
55 return ERR_INVALID_ARGS;
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +053056
Ajay Dudanib01e5062011-12-03 23:23:42 -080057 dprintf(SPEW, "MDP3.0.3 for DSI Video Mode\n");
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +053058
Channagoud Kadabi539ef722012-03-29 16:02:50 +053059 hsync_period = pinfo->xres + lcdc->h_front_porch + \
60 lcdc->h_back_porch + 1;
61 vsync_period_intmd = pinfo->yres + lcdc->v_front_porch + \
62 lcdc->v_back_porch + 1;
Shivaraj Shettyf9e10c42014-09-17 04:21:15 +053063 if (mdp_rev == MDP_REV_304 || mdp_rev == MDP_REV_305) {
Terence Hampson7385f6a2013-08-16 15:31:25 -040064 hsync_period += lcdc->h_pulse_width - 1;
65 vsync_period_intmd += lcdc->v_pulse_width - 1;
66 }
Ajay Dudanib01e5062011-12-03 23:23:42 -080067 vsync_period = vsync_period_intmd * hsync_period;
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +053068
Sandeep Panda09fd9782014-12-26 10:32:01 +053069 /* Program QOS remapper settings */
70 writel(0x1A9, MDP_DMA_P_QOS_REMAPPER);
71 writel(0x0, MDP_DMA_P_WATERMARK_0);
72 writel(0x0, MDP_DMA_P_WATERMARK_1);
73 writel(0x0, MDP_DMA_P_WATERMARK_2);
Sachin Bhayarea8deb5c2015-07-16 11:49:08 +053074 if (pinfo->xres >= 720) {
Sandeep Panda09fd9782014-12-26 10:32:01 +053075 writel(0xFFFF, MDP_PANIC_LUT0);
Sachin Bhayarea8deb5c2015-07-16 11:49:08 +053076 writel(0xFF00, MDP_ROBUST_LUT);
77 } else {
Sandeep Panda09fd9782014-12-26 10:32:01 +053078 writel(0x00FF, MDP_PANIC_LUT0);
Sachin Bhayarea8deb5c2015-07-16 11:49:08 +053079 writel(0xFFF0, MDP_ROBUST_LUT);
80 }
Sandeep Panda09fd9782014-12-26 10:32:01 +053081 writel(0x1, MDP_PANIC_ROBUST_CTRL);
82 writel(0xFF00, MDP_ROBUST_LUT);
83
Ajay Dudanib01e5062011-12-03 23:23:42 -080084 // ------------- programming MDP_DMA_P_CONFIG ---------------------
85 writel(0x1800bf, MDP_DMA_P_CONFIG); // rgb888
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +053086
Ajay Dudanib01e5062011-12-03 23:23:42 -080087 writel(0x00000000, MDP_DMA_P_OUT_XY);
Channagoud Kadabi539ef722012-03-29 16:02:50 +053088 writel(pinfo->yres << 16 | pinfo->xres, MDP_DMA_P_SIZE);
89 writel(MIPI_FB_ADDR, MDP_DMA_P_BUF_ADDR);
90 writel(pinfo->xres * ystride, MDP_DMA_P_BUF_Y_STRIDE);
91 writel(hsync_period << 16 | lcdc->h_pulse_width, \
92 MDP_DSI_VIDEO_HSYNC_CTL);
Ajay Dudanib01e5062011-12-03 23:23:42 -080093 writel(vsync_period, MDP_DSI_VIDEO_VSYNC_PERIOD);
Channagoud Kadabi539ef722012-03-29 16:02:50 +053094 writel(lcdc->v_pulse_width * hsync_period, \
95 MDP_DSI_VIDEO_VSYNC_PULSE_WIDTH);
Shivaraj Shettyf9e10c42014-09-17 04:21:15 +053096 if (mdp_rev == MDP_REV_304 || mdp_rev == MDP_REV_305) {
Terence Hampson7385f6a2013-08-16 15:31:25 -040097 writel((pinfo->xres + lcdc->h_back_porch + \
98 lcdc->h_pulse_width - 1) << 16 | \
99 lcdc->h_back_porch + lcdc->h_pulse_width, \
100 MDP_DSI_VIDEO_DISPLAY_HCTL);
101 writel((lcdc->v_back_porch + lcdc->v_pulse_width) \
102 * hsync_period, MDP_DSI_VIDEO_DISPLAY_V_START);
103 writel(vsync_period - lcdc->v_front_porch * hsync_period - 1,
Ajay Dudanib01e5062011-12-03 23:23:42 -0800104 MDP_DSI_VIDEO_DISPLAY_V_END);
Terence Hampson7385f6a2013-08-16 15:31:25 -0400105 } else {
106 writel((pinfo->xres + lcdc->h_back_porch - 1) << 16 | \
107 lcdc->h_back_porch, MDP_DSI_VIDEO_DISPLAY_HCTL);
108 writel(lcdc->v_back_porch * hsync_period, \
109 MDP_DSI_VIDEO_DISPLAY_V_START);
110 writel((pinfo->yres + lcdc->v_back_porch) * hsync_period,
111 MDP_DSI_VIDEO_DISPLAY_V_END);
112 }
Ajay Dudanib01e5062011-12-03 23:23:42 -0800113 writel(0x00ABCDEF, MDP_DSI_VIDEO_BORDER_CLR);
114 writel(0x00000000, MDP_DSI_VIDEO_HSYNC_SKEW);
115 writel(0x00000000, MDP_DSI_VIDEO_CTL_POLARITY);
116 // end of cmd mdp
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +0530117
Channagoud Kadabi539ef722012-03-29 16:02:50 +0530118 return 0;
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +0530119}
Ajay Dudanib01e5062011-12-03 23:23:42 -0800120
Channagoud Kadabi10189fd2012-05-25 13:33:39 +0530121int mdp_dsi_cmd_config(struct msm_panel_info *pinfo,
122 struct fbcon_config *fb)
123{
124 int ret = 0;
125 unsigned short pack_pattern = 0x21;
126 unsigned char ystride = 3;
127
Sandeep Panda09fd9782014-12-26 10:32:01 +0530128 /* Program QOS remapper settings */
129 writel(0x1A9, MDP_DMA_P_QOS_REMAPPER);
130 writel(0x0, MDP_DMA_P_WATERMARK_0);
131 writel(0x0, MDP_DMA_P_WATERMARK_1);
132 writel(0x0, MDP_DMA_P_WATERMARK_2);
133 if (pinfo->xres >= 720)
134 writel(0xFFFF, MDP_PANIC_LUT0);
135 else
136 writel(0x00FF, MDP_PANIC_LUT0);
137 writel(0x1, MDP_PANIC_ROBUST_CTRL);
138 writel(0xFF00, MDP_ROBUST_LUT);
139
Channagoud Kadabi10189fd2012-05-25 13:33:39 +0530140 writel(0x03ffffff, MDP_INTR_ENABLE);
141
142 // ------------- programming MDP_DMA_P_CONFIG ---------------------
143 writel(pack_pattern << 8 | 0x3f | (0 << 25)| (1 << 19) | (1 << 7) , MDP_DMA_P_CONFIG); // rgb888
144 writel(0x00000000, MDP_DMA_P_OUT_XY);
145 writel(pinfo->yres << 16 | pinfo->xres, MDP_DMA_P_SIZE);
146 writel(MIPI_FB_ADDR, MDP_DMA_P_BUF_ADDR);
147
148 writel(pinfo->xres * ystride, MDP_DMA_P_BUF_Y_STRIDE);
149
150 writel(0x10, MDP_DSI_CMD_MODE_ID_MAP);
151 writel(0x11, MDP_DSI_CMD_MODE_TRIGGER_EN);
152 mdelay(10);
153
154 return ret;
155}
156
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +0530157void mdp_disable(void)
158{
Channagoud Kadabif2488462012-06-12 15:22:48 +0530159 if (!target_cont_splash_screen())
160 writel(0x00000000, MDP_DSI_VIDEO_EN);
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +0530161}
162
Channagoud Kadabi539ef722012-03-29 16:02:50 +0530163int mdp_dsi_video_off(void)
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +0530164{
Channagoud Kadabif2488462012-06-12 15:22:48 +0530165 if (!target_cont_splash_screen()) {
166 mdp_disable();
167 mdelay(60);
Channagoud Kadabif2488462012-06-12 15:22:48 +0530168 }
Padmanabhan Komandurufa4be752012-10-08 16:51:56 +0530169 writel(0x00000000, MDP_INTR_ENABLE);
170 writel(0x01ffffff, MDP_INTR_CLEAR);
Channagoud Kadabi539ef722012-03-29 16:02:50 +0530171 return NO_ERROR;
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +0530172}
Shashank Mittal4bfb2e32012-04-16 10:56:27 -0700173
Channagoud Kadabi10189fd2012-05-25 13:33:39 +0530174int mdp_dsi_cmd_off(void)
175{
Channagoud Kadabif2488462012-06-12 15:22:48 +0530176 if (!target_cont_splash_screen()) {
177 mdp_dma_off();
178 /*
179 * Allow sometime for the DMA channel to
180 * stop the data transfer
181 */
182 mdelay(10);
Channagoud Kadabif2488462012-06-12 15:22:48 +0530183 }
Padmanabhan Komandurufa4be752012-10-08 16:51:56 +0530184 writel(0x00000000, MDP_INTR_ENABLE);
185 writel(0x01ffffff, MDP_INTR_CLEAR);
Channagoud Kadabi10189fd2012-05-25 13:33:39 +0530186 return NO_ERROR;
187}
188
Shashank Mittal4bfb2e32012-04-16 10:56:27 -0700189void mdp_set_revision(int rev)
190{
191 mdp_rev = rev;
192}
193
194int mdp_get_revision(void)
195{
196 return mdp_rev;
197}
Channagoud Kadabi539ef722012-03-29 16:02:50 +0530198
Jayant Shekhar32397f92014-03-27 13:30:41 +0530199int mdp_dsi_video_on(struct msm_panel_info *pinfo)
Channagoud Kadabi539ef722012-03-29 16:02:50 +0530200{
201 int ret = 0;
202
203 writel(0x00000001, MDP_DSI_VIDEO_EN);
204
205 return ret;
206}
Channagoud Kadabi10189fd2012-05-25 13:33:39 +0530207
Jayant Shekhar32397f92014-03-27 13:30:41 +0530208int mdp_dma_on(struct msm_panel_info *pinfo)
Channagoud Kadabi10189fd2012-05-25 13:33:39 +0530209{
210 int ret = 0;
Xiaoming Zhou8d534dd2013-07-29 15:49:19 -0400211 mdelay(100);
Channagoud Kadabi10189fd2012-05-25 13:33:39 +0530212 writel(0x00000001, MDP_DMA_P_START);
213
214 return ret;
215}
216
217int mdp_dma_off()
218{
219 int ret = 0;
220
Channagoud Kadabif2488462012-06-12 15:22:48 +0530221 if (!target_cont_splash_screen())
222 writel(0x00000000, MDP_DMA_P_START);
Channagoud Kadabi10189fd2012-05-25 13:33:39 +0530223
224 return ret;
225}
Asaf Penso6c58a6b2013-07-14 19:57:29 +0300226
227int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb)
228{
229 return NO_ERROR;
230}
231
Jayant Shekhar32397f92014-03-27 13:30:41 +0530232int mdp_edp_on(struct msm_panel_info *pinfo)
Asaf Penso6c58a6b2013-07-14 19:57:29 +0300233{
234 return NO_ERROR;
235}
236
237int mdp_edp_off(void)
238{
239 return NO_ERROR;
240}
Ajay Singh Parmar63c18502014-07-23 23:37:19 -0700241
Ajay Singh Parmar243d82b2014-07-23 23:01:44 -0700242int mdss_hdmi_config(struct msm_panel_info *pinfo, struct fbcon_config *fb)
Ajay Singh Parmar63c18502014-07-23 23:37:19 -0700243{
244 return NO_ERROR;
245}
246
Veera Sundaram Sankarandb0b2bf2014-12-16 18:09:27 -0800247int mdss_hdmi_on(struct msm_panel_info *pinfo)
Ajay Singh Parmar63c18502014-07-23 23:37:19 -0700248{
249 return NO_ERROR;
250}
251
Ajay Singh Parmar243d82b2014-07-23 23:01:44 -0700252int mdss_hdmi_off(void)
Ajay Singh Parmar63c18502014-07-23 23:37:19 -0700253{
254 return NO_ERROR;
255}