Jeevan Shriram | 2d3500b | 2014-12-29 16:25:06 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions |
| 5 | * are met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer in |
| 10 | * the documentation and/or other materials provided with the |
| 11 | * distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 19 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 20 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
| 22 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
| 23 | * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
| 24 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| 25 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 26 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 27 | * SUCH DAMAGE. |
| 28 | */ |
| 29 | |
| 30 | #include <debug.h> |
| 31 | #include <smem.h> |
| 32 | #include <err.h> |
| 33 | #include <msm_panel.h> |
| 34 | #include <mipi_dsi.h> |
| 35 | #include <pm8x41.h> |
| 36 | #include <pm8x41_wled.h> |
| 37 | #include <board.h> |
| 38 | #include <mdp5.h> |
| 39 | #include <scm.h> |
| 40 | #include <platform/gpio.h> |
| 41 | #include <platform/iomap.h> |
| 42 | #include <target/display.h> |
Aparna Mallavarapu | 430797d | 2014-05-15 11:52:56 +0530 | [diff] [blame] | 43 | #include <i2c_qup.h> |
| 44 | #include <blsp_qup.h> |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 45 | |
| 46 | #include "include/panel.h" |
| 47 | #include "include/display_resource.h" |
Veera Sundaram Sankaran | 87f8813 | 2015-01-28 11:32:44 -0800 | [diff] [blame] | 48 | #include "gcdb_display.h" |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 49 | |
Padmanabhan Komanduru | 18aa507 | 2014-04-17 16:52:53 +0530 | [diff] [blame] | 50 | #define VCO_DELAY_USEC 1000 |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 51 | #define GPIO_STATE_LOW 0 |
| 52 | #define GPIO_STATE_HIGH 2 |
| 53 | #define RESET_GPIO_SEQ_LEN 3 |
| 54 | #define PWM_DUTY_US 13 |
| 55 | #define PWM_PERIOD_US 27 |
| 56 | |
Padmanabhan Komanduru | 0a5db94 | 2014-04-17 16:56:04 +0530 | [diff] [blame] | 57 | static void mdss_dsi_uniphy_pll_sw_reset_8916(uint32_t pll_base) |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 58 | { |
Padmanabhan Komanduru | 0a5db94 | 2014-04-17 16:56:04 +0530 | [diff] [blame] | 59 | writel(0x01, pll_base + 0x0068); /* PLL TEST CFG */ |
| 60 | mdelay(1); |
| 61 | writel(0x00, pll_base + 0x0068); /* PLL TEST CFG */ |
| 62 | mdelay(1); |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 63 | } |
| 64 | |
Shuo Yan | d954f18 | 2015-02-11 10:08:49 +0800 | [diff] [blame^] | 65 | static void dsi_pll_toggle_lock_detect_8916(uint32_t pll_base) |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 66 | { |
Shuo Yan | d954f18 | 2015-02-11 10:08:49 +0800 | [diff] [blame^] | 67 | writel(0x04, pll_base + 0x0064); /* LKDetect CFG2 */ |
| 68 | udelay(1); |
| 69 | writel(0x05, pll_base + 0x0064); /* LKDetect CFG2 */ |
| 70 | udelay(512); |
| 71 | } |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 72 | |
Shuo Yan | d954f18 | 2015-02-11 10:08:49 +0800 | [diff] [blame^] | 73 | static void dsi_pll_sw_reset_8916(uint32_t pll_base) |
| 74 | { |
Padmanabhan Komanduru | 0a5db94 | 2014-04-17 16:56:04 +0530 | [diff] [blame] | 75 | writel(0x01, pll_base + 0x0068); /* PLL TEST CFG */ |
| 76 | udelay(1); |
| 77 | writel(0x00, pll_base + 0x0068); /* PLL TEST CFG */ |
Shuo Yan | d954f18 | 2015-02-11 10:08:49 +0800 | [diff] [blame^] | 78 | } |
| 79 | |
| 80 | static uint32_t gf_1_dsi_pll_enable_sequence_8916(uint32_t pll_base) |
| 81 | { |
| 82 | uint32_t rc; |
| 83 | |
| 84 | dsi_pll_sw_reset_8916(pll_base); |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 85 | |
| 86 | /* |
| 87 | * Add hardware recommended delays between register writes for |
| 88 | * the updates to take effect. These delays are necessary for the |
| 89 | * PLL to successfully lock |
| 90 | */ |
Shuo Yan | d954f18 | 2015-02-11 10:08:49 +0800 | [diff] [blame^] | 91 | writel(0x14, pll_base + 0x0070); /* CAL CFG1*/ |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 92 | writel(0x01, pll_base + 0x0020); /* GLB CFG */ |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 93 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
Shuo Yan | d954f18 | 2015-02-11 10:08:49 +0800 | [diff] [blame^] | 94 | udelay(3); |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 95 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
Shuo Yan | d954f18 | 2015-02-11 10:08:49 +0800 | [diff] [blame^] | 96 | udelay(500); |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 97 | |
Shuo Yan | d954f18 | 2015-02-11 10:08:49 +0800 | [diff] [blame^] | 98 | dsi_pll_toggle_lock_detect_8916(pll_base); |
| 99 | rc = readl(pll_base + 0x00c0) & 0x01; |
| 100 | |
| 101 | return rc; |
| 102 | } |
| 103 | |
| 104 | static uint32_t gf_2_dsi_pll_enable_sequence_8916(uint32_t pll_base) |
| 105 | { |
| 106 | uint32_t rc; |
| 107 | |
| 108 | dsi_pll_sw_reset_8916(pll_base); |
| 109 | |
| 110 | /* |
| 111 | * Add hardware recommended delays between register writes for |
| 112 | * the updates to take effect. These delays are necessary for the |
| 113 | * PLL to successfully lock |
| 114 | */ |
| 115 | writel(0x04, pll_base + 0x0070); /* CAL CFG1*/ |
| 116 | writel(0x01, pll_base + 0x0020); /* GLB CFG */ |
| 117 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
| 118 | udelay(3); |
| 119 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
| 120 | udelay(500); |
| 121 | |
| 122 | dsi_pll_toggle_lock_detect_8916(pll_base); |
| 123 | rc = readl(pll_base + 0x00c0) & 0x01; |
| 124 | |
| 125 | return rc; |
| 126 | } |
| 127 | |
| 128 | static uint32_t tsmc_dsi_pll_enable_sequence_8916(uint32_t pll_base) |
| 129 | { |
| 130 | uint32_t rc; |
| 131 | |
| 132 | dsi_pll_sw_reset_8916(pll_base); |
| 133 | /* |
| 134 | * Add hardware recommended delays between register writes for |
| 135 | * the updates to take effect. These delays are necessary for the |
| 136 | * PLL to successfully lock |
| 137 | */ |
| 138 | |
| 139 | writel(0x34, pll_base + 0x0070); /* CAL CFG1*/ |
| 140 | writel(0x01, pll_base + 0x0020); /* GLB CFG */ |
| 141 | writel(0x05, pll_base + 0x0020); /* GLB CFG */ |
| 142 | writel(0x0f, pll_base + 0x0020); /* GLB CFG */ |
| 143 | udelay(500); |
| 144 | |
| 145 | dsi_pll_toggle_lock_detect_8916(pll_base); |
| 146 | rc = readl(pll_base + 0x00c0) & 0x01; |
| 147 | |
| 148 | return rc; |
| 149 | } |
| 150 | |
| 151 | |
| 152 | static uint32_t dsi_pll_enable_seq_8916(uint32_t pll_base) |
| 153 | { |
| 154 | uint32_t pll_locked = 0; |
| 155 | uint32_t counter = 0; |
| 156 | |
| 157 | do { |
| 158 | pll_locked = tsmc_dsi_pll_enable_sequence_8916(pll_base); |
| 159 | |
| 160 | dprintf(SPEW, "TSMC pll locked status is %d\n", pll_locked); |
| 161 | ++counter; |
| 162 | } while (!pll_locked && (counter < 3)); |
| 163 | |
| 164 | if(!pll_locked) { |
| 165 | counter = 0; |
| 166 | do { |
| 167 | pll_locked = gf_1_dsi_pll_enable_sequence_8916(pll_base); |
| 168 | |
| 169 | dprintf(SPEW, "GF P1 pll locked status is %d\n", pll_locked); |
| 170 | ++counter; |
| 171 | } while (!pll_locked && (counter < 3)); |
| 172 | } |
| 173 | |
| 174 | if(!pll_locked) { |
| 175 | counter = 0; |
| 176 | do { |
| 177 | pll_locked = gf_2_dsi_pll_enable_sequence_8916(pll_base); |
| 178 | |
| 179 | dprintf(SPEW, "GF P2 pll locked status is %d\n", pll_locked); |
| 180 | ++counter; |
| 181 | } while (!pll_locked && (counter < 3)); |
| 182 | } |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 183 | |
| 184 | return pll_locked; |
| 185 | } |
| 186 | |
| 187 | int target_backlight_ctrl(struct backlight *bl, uint8_t enable) |
| 188 | { |
| 189 | struct pm8x41_mpp mpp; |
| 190 | int rc; |
| 191 | |
Shuo Yan | 123546b | 2014-05-19 19:35:41 +0800 | [diff] [blame] | 192 | if (bl->bl_interface_type == BL_DCS) |
| 193 | return 0; |
| 194 | |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 195 | mpp.base = PM8x41_MMP4_BASE; |
| 196 | mpp.vin = MPP_VIN0; |
| 197 | if (enable) { |
| 198 | pm_pwm_enable(false); |
| 199 | rc = pm_pwm_config(PWM_DUTY_US, PWM_PERIOD_US); |
| 200 | if (rc < 0) |
| 201 | mpp.mode = MPP_HIGH; |
| 202 | else { |
| 203 | mpp.mode = MPP_DTEST1; |
| 204 | pm_pwm_enable(true); |
| 205 | } |
| 206 | pm8x41_config_output_mpp(&mpp); |
| 207 | pm8x41_enable_mpp(&mpp, MPP_ENABLE); |
| 208 | } else { |
| 209 | pm_pwm_enable(false); |
| 210 | pm8x41_enable_mpp(&mpp, MPP_DISABLE); |
| 211 | } |
| 212 | mdelay(20); |
| 213 | return 0; |
| 214 | } |
| 215 | |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 216 | int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo) |
| 217 | { |
| 218 | int32_t ret = 0; |
| 219 | struct mdss_dsi_pll_config *pll_data; |
| 220 | dprintf(SPEW, "target_panel_clock\n"); |
| 221 | |
| 222 | pll_data = pinfo->mipi.dsi_pll_config; |
Padmanabhan Komanduru | 18aa507 | 2014-04-17 16:52:53 +0530 | [diff] [blame] | 223 | pll_data->vco_delay = VCO_DELAY_USEC; |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 224 | |
| 225 | if (enable) { |
| 226 | mdp_gdsc_ctrl(enable); |
| 227 | mdss_bus_clocks_enable(); |
| 228 | mdp_clock_enable(); |
| 229 | ret = restore_secure_cfg(SECURE_DEVICE_MDSS); |
| 230 | if (ret) { |
| 231 | dprintf(CRITICAL, |
| 232 | "%s: Failed to restore MDP security configs", |
| 233 | __func__); |
| 234 | mdp_clock_disable(); |
| 235 | mdss_bus_clocks_disable(); |
| 236 | mdp_gdsc_ctrl(0); |
| 237 | return ret; |
| 238 | } |
Padmanabhan Komanduru | 0a5db94 | 2014-04-17 16:56:04 +0530 | [diff] [blame] | 239 | mdss_dsi_uniphy_pll_sw_reset_8916(DSI0_PLL_BASE); |
Jeevan Shriram | 2d3500b | 2014-12-29 16:25:06 -0800 | [diff] [blame] | 240 | mdss_dsi_auto_pll_config(pinfo->mipi.pll_0_base, |
| 241 | pinfo->mipi.ctl_base, pll_data); |
| 242 | if (!dsi_pll_enable_seq_8916(pinfo->mipi.pll_0_base)) |
Padmanabhan Komanduru | 0a5db94 | 2014-04-17 16:56:04 +0530 | [diff] [blame] | 243 | dprintf(CRITICAL, "Not able to enable the pll\n"); |
Vineet Bajaj | e022da6 | 2014-07-24 19:13:34 +0530 | [diff] [blame] | 244 | gcc_dsi_clocks_enable(pinfo->mipi.dual_dsi, pll_data->pclk_m, |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 245 | pll_data->pclk_n, |
| 246 | pll_data->pclk_d); |
| 247 | } else if(!target_cont_splash_screen()) { |
Vineet Bajaj | e022da6 | 2014-07-24 19:13:34 +0530 | [diff] [blame] | 248 | gcc_dsi_clocks_disable(pinfo->mipi.dual_dsi); |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 249 | mdp_clock_disable(); |
| 250 | mdss_bus_clocks_disable(); |
| 251 | mdp_gdsc_ctrl(enable); |
| 252 | } |
| 253 | |
| 254 | return 0; |
| 255 | } |
| 256 | |
Aparna Mallavarapu | 430797d | 2014-05-15 11:52:56 +0530 | [diff] [blame] | 257 | #define QRD_LCD_I2C_ADDRESS 0x3E |
| 258 | #define QRD_LCD_VPOS_ADDRESS 0x00 |
| 259 | #define QRD_LCD_VNEG_ADDRESS 0x01 |
| 260 | #define QRD_LCD_DIS_ADDRESS 0x03 |
| 261 | #define QRD_LCD_CONTROL_ADDRESS 0xFF |
| 262 | |
| 263 | static struct qup_i2c_dev *i2c_dev; |
| 264 | static int qrd_lcd_i2c_read(uint8_t addr) |
| 265 | { |
| 266 | int ret = 0; |
| 267 | /* Create a i2c_msg buffer, that is used to put the controller into read |
| 268 | mode and then to read some data. */ |
| 269 | struct i2c_msg msg_buf[] = { |
| 270 | {QRD_LCD_I2C_ADDRESS, I2C_M_WR, 1, &addr}, |
| 271 | {QRD_LCD_I2C_ADDRESS, I2C_M_RD, 1, &ret} |
| 272 | }; |
| 273 | |
| 274 | ret = qup_i2c_xfer(i2c_dev, msg_buf, 2); |
| 275 | if(ret < 0) { |
| 276 | dprintf(CRITICAL, "qup_i2c_xfer error %d\n", ret); |
| 277 | return ret; |
| 278 | } |
| 279 | return 0; |
| 280 | } |
| 281 | |
| 282 | static int qrd_lcd_i2c_write(uint8_t addr, uint8_t val) |
| 283 | { |
| 284 | int ret = 0; |
| 285 | uint8_t data_buf[] = { addr, val }; |
| 286 | |
| 287 | /* Create a i2c_msg buffer, that is used to put the controller into write |
| 288 | mode and then to write some data. */ |
| 289 | struct i2c_msg msg_buf[] = { {QRD_LCD_I2C_ADDRESS, |
| 290 | I2C_M_WR, 2, data_buf} |
| 291 | }; |
| 292 | |
| 293 | ret = qup_i2c_xfer(i2c_dev, msg_buf, 1); |
| 294 | if(ret < 0) { |
| 295 | dprintf(CRITICAL, "qup_i2c_xfer error %d\n", ret); |
| 296 | return ret; |
| 297 | } |
| 298 | return 0; |
| 299 | } |
| 300 | |
Mao Flynn | 732e3c2 | 2014-07-02 17:39:02 +0800 | [diff] [blame] | 301 | static int target_panel_reset_skuh(uint8_t enable) |
| 302 | { |
| 303 | int ret = NO_ERROR; |
| 304 | if (enable) { |
| 305 | /* for tps65132 ENP pin */ |
| 306 | gpio_tlmm_config(enp_gpio.pin_id, 0, |
| 307 | enp_gpio.pin_direction, enp_gpio.pin_pull, |
| 308 | enp_gpio.pin_strength, |
| 309 | enp_gpio.pin_state); |
| 310 | gpio_set_dir(enp_gpio.pin_id, 2); |
| 311 | |
| 312 | /* for tps65132 ENN pin*/ |
| 313 | gpio_tlmm_config(enn_gpio.pin_id, 0, |
| 314 | enn_gpio.pin_direction, enn_gpio.pin_pull, |
| 315 | enn_gpio.pin_strength, |
| 316 | enn_gpio.pin_state); |
| 317 | gpio_set_dir(enn_gpio.pin_id, 2); |
| 318 | |
| 319 | i2c_dev = qup_blsp_i2c_init(BLSP_ID_1, QUP_ID_1, 100000, 19200000); |
| 320 | if(!i2c_dev) { |
| 321 | dprintf(CRITICAL, "qup_blsp_i2c_init failed \n"); |
| 322 | ASSERT(0); |
| 323 | } |
| 324 | |
| 325 | ret = qrd_lcd_i2c_write(QRD_LCD_VPOS_ADDRESS, 0x0E); /* 5.4V */ |
| 326 | if (ret) { |
| 327 | dprintf(CRITICAL, "VPOS Register: I2C Write failure\n"); |
| 328 | } |
| 329 | |
| 330 | ret = qrd_lcd_i2c_write(QRD_LCD_VNEG_ADDRESS, 0x0E); /* -5.4V */ |
| 331 | if (ret) { |
| 332 | dprintf(CRITICAL, "VNEG Register: I2C write failure\n"); |
| 333 | } |
| 334 | |
| 335 | ret = qrd_lcd_i2c_write(QRD_LCD_DIS_ADDRESS, 0x0F); |
| 336 | if (ret) { |
| 337 | dprintf(CRITICAL, "Apps freq DIS Register: I2C write failure\n"); |
| 338 | } |
| 339 | |
| 340 | ret = qrd_lcd_i2c_write(QRD_LCD_CONTROL_ADDRESS, 0xF0); |
| 341 | if (ret) { |
| 342 | dprintf(CRITICAL, "Control Register: I2C write failure\n"); |
| 343 | } |
| 344 | } else { |
| 345 | gpio_set_dir(enp_gpio.pin_id, 0); /* ENP */ |
| 346 | gpio_set_dir(enn_gpio.pin_id, 0); /* ENN */ |
| 347 | } |
| 348 | return 0; |
| 349 | } |
| 350 | |
| 351 | static int target_panel_reset_skuk(uint8_t enable) |
| 352 | { |
| 353 | if (enable) { |
| 354 | /* for tps65132 ENP pin*/ |
| 355 | gpio_tlmm_config(enp_gpio_skuk.pin_id, 0, |
| 356 | enp_gpio_skuk.pin_direction, enp_gpio_skuk.pin_pull, |
| 357 | enp_gpio_skuk.pin_strength, enp_gpio_skuk.pin_state); |
| 358 | gpio_set_dir(enp_gpio_skuk.pin_id, 2); |
| 359 | |
| 360 | /* for tps65132 ENN pin*/ |
| 361 | gpio_tlmm_config(enn_gpio_skuk.pin_id, 0, |
| 362 | enn_gpio_skuk.pin_direction, enn_gpio_skuk.pin_pull, |
| 363 | enn_gpio_skuk.pin_strength, enn_gpio_skuk.pin_state); |
| 364 | gpio_set_dir(enn_gpio_skuk.pin_id, 2); |
| 365 | |
| 366 | /* configure backlight gpio for SKUK */ |
| 367 | gpio_tlmm_config(bkl_gpio_skuk.pin_id, 0, |
| 368 | bkl_gpio_skuk.pin_direction, bkl_gpio_skuk.pin_pull, |
| 369 | bkl_gpio_skuk.pin_strength, bkl_gpio_skuk.pin_state); |
| 370 | gpio_set_dir(bkl_gpio_skuk.pin_id, 2); |
| 371 | } else { |
| 372 | gpio_set_dir(bkl_gpio_skuk.pin_id, 0); |
| 373 | gpio_set_dir(enp_gpio_skuk.pin_id, 0); /* ENP */ |
| 374 | gpio_set_dir(enn_gpio_skuk.pin_id, 0); /* ENN */ |
| 375 | } |
| 376 | return 0; |
| 377 | } |
| 378 | |
Vineet Bajaj | 3acf94f | 2014-12-04 19:55:03 +0530 | [diff] [blame] | 379 | int target_panel_reset_incell(uint8_t enable) |
| 380 | { |
| 381 | /*Enable the gpios in 75->97->77 order for incell panel*/ |
| 382 | if (enable) { |
| 383 | gpio_tlmm_config(enable_gpio_1.pin_id, 0, |
| 384 | enable_gpio_1.pin_direction, enable_gpio_1.pin_pull, |
| 385 | enable_gpio_1.pin_strength, enable_gpio_1.pin_state); |
| 386 | gpio_set_dir(enable_gpio_1.pin_id, 2); |
| 387 | |
| 388 | gpio_tlmm_config(enp_gpio.pin_id, 0, |
| 389 | enp_gpio.pin_direction, enp_gpio.pin_pull, |
| 390 | enp_gpio.pin_strength, enp_gpio.pin_state); |
| 391 | gpio_set_dir(enp_gpio.pin_id, 2); |
| 392 | |
| 393 | gpio_tlmm_config(enn_gpio_1.pin_id, 0, |
| 394 | enn_gpio_1.pin_direction, enn_gpio_1.pin_pull, |
| 395 | enn_gpio_1.pin_strength, enn_gpio_1.pin_state); |
| 396 | gpio_set_dir(enn_gpio_1.pin_id, 2); |
| 397 | } |
| 398 | else { |
| 399 | gpio_set_dir(enable_gpio_1.pin_id, 0); |
| 400 | gpio_set_dir(enp_gpio.pin_id, 0); /* ENP */ |
| 401 | gpio_set_dir(enn_gpio_1.pin_id, 0); /* ENN */ |
| 402 | } |
| 403 | } |
| 404 | |
Vineet Bajaj | 5be1e4a | 2015-02-02 15:07:49 +0530 | [diff] [blame] | 405 | int target_panel_reset_jdi_a216(uint8_t enable) |
| 406 | { |
| 407 | if (enable) { |
| 408 | gpio_tlmm_config(ts_reset_gpio.pin_id, 0, |
| 409 | ts_reset_gpio.pin_direction, ts_reset_gpio.pin_pull, |
| 410 | ts_reset_gpio.pin_strength, ts_reset_gpio.pin_state); |
| 411 | gpio_set_dir(ts_reset_gpio.pin_id, GPIO_STATE_HIGH); |
| 412 | } else { |
| 413 | gpio_set_dir(ts_reset_gpio.pin_id, GPIO_STATE_LOW); |
| 414 | } |
| 415 | } |
| 416 | |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 417 | int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq, |
| 418 | struct msm_panel_info *pinfo) |
| 419 | { |
| 420 | int ret = NO_ERROR; |
Mao Flynn | 8140947 | 2014-04-10 15:01:30 +0800 | [diff] [blame] | 421 | uint32_t hw_id = board_hardware_id(); |
| 422 | uint32_t hw_subtype = board_hardware_subtype(); |
Gustavo Solaira | 80c274c | 2014-10-22 16:21:27 -0300 | [diff] [blame] | 423 | uint32_t target_id, plat_hw_ver_major; |
Mao Flynn | 8140947 | 2014-04-10 15:01:30 +0800 | [diff] [blame] | 424 | |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 425 | if (enable) { |
| 426 | if (pinfo->mipi.use_enable_gpio) { |
Gustavo Solaira | fb6fdd6 | 2014-09-30 08:15:32 -0300 | [diff] [blame] | 427 | /* set enable gpio pin for SKUT1 */ |
| 428 | if ((hw_id == HW_PLATFORM_QRD) && |
Gustavo Solaira | 80c274c | 2014-10-22 16:21:27 -0300 | [diff] [blame] | 429 | (hw_subtype == HW_PLATFORM_SUBTYPE_SKUT1)) { |
| 430 | target_id = board_target_id(); |
| 431 | plat_hw_ver_major = ((target_id >> 16) & 0xFF); |
| 432 | if ((plat_hw_ver_major & 0x0F) == 0x1) |
| 433 | enable_gpio = enable_gpio_skut1; |
| 434 | else |
| 435 | enable_gpio = enable_gpio_skut2; |
| 436 | } |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 437 | gpio_tlmm_config(enable_gpio.pin_id, 0, |
| 438 | enable_gpio.pin_direction, enable_gpio.pin_pull, |
| 439 | enable_gpio.pin_strength, |
| 440 | enable_gpio.pin_state); |
| 441 | |
| 442 | gpio_set_dir(enable_gpio.pin_id, 2); |
| 443 | } |
| 444 | |
vijay kumar | dd51c59 | 2015-01-05 12:46:28 +0530 | [diff] [blame] | 445 | if (platform_is_msm8939() || platform_is_msm8929()) { |
Mao Flynn | 732e3c2 | 2014-07-02 17:39:02 +0800 | [diff] [blame] | 446 | if ((hw_id == HW_PLATFORM_QRD) && |
| 447 | (hw_subtype == HW_PLATFORM_SUBTYPE_SKUK)) |
| 448 | target_panel_reset_skuk(enable); |
Vineet Bajaj | 5be1e4a | 2015-02-02 15:07:49 +0530 | [diff] [blame] | 449 | if (((hw_id == HW_PLATFORM_SURF) && |
| 450 | (hw_subtype == HW_PLATFORM_SUBTYPE_CDP_1)) || |
| 451 | ((hw_id == HW_PLATFORM_MTP) && |
| 452 | (hw_subtype == HW_PLATFORM_SUBTYPE_MTP_3))) |
Vineet Bajaj | 3acf94f | 2014-12-04 19:55:03 +0530 | [diff] [blame] | 453 | target_panel_reset_incell(enable); |
Vineet Bajaj | 5be1e4a | 2015-02-02 15:07:49 +0530 | [diff] [blame] | 454 | if ((hw_id == HW_PLATFORM_SURF) && |
| 455 | (hw_subtype == HW_PLATFORM_SUBTYPE_CDP_2)) |
| 456 | target_panel_reset_jdi_a216(enable); |
Mao Flynn | 732e3c2 | 2014-07-02 17:39:02 +0800 | [diff] [blame] | 457 | } else { /* msm8916 */ |
| 458 | if ((hw_id == HW_PLATFORM_QRD) && |
| 459 | (hw_subtype == HW_PLATFORM_SUBTYPE_SKUH)) |
| 460 | target_panel_reset_skuh(enable); |
Mao Flynn | 8140947 | 2014-04-10 15:01:30 +0800 | [diff] [blame] | 461 | } |
| 462 | |
Shuo Yan | c8a417f | 2014-05-20 14:44:56 +0800 | [diff] [blame] | 463 | if (hw_id == HW_PLATFORM_MTP || hw_id == HW_PLATFORM_SURF) { |
| 464 | /* configure backlight gpio for MTP & CDP */ |
Vineet Bajaj | 3acf94f | 2014-12-04 19:55:03 +0530 | [diff] [blame] | 465 | gpio_tlmm_config(bkl_gpio.pin_id, 0, |
| 466 | bkl_gpio.pin_direction, bkl_gpio.pin_pull, |
| 467 | bkl_gpio.pin_strength, bkl_gpio.pin_state); |
| 468 | gpio_set_dir(bkl_gpio.pin_id, 2); |
Shuo Yan | c8a417f | 2014-05-20 14:44:56 +0800 | [diff] [blame] | 469 | } |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 470 | |
| 471 | gpio_tlmm_config(reset_gpio.pin_id, 0, |
| 472 | reset_gpio.pin_direction, reset_gpio.pin_pull, |
| 473 | reset_gpio.pin_strength, reset_gpio.pin_state); |
| 474 | |
| 475 | gpio_set_dir(reset_gpio.pin_id, 2); |
| 476 | |
| 477 | /* reset */ |
| 478 | for (int i = 0; i < RESET_GPIO_SEQ_LEN; i++) { |
| 479 | if (resetseq->pin_state[i] == GPIO_STATE_LOW) |
| 480 | gpio_set_dir(reset_gpio.pin_id, GPIO_STATE_LOW); |
| 481 | else |
| 482 | gpio_set_dir(reset_gpio.pin_id, GPIO_STATE_HIGH); |
| 483 | mdelay(resetseq->sleep[i]); |
| 484 | } |
| 485 | } else if(!target_cont_splash_screen()) { |
| 486 | gpio_set_dir(reset_gpio.pin_id, 0); |
| 487 | if (pinfo->mipi.use_enable_gpio) |
| 488 | gpio_set_dir(enable_gpio.pin_id, 0); |
Mao Flynn | 8140947 | 2014-04-10 15:01:30 +0800 | [diff] [blame] | 489 | |
vijay kumar | dd51c59 | 2015-01-05 12:46:28 +0530 | [diff] [blame] | 490 | if (platform_is_msm8939() || platform_is_msm8929()) { |
Mao Flynn | 732e3c2 | 2014-07-02 17:39:02 +0800 | [diff] [blame] | 491 | if ((hw_id == HW_PLATFORM_QRD) && |
| 492 | (hw_subtype == HW_PLATFORM_SUBTYPE_SKUK)) |
| 493 | target_panel_reset_skuk(enable); |
| 494 | } else { /* msm8916 */ |
| 495 | if ((hw_id == HW_PLATFORM_QRD) && |
| 496 | (hw_subtype == HW_PLATFORM_SUBTYPE_SKUH)) |
| 497 | target_panel_reset_skuh(enable); |
Mao Flynn | 8140947 | 2014-04-10 15:01:30 +0800 | [diff] [blame] | 498 | } |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 499 | } |
| 500 | |
| 501 | return ret; |
| 502 | } |
| 503 | |
Kuogee Hsieh | 93bcff6 | 2014-08-22 14:02:08 -0700 | [diff] [blame] | 504 | int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo) |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 505 | { |
Padmanabhan Komanduru | 0ed51fb | 2014-06-04 12:22:08 +0530 | [diff] [blame] | 506 | /* |
| 507 | * The PMIC regulators needed for display are enabled in SBL. |
| 508 | * There is no access to the regulators is LK. |
| 509 | */ |
| 510 | return NO_ERROR; |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 511 | } |
| 512 | |
| 513 | bool target_display_panel_node(char *panel_name, char *pbuf, uint16_t buf_size) |
| 514 | { |
Veera Sundaram Sankaran | c95d675 | 2014-07-31 11:49:52 -0700 | [diff] [blame] | 515 | return gcdb_display_cmdline_arg(panel_name, pbuf, buf_size); |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 516 | } |
| 517 | |
| 518 | void target_display_init(const char *panel_name) |
| 519 | { |
Padmanabhan Komanduru | 1869a76 | 2014-04-01 20:12:05 +0530 | [diff] [blame] | 520 | uint32_t panel_loop = 0; |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 521 | uint32_t ret = 0; |
Veera Sundaram Sankaran | 7868d54 | 2015-01-02 14:48:47 -0800 | [diff] [blame] | 522 | char cont_splash = '\0'; |
Jeevan Shriram | b0d523a | 2014-05-30 12:55:17 -0700 | [diff] [blame] | 523 | |
Veera Sundaram Sankaran | 7868d54 | 2015-01-02 14:48:47 -0800 | [diff] [blame] | 524 | set_panel_cmd_string(panel_name, &cont_splash); |
Sandeep Panda | e07c07b | 2014-08-25 17:04:17 +0530 | [diff] [blame] | 525 | panel_name += strspn(panel_name, " "); |
Veera Sundaram Sankaran | 3b75882 | 2014-10-17 12:15:39 -0700 | [diff] [blame] | 526 | |
| 527 | if (!strcmp(panel_name, NO_PANEL_CONFIG) |
| 528 | || !strcmp(panel_name, SIM_VIDEO_PANEL) |
| 529 | || !strcmp(panel_name, SIM_CMD_PANEL)) { |
Veera Sundaram Sankaran | c95d675 | 2014-07-31 11:49:52 -0700 | [diff] [blame] | 530 | dprintf(INFO, "Selected panel: %s\nSkip panel configuration\n", |
Veera Sundaram Sankaran | 3b75882 | 2014-10-17 12:15:39 -0700 | [diff] [blame] | 531 | panel_name); |
Jeevan Shriram | b0d523a | 2014-05-30 12:55:17 -0700 | [diff] [blame] | 532 | return; |
| 533 | } |
| 534 | |
Padmanabhan Komanduru | 1869a76 | 2014-04-01 20:12:05 +0530 | [diff] [blame] | 535 | do { |
Justin Philip | be9de5c | 2014-09-17 12:26:49 +0530 | [diff] [blame] | 536 | target_force_cont_splash_disable(false); |
Padmanabhan Komanduru | 1869a76 | 2014-04-01 20:12:05 +0530 | [diff] [blame] | 537 | ret = gcdb_display_init(panel_name, MDP_REV_50, MIPI_FB_ADDR); |
| 538 | if (!ret || ret == ERR_NOT_SUPPORTED) { |
| 539 | break; |
| 540 | } else { |
| 541 | target_force_cont_splash_disable(true); |
| 542 | msm_display_off(); |
Padmanabhan Komanduru | 1869a76 | 2014-04-01 20:12:05 +0530 | [diff] [blame] | 543 | } |
| 544 | } while (++panel_loop <= oem_panel_max_auto_detect_panels()); |
Veera Sundaram Sankaran | 7868d54 | 2015-01-02 14:48:47 -0800 | [diff] [blame] | 545 | |
| 546 | if (cont_splash == '0') { |
| 547 | dprintf(INFO, "Forcing continuous splash disable\n"); |
| 548 | target_force_cont_splash_disable(true); |
| 549 | } |
Padmanabhan Komanduru | cd5645e | 2014-03-25 20:34:18 +0530 | [diff] [blame] | 550 | } |
| 551 | |
| 552 | void target_display_shutdown(void) |
| 553 | { |
| 554 | gcdb_display_shutdown(); |
| 555 | } |