blob: 06a2c06f2334dd10dd5cb1de3b7f92fa234ff2d8 [file] [log] [blame]
Aparna Mallavarapu9e014372013-10-19 15:04:58 +05301/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <err.h>
30#include <assert.h>
31#include <debug.h>
32#include <reg.h>
33#include <platform/timer.h>
34#include <platform/iomap.h>
35#include <mmc.h>
36#include <clock.h>
37#include <platform/clock.h>
38
39void hsusb_clock_init(void)
40{
Aparna Mallavarapu70e5df52014-02-27 22:51:29 -080041 int ret;
42 struct clk *iclk, *cclk;
Aparna Mallavarapu9e014372013-10-19 15:04:58 +053043
Aparna Mallavarapu70e5df52014-02-27 22:51:29 -080044 ret = clk_get_set_enable("usb_iface_clk", 0, 1);
45 if(ret)
46 {
47 dprintf(CRITICAL, "failed to set usb_iface_clk ret = %d\n", ret);
48 ASSERT(0);
49 }
50
51 ret = clk_get_set_enable("usb_core_clk", 80000000, 1);
52 if(ret)
53 {
54 dprintf(CRITICAL, "failed to set usb_core_clk ret = %d\n", ret);
55 ASSERT(0);
56 }
57
58 mdelay(20);
59
60 iclk = clk_get("usb_iface_clk");
61 cclk = clk_get("usb_core_clk");
62
63 clk_disable(iclk);
64 clk_disable(cclk);
65
66 mdelay(20);
67
68 /* Start the block reset for usb */
69 writel(1, USB_HS_BCR);
70
71 mdelay(20);
72
73 /* Take usb block out of reset */
74 writel(0, USB_HS_BCR);
75
76 mdelay(20);
77
78 ret = clk_enable(iclk);
79
80 if(ret)
81 {
82 dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
83 ASSERT(0);
84 }
85
86 ret = clk_enable(cclk);
87
88 if(ret)
89 {
90 dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
91 ASSERT(0);
92 }
Aparna Mallavarapu9e014372013-10-19 15:04:58 +053093}
94
95void clock_init_mmc(uint32_t interface)
96{
Aparna Mallavarapu70e5df52014-02-27 22:51:29 -080097 char clk_name[64];
98 int ret;
Aparna Mallavarapu9e014372013-10-19 15:04:58 +053099
Aparna Mallavarapu70e5df52014-02-27 22:51:29 -0800100 snprintf(clk_name, sizeof(clk_name), "sdc%u_iface_clk", interface);
101
102 /* enable interface clock */
103 ret = clk_get_set_enable(clk_name, 0, 1);
104 if(ret)
105 {
106 dprintf(CRITICAL, "failed to set sdc1_iface_clk ret = %d\n", ret);
107 ASSERT(0);
108 }
Aparna Mallavarapu9e014372013-10-19 15:04:58 +0530109}
110
111/* Configure MMC clock */
112void clock_config_mmc(uint32_t interface, uint32_t freq)
113{
Aparna Mallavarapu70e5df52014-02-27 22:51:29 -0800114 int ret;
115 uint32_t reg;
116 char clk_name[64];
117
118 snprintf(clk_name, sizeof(clk_name), "sdc%u_core_clk", interface);
119
120 if(freq == MMC_CLK_400KHZ)
121 {
122 ret = clk_get_set_enable(clk_name, 400000, 1);
123 }
124 else if(freq == MMC_CLK_50MHZ)
125 {
126 ret = clk_get_set_enable(clk_name, 50000000, 1);
127 }
128 else if(freq == MMC_CLK_200MHZ)
129 {
130 ret = clk_get_set_enable(clk_name, 200000000, 1);
131 }
132 else if(freq == MMC_CLK_177MHZ)
133 {
134 ret = clk_get_set_enable(clk_name, 177770000, 1);
135 }
136 else
137 {
138 dprintf(CRITICAL, "sdc frequency (%u) is not supported\n", freq);
139 ASSERT(0);
140 }
141
142 if(ret)
143 {
144 dprintf(CRITICAL, "failed to set %s ret = %d\n", clk_name, ret);
145 ASSERT(0);
146 }
Aparna Mallavarapu9e014372013-10-19 15:04:58 +0530147}
148
149/* Configure UART clock based on the UART block id*/
150void clock_config_uart_dm(uint8_t id)
151{
Aparna Mallavarapu70e5df52014-02-27 22:51:29 -0800152 int ret;
153 char iclk[64];
154 char cclk[64];
Aparna Mallavarapu9e014372013-10-19 15:04:58 +0530155
Aparna Mallavarapu70e5df52014-02-27 22:51:29 -0800156 snprintf(iclk, sizeof(iclk), "uart%u_iface_clk", id);
157 snprintf(cclk, sizeof(cclk), "uart%u_core_clk", id);
Aparna Mallavarapu9e014372013-10-19 15:04:58 +0530158
Aparna Mallavarapu70e5df52014-02-27 22:51:29 -0800159 ret = clk_get_set_enable(iclk, 0, 1);
160 if(ret)
161 {
162 dprintf(CRITICAL, "failed to set %s ret = %d\n", iclk, ret);
163 ASSERT(0);
164 }
Aparna Mallavarapu9e014372013-10-19 15:04:58 +0530165
Aparna Mallavarapu70e5df52014-02-27 22:51:29 -0800166 ret = clk_get_set_enable(cclk, 7372800, 1);
167 if(ret)
168 {
169 dprintf(CRITICAL, "failed to set %s ret = %d\n", cclk, ret);
170 ASSERT(0);
171 }
Aparna Mallavarapu9e014372013-10-19 15:04:58 +0530172}