Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <assert.h> |
| 30 | #include <reg.h> |
| 31 | #include <err.h> |
| 32 | #include <clock.h> |
| 33 | #include <clock_pll.h> |
| 34 | #include <clock_lib2.h> |
| 35 | #include <platform/clock.h> |
| 36 | #include <platform/iomap.h> |
| 37 | |
| 38 | |
| 39 | /* Mux source select values */ |
| 40 | #define cxo_source_val 0 |
| 41 | #define gpll0_source_val 1 |
| 42 | #define gpll4_source_val 5 |
| 43 | #define cxo_mm_source_val 0 |
| 44 | #define mmpll0_mm_source_val 1 |
| 45 | #define mmpll1_mm_source_val 2 |
| 46 | #define mmpll3_mm_source_val 3 |
| 47 | #define gpll0_mm_source_val 5 |
Channagoud Kadabi | b4c64b8 | 2014-07-24 17:18:46 -0700 | [diff] [blame] | 48 | #define edppll_270_mm_source_val 4 |
| 49 | #define edppll_350_mm_source_val 4 |
Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 50 | |
| 51 | struct clk_freq_tbl rcg_dummy_freq = F_END; |
| 52 | |
| 53 | |
| 54 | /* Clock Operations */ |
Channagoud Kadabi | 3dcc4ed | 2014-04-10 14:59:41 -0700 | [diff] [blame] | 55 | static struct clk_ops clk_ops_rst = |
| 56 | { |
| 57 | .reset = clock_lib2_reset_clk_reset, |
| 58 | }; |
| 59 | |
Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 60 | static struct clk_ops clk_ops_branch = |
| 61 | { |
| 62 | .enable = clock_lib2_branch_clk_enable, |
| 63 | .disable = clock_lib2_branch_clk_disable, |
| 64 | .set_rate = clock_lib2_branch_set_rate, |
Channagoud Kadabi | 3dcc4ed | 2014-04-10 14:59:41 -0700 | [diff] [blame] | 65 | .reset = clock_lib2_branch_clk_reset, |
Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 66 | }; |
| 67 | |
| 68 | static struct clk_ops clk_ops_rcg_mnd = |
| 69 | { |
| 70 | .enable = clock_lib2_rcg_enable, |
| 71 | .set_rate = clock_lib2_rcg_set_rate, |
| 72 | }; |
| 73 | |
| 74 | static struct clk_ops clk_ops_rcg = |
| 75 | { |
| 76 | .enable = clock_lib2_rcg_enable, |
| 77 | .set_rate = clock_lib2_rcg_set_rate, |
| 78 | }; |
| 79 | |
| 80 | static struct clk_ops clk_ops_cxo = |
| 81 | { |
| 82 | .enable = cxo_clk_enable, |
| 83 | .disable = cxo_clk_disable, |
| 84 | }; |
| 85 | |
| 86 | static struct clk_ops clk_ops_pll_vote = |
| 87 | { |
| 88 | .enable = pll_vote_clk_enable, |
| 89 | .disable = pll_vote_clk_disable, |
| 90 | .auto_off = pll_vote_clk_disable, |
| 91 | .is_enabled = pll_vote_clk_is_enabled, |
| 92 | }; |
| 93 | |
| 94 | static struct clk_ops clk_ops_vote = |
| 95 | { |
| 96 | .enable = clock_lib2_vote_clk_enable, |
| 97 | .disable = clock_lib2_vote_clk_disable, |
| 98 | }; |
| 99 | |
| 100 | /* Clock Sources */ |
| 101 | static struct fixed_clk cxo_clk_src = |
| 102 | { |
| 103 | .c = { |
| 104 | .rate = 19200000, |
| 105 | .dbg_name = "cxo_clk_src", |
| 106 | .ops = &clk_ops_cxo, |
| 107 | }, |
| 108 | }; |
| 109 | |
| 110 | static struct pll_vote_clk gpll0_clk_src = |
| 111 | { |
| 112 | .en_reg = (void *) APCS_GPLL_ENA_VOTE, |
| 113 | .en_mask = BIT(0), |
| 114 | .status_reg = (void *) GPLL0_MODE, |
| 115 | .status_mask = BIT(30), |
| 116 | .parent = &cxo_clk_src.c, |
| 117 | |
| 118 | .c = { |
| 119 | .rate = 600000000, |
| 120 | .dbg_name = "gpll0_clk_src", |
| 121 | .ops = &clk_ops_pll_vote, |
| 122 | }, |
| 123 | }; |
| 124 | |
| 125 | static struct pll_vote_clk gpll4_clk_src = |
| 126 | { |
| 127 | .en_reg = (void *) APCS_GPLL_ENA_VOTE, |
| 128 | .en_mask = BIT(4), |
| 129 | .status_reg = (void *) GPLL4_MODE, |
| 130 | .status_mask = BIT(30), |
| 131 | .parent = &cxo_clk_src.c, |
| 132 | |
| 133 | .c = { |
| 134 | .rate = 1600000000, |
| 135 | .dbg_name = "gpll4_clk_src", |
| 136 | .ops = &clk_ops_pll_vote, |
| 137 | }, |
| 138 | }; |
| 139 | |
| 140 | /* UART Clocks */ |
| 141 | static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = |
| 142 | { |
| 143 | F( 3686400, gpll0, 1, 96, 15625), |
| 144 | F( 7372800, gpll0, 1, 192, 15625), |
| 145 | F(14745600, gpll0, 1, 384, 15625), |
| 146 | F(16000000, gpll0, 5, 2, 15), |
| 147 | F(19200000, cxo, 1, 0, 0), |
| 148 | F(24000000, gpll0, 5, 1, 5), |
| 149 | F(32000000, gpll0, 1, 4, 75), |
| 150 | F(40000000, gpll0, 15, 0, 0), |
| 151 | F(46400000, gpll0, 1, 29, 375), |
| 152 | F(48000000, gpll0, 12.5, 0, 0), |
| 153 | F(51200000, gpll0, 1, 32, 375), |
| 154 | F(56000000, gpll0, 1, 7, 75), |
| 155 | F(58982400, gpll0, 1, 1536, 15625), |
| 156 | F(60000000, gpll0, 10, 0, 0), |
Channagoud Kadabi | a66a6f2 | 2014-05-28 17:19:44 -0700 | [diff] [blame] | 157 | F(63160000, gpll0, 9.5, 0, 0), |
Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 158 | F_END |
| 159 | }; |
| 160 | |
| 161 | static struct rcg_clk blsp2_uart2_apps_clk_src = |
| 162 | { |
| 163 | .cmd_reg = (uint32_t *) BLSP2_UART2_APPS_CMD_RCGR, |
| 164 | .cfg_reg = (uint32_t *) BLSP2_UART2_APPS_CFG_RCGR, |
| 165 | .m_reg = (uint32_t *) BLSP2_UART2_APPS_M, |
| 166 | .n_reg = (uint32_t *) BLSP2_UART2_APPS_N, |
| 167 | .d_reg = (uint32_t *) BLSP2_UART2_APPS_D, |
| 168 | |
| 169 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 170 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
| 171 | .current_freq = &rcg_dummy_freq, |
| 172 | |
| 173 | .c = { |
| 174 | .dbg_name = "blsp1_uart2_apps_clk", |
| 175 | .ops = &clk_ops_rcg_mnd, |
| 176 | }, |
| 177 | }; |
| 178 | |
| 179 | static struct rcg_clk blsp1_uart2_apps_clk_src = |
| 180 | { |
| 181 | .cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR, |
| 182 | .cfg_reg = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR, |
| 183 | .m_reg = (uint32_t *) BLSP1_UART2_APPS_M, |
| 184 | .n_reg = (uint32_t *) BLSP1_UART2_APPS_N, |
| 185 | .d_reg = (uint32_t *) BLSP1_UART2_APPS_D, |
| 186 | |
| 187 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 188 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
| 189 | .current_freq = &rcg_dummy_freq, |
| 190 | |
| 191 | .c = { |
| 192 | .dbg_name = "blsp1_uart2_apps_clk", |
| 193 | .ops = &clk_ops_rcg_mnd, |
| 194 | }, |
| 195 | }; |
| 196 | |
| 197 | static struct branch_clk gcc_blsp2_uart2_apps_clk = |
| 198 | { |
| 199 | .cbcr_reg = (uint32_t *) BLSP2_UART2_APPS_CBCR, |
| 200 | .parent = &blsp2_uart2_apps_clk_src.c, |
| 201 | |
| 202 | .c = { |
| 203 | .dbg_name = "gcc_blsp2_uart2_apps_clk", |
| 204 | .ops = &clk_ops_branch, |
| 205 | }, |
| 206 | }; |
| 207 | |
| 208 | static struct branch_clk gcc_blsp1_uart2_apps_clk = |
| 209 | { |
| 210 | .cbcr_reg = (uint32_t *) BLSP1_UART2_APPS_CBCR, |
| 211 | .parent = &blsp1_uart2_apps_clk_src.c, |
| 212 | |
| 213 | .c = { |
| 214 | .dbg_name = "gcc_blsp1_uart2_apps_clk", |
| 215 | .ops = &clk_ops_branch, |
| 216 | }, |
| 217 | }; |
| 218 | |
| 219 | static struct vote_clk gcc_blsp1_ahb_clk = { |
| 220 | .cbcr_reg = (uint32_t *) BLSP1_AHB_CBCR, |
| 221 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 222 | .en_mask = BIT(17), |
| 223 | |
| 224 | .c = { |
| 225 | .dbg_name = "gcc_blsp1_ahb_clk", |
| 226 | .ops = &clk_ops_vote, |
| 227 | }, |
| 228 | }; |
| 229 | |
| 230 | static struct vote_clk gcc_blsp2_ahb_clk = { |
| 231 | .cbcr_reg = (uint32_t *) BLSP2_AHB_CBCR, |
| 232 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 233 | .en_mask = BIT(15), |
| 234 | |
| 235 | .c = { |
| 236 | .dbg_name = "gcc_blsp2_ahb_clk", |
| 237 | .ops = &clk_ops_vote, |
| 238 | }, |
| 239 | }; |
| 240 | |
| 241 | /* USB Clocks */ |
| 242 | static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = |
| 243 | { |
| 244 | F(75000000, gpll0, 8, 0, 0), |
| 245 | F_END |
| 246 | }; |
| 247 | |
| 248 | static struct rcg_clk usb_hs_system_clk_src = |
| 249 | { |
| 250 | .cmd_reg = (uint32_t *) USB_HS_SYSTEM_CMD_RCGR, |
| 251 | .cfg_reg = (uint32_t *) USB_HS_SYSTEM_CFG_RCGR, |
| 252 | |
| 253 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 254 | .freq_tbl = ftbl_gcc_usb_hs_system_clk, |
| 255 | .current_freq = &rcg_dummy_freq, |
| 256 | |
| 257 | .c = { |
| 258 | .dbg_name = "usb_hs_system_clk", |
| 259 | .ops = &clk_ops_rcg, |
| 260 | }, |
| 261 | }; |
| 262 | |
| 263 | static struct branch_clk gcc_usb_hs_system_clk = |
| 264 | { |
| 265 | .cbcr_reg = (uint32_t *) USB_HS_SYSTEM_CBCR, |
| 266 | .parent = &usb_hs_system_clk_src.c, |
| 267 | |
| 268 | .c = { |
| 269 | .dbg_name = "gcc_usb_hs_system_clk", |
| 270 | .ops = &clk_ops_branch, |
| 271 | }, |
| 272 | }; |
| 273 | |
| 274 | static struct branch_clk gcc_usb_hs_ahb_clk = |
| 275 | { |
| 276 | .cbcr_reg = (uint32_t *) USB_HS_AHB_CBCR, |
| 277 | .has_sibling = 1, |
| 278 | |
| 279 | .c = { |
| 280 | .dbg_name = "gcc_usb_hs_ahb_clk", |
| 281 | .ops = &clk_ops_branch, |
| 282 | }, |
| 283 | }; |
| 284 | |
| 285 | /* SDCC Clocks */ |
| 286 | static struct clk_freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] = |
| 287 | { |
| 288 | F( 144000, cxo, 16, 3, 25), |
| 289 | F( 400000, cxo, 12, 1, 4), |
| 290 | F( 20000000, gpll0, 15, 1, 2), |
| 291 | F( 25000000, gpll0, 12, 1, 2), |
| 292 | F( 50000000, gpll0, 12, 0, 0), |
Channagoud Kadabi | a66a6f2 | 2014-05-28 17:19:44 -0700 | [diff] [blame] | 293 | F( 96000000, gpll4, 6, 0, 0), |
| 294 | F(192000000, gpll4, 2, 0, 0), |
| 295 | F(384000000, gpll4, 1, 0, 0), |
Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 296 | F_END |
| 297 | }; |
| 298 | |
| 299 | static struct rcg_clk sdcc1_apps_clk_src = |
| 300 | { |
| 301 | .cmd_reg = (uint32_t *) SDCC1_CMD_RCGR, |
| 302 | .cfg_reg = (uint32_t *) SDCC1_CFG_RCGR, |
| 303 | .m_reg = (uint32_t *) SDCC1_M, |
| 304 | .n_reg = (uint32_t *) SDCC1_N, |
| 305 | .d_reg = (uint32_t *) SDCC1_D, |
| 306 | |
| 307 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 308 | .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, |
| 309 | .current_freq = &rcg_dummy_freq, |
| 310 | |
| 311 | .c = { |
| 312 | .dbg_name = "sdc1_clk", |
| 313 | .ops = &clk_ops_rcg_mnd, |
| 314 | }, |
| 315 | }; |
| 316 | |
| 317 | static struct branch_clk gcc_sdcc1_apps_clk = |
| 318 | { |
| 319 | .cbcr_reg = (uint32_t *) SDCC1_APPS_CBCR, |
| 320 | .parent = &sdcc1_apps_clk_src.c, |
| 321 | |
| 322 | .c = { |
| 323 | .dbg_name = "gcc_sdcc1_apps_clk", |
| 324 | .ops = &clk_ops_branch, |
| 325 | }, |
| 326 | }; |
| 327 | |
| 328 | static struct branch_clk gcc_sdcc1_ahb_clk = |
| 329 | { |
| 330 | .cbcr_reg = (uint32_t *) SDCC1_AHB_CBCR, |
| 331 | .has_sibling = 1, |
| 332 | |
| 333 | .c = { |
| 334 | .dbg_name = "gcc_sdcc1_ahb_clk", |
| 335 | .ops = &clk_ops_branch, |
| 336 | }, |
| 337 | }; |
| 338 | |
Channagoud Kadabi | 3dcc4ed | 2014-04-10 14:59:41 -0700 | [diff] [blame] | 339 | static struct branch_clk gcc_sys_noc_usb30_axi_clk = { |
| 340 | .cbcr_reg = (uint32_t *) SYS_NOC_USB3_AXI_CBCR, |
| 341 | .has_sibling = 1, |
| 342 | |
| 343 | .c = { |
| 344 | .dbg_name = "sys_noc_usb30_axi_clk", |
| 345 | .ops = &clk_ops_branch, |
| 346 | }, |
| 347 | }; |
| 348 | |
| 349 | static struct branch_clk gcc_usb2b_phy_sleep_clk = { |
| 350 | .cbcr_reg = (uint32_t *) USB2B_PHY_SLEEP_CBCR, |
| 351 | .bcr_reg = (uint32_t *) USB2B_PHY_BCR, |
| 352 | .has_sibling = 1, |
| 353 | |
| 354 | .c = { |
| 355 | .dbg_name = "usb2b_phy_sleep_clk", |
| 356 | .ops = &clk_ops_branch, |
| 357 | }, |
| 358 | }; |
| 359 | |
| 360 | static struct clk_freq_tbl ftbl_gcc_usb30_master_clk[] = { |
| 361 | F( 125000000, gpll0, 1, 5, 24), |
| 362 | F_END |
| 363 | }; |
| 364 | |
| 365 | static struct rcg_clk usb30_master_clk_src = { |
| 366 | .cmd_reg = (uint32_t *) USB30_MASTER_CMD_RCGR, |
| 367 | .cfg_reg = (uint32_t *) USB30_MASTER_CFG_RCGR, |
| 368 | .m_reg = (uint32_t *) USB30_MASTER_M, |
| 369 | .n_reg = (uint32_t *) USB30_MASTER_N, |
| 370 | .d_reg = (uint32_t *) USB30_MASTER_D, |
| 371 | |
| 372 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 373 | .freq_tbl = ftbl_gcc_usb30_master_clk, |
| 374 | .current_freq = &rcg_dummy_freq, |
| 375 | |
| 376 | .c = { |
| 377 | .dbg_name = "usb30_master_clk_src", |
| 378 | .ops = &clk_ops_rcg, |
| 379 | }, |
| 380 | }; |
| 381 | |
| 382 | static struct branch_clk gcc_usb30_master_clk = { |
| 383 | .cbcr_reg = (uint32_t *) USB30_MASTER_CBCR, |
| 384 | .bcr_reg = (uint32_t *) USB_30_BCR, |
| 385 | .parent = &usb30_master_clk_src.c, |
| 386 | |
| 387 | .c = { |
| 388 | .dbg_name = "usb30_master_clk", |
| 389 | .ops = &clk_ops_branch, |
| 390 | }, |
| 391 | }; |
| 392 | |
| 393 | static struct clk_freq_tbl ftbl_gcc_usb30_mock_utmi_clk_src[] = { |
| 394 | F( 60000000, gpll0, 10, 0, 0), |
| 395 | F_END |
| 396 | }; |
| 397 | |
| 398 | static struct rcg_clk usb30_mock_utmi_clk_src = { |
| 399 | .cmd_reg = (uint32_t *) USB30_MOCK_UTMI_CMD_RCGR, |
| 400 | .cfg_reg = (uint32_t *) USB30_MOCK_UTMI_CFG_RCGR, |
| 401 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 402 | .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk_src, |
| 403 | .current_freq = &rcg_dummy_freq, |
| 404 | |
| 405 | .c = { |
| 406 | .dbg_name = "usb30_mock_utmi_clk_src", |
| 407 | .ops = &clk_ops_rcg, |
| 408 | }, |
| 409 | }; |
| 410 | |
| 411 | static struct branch_clk gcc_usb30_mock_utmi_clk = { |
| 412 | .cbcr_reg = (uint32_t *) USB30_MOCK_UTMI_CBCR, |
| 413 | .has_sibling = 0, |
| 414 | .parent = &usb30_mock_utmi_clk_src.c, |
| 415 | |
| 416 | .c = { |
| 417 | .dbg_name = "usb30_mock_utmi_clk", |
| 418 | .ops = &clk_ops_branch, |
| 419 | }, |
| 420 | }; |
| 421 | |
| 422 | static struct branch_clk gcc_usb30_sleep_clk = { |
| 423 | .cbcr_reg = (uint32_t *) USB30_SLEEP_CBCR, |
| 424 | .has_sibling = 1, |
| 425 | |
| 426 | .c = { |
| 427 | .dbg_name = "usb30_sleep_clk", |
| 428 | .ops = &clk_ops_branch, |
| 429 | }, |
| 430 | }; |
| 431 | |
| 432 | static struct clk_freq_tbl ftbl_gcc_usb30_phy_aux_clk_src[] = { |
| 433 | F( 1200000, cxo, 16, 0, 0), |
| 434 | F_END |
| 435 | }; |
| 436 | |
| 437 | static struct rcg_clk usb30_phy_aux_clk_src = { |
| 438 | .cmd_reg = (uint32_t *) USB30_PHY_AUX_CMD_RCGR, |
| 439 | .cfg_reg = (uint32_t *) USB30_PHY_AUX_CFG_RCGR, |
| 440 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 441 | .freq_tbl = ftbl_gcc_usb30_phy_aux_clk_src, |
| 442 | .current_freq = &rcg_dummy_freq, |
| 443 | |
| 444 | .c = { |
| 445 | .dbg_name = "usb30_phy_aux_clk_src", |
| 446 | .ops = &clk_ops_rcg, |
| 447 | }, |
| 448 | }; |
| 449 | |
| 450 | static struct branch_clk gcc_usb30_phy_aux_clk = { |
| 451 | .cbcr_reg = (uint32_t *)USB30_PHY_AUX_CBCR, |
| 452 | .has_sibling = 0, |
| 453 | .parent = &usb30_phy_aux_clk_src.c, |
| 454 | |
| 455 | .c = { |
| 456 | .dbg_name = "usb30_phy_aux_clk", |
| 457 | .ops = &clk_ops_branch, |
| 458 | }, |
| 459 | }; |
| 460 | |
| 461 | static struct branch_clk gcc_usb30_pipe_clk = { |
| 462 | .bcr_reg = (uint32_t *) USB30PHY_PHY_BCR, |
| 463 | .cbcr_reg = (uint32_t *) USB30_PHY_PIPE_CBCR, |
| 464 | .has_sibling = 1, |
| 465 | |
| 466 | .c = { |
| 467 | .dbg_name = "usb30_pipe_clk", |
| 468 | .ops = &clk_ops_branch, |
| 469 | }, |
| 470 | }; |
| 471 | |
| 472 | static struct reset_clk gcc_usb30_phy_reset = { |
Channagoud Kadabi | 3c2be1c | 2014-06-01 18:59:21 -0700 | [diff] [blame] | 473 | .bcr_reg = (uint32_t )USB30_PHY_BCR, |
Channagoud Kadabi | 3dcc4ed | 2014-04-10 14:59:41 -0700 | [diff] [blame] | 474 | |
| 475 | .c = { |
| 476 | .dbg_name = "usb30_phy_reset", |
| 477 | .ops = &clk_ops_rst, |
| 478 | }, |
| 479 | }; |
| 480 | |
Channagoud Kadabi | 3c2be1c | 2014-06-01 18:59:21 -0700 | [diff] [blame] | 481 | static struct branch_clk gcc_usb_phy_cfg_ahb2phy_clk = { |
| 482 | .cbcr_reg = (uint32_t *)USB_PHY_CFG_AHB2PHY_CBCR, |
| 483 | .has_sibling = 1, |
| 484 | |
| 485 | .c = { |
| 486 | .dbg_name = "usb_phy_cfg_ahb2phy_clk", |
| 487 | .ops = &clk_ops_branch, |
| 488 | }, |
| 489 | }; |
| 490 | |
Channagoud Kadabi | b4c64b8 | 2014-07-24 17:18:46 -0700 | [diff] [blame] | 491 | /* Display clocks */ |
| 492 | static struct clk_freq_tbl ftbl_mdss_esc0_1_clk[] = { |
| 493 | F_MM(19200000, cxo, 1, 0, 0), |
| 494 | F_END |
| 495 | }; |
| 496 | |
| 497 | static struct clk_freq_tbl ftbl_mdss_esc1_1_clk[] = { |
| 498 | F_MM(19200000, cxo, 1, 0, 0), |
| 499 | F_END |
| 500 | }; |
| 501 | |
| 502 | static struct clk_freq_tbl ftbl_mmss_axi_clk[] = { |
| 503 | F_MM(19200000, cxo, 1, 0, 0), |
| 504 | F_MM(100000000, gpll0, 6, 0, 0), |
| 505 | F_END |
| 506 | }; |
| 507 | |
| 508 | static struct clk_freq_tbl ftbl_mdp_clk[] = { |
| 509 | F_MM( 75000000, gpll0, 8, 0, 0), |
| 510 | F_MM( 240000000, gpll0, 2.5, 0, 0), |
| 511 | F_END |
| 512 | }; |
| 513 | |
| 514 | static struct rcg_clk dsi_esc0_clk_src = { |
| 515 | .cmd_reg = (uint32_t *) DSI_ESC0_CMD_RCGR, |
| 516 | .cfg_reg = (uint32_t *) DSI_ESC0_CFG_RCGR, |
| 517 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 518 | .freq_tbl = ftbl_mdss_esc0_1_clk, |
| 519 | |
| 520 | .c = { |
| 521 | .dbg_name = "dsi_esc0_clk_src", |
| 522 | .ops = &clk_ops_rcg, |
| 523 | }, |
| 524 | }; |
| 525 | |
| 526 | static struct rcg_clk dsi_esc1_clk_src = { |
| 527 | .cmd_reg = (uint32_t *) DSI_ESC1_CMD_RCGR, |
| 528 | .cfg_reg = (uint32_t *) DSI_ESC1_CFG_RCGR, |
| 529 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 530 | .freq_tbl = ftbl_mdss_esc1_1_clk, |
| 531 | |
| 532 | .c = { |
| 533 | .dbg_name = "dsi_esc1_clk_src", |
| 534 | .ops = &clk_ops_rcg, |
| 535 | }, |
| 536 | }; |
| 537 | |
| 538 | static struct clk_freq_tbl ftbl_mdss_vsync_clk[] = { |
| 539 | F_MM(19200000, cxo, 1, 0, 0), |
| 540 | F_END |
| 541 | }; |
| 542 | |
| 543 | static struct rcg_clk vsync_clk_src = { |
| 544 | .cmd_reg = (uint32_t *) VSYNC_CMD_RCGR, |
| 545 | .cfg_reg = (uint32_t *) VSYNC_CFG_RCGR, |
| 546 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 547 | .freq_tbl = ftbl_mdss_vsync_clk, |
| 548 | |
| 549 | .c = { |
| 550 | .dbg_name = "vsync_clk_src", |
| 551 | .ops = &clk_ops_rcg, |
| 552 | }, |
| 553 | }; |
| 554 | |
| 555 | static struct rcg_clk mdp_axi_clk_src = { |
| 556 | .cmd_reg = (uint32_t *) MDP_AXI_CMD_RCGR, |
| 557 | .cfg_reg = (uint32_t *) MDP_AXI_CFG_RCGR, |
| 558 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 559 | .freq_tbl = ftbl_mmss_axi_clk, |
| 560 | |
| 561 | .c = { |
| 562 | .dbg_name = "mdp_axi_clk_src", |
| 563 | .ops = &clk_ops_rcg, |
| 564 | }, |
| 565 | }; |
| 566 | |
| 567 | static struct branch_clk mdss_esc0_clk = { |
| 568 | .cbcr_reg = (uint32_t *) DSI_ESC0_CBCR, |
| 569 | .parent = &dsi_esc0_clk_src.c, |
| 570 | .has_sibling = 0, |
| 571 | |
| 572 | .c = { |
| 573 | .dbg_name = "mdss_esc0_clk", |
| 574 | .ops = &clk_ops_branch, |
| 575 | }, |
| 576 | }; |
| 577 | |
| 578 | static struct branch_clk mdss_esc1_clk = { |
| 579 | .cbcr_reg = (uint32_t *) DSI_ESC1_CBCR, |
| 580 | .parent = &dsi_esc1_clk_src.c, |
| 581 | .has_sibling = 0, |
| 582 | |
| 583 | .c = { |
| 584 | .dbg_name = "mdss_esc1_clk", |
| 585 | .ops = &clk_ops_branch, |
| 586 | }, |
| 587 | }; |
| 588 | |
| 589 | static struct branch_clk mdss_axi_clk = { |
| 590 | .cbcr_reg = (uint32_t *) MDP_AXI_CBCR, |
| 591 | .parent = &mdp_axi_clk_src.c, |
| 592 | .has_sibling = 0, |
| 593 | |
| 594 | .c = { |
| 595 | .dbg_name = "mdss_axi_clk", |
| 596 | .ops = &clk_ops_branch, |
| 597 | }, |
| 598 | }; |
| 599 | |
| 600 | static struct branch_clk mmss_mmssnoc_axi_clk = { |
| 601 | .cbcr_reg = (uint32_t *) MMSS_MMSSNOC_AXI_CBCR, |
| 602 | .parent = &mdp_axi_clk_src.c, |
| 603 | .has_sibling = 0, |
| 604 | |
| 605 | .c = { |
| 606 | .dbg_name = "mmss_mmssnoc_axi_clk", |
| 607 | .ops = &clk_ops_branch, |
| 608 | }, |
| 609 | }; |
| 610 | |
| 611 | static struct branch_clk mmss_s0_axi_clk = { |
| 612 | .cbcr_reg = (uint32_t *) MMSS_S0_AXI_CBCR, |
| 613 | .parent = &mdp_axi_clk_src.c, |
| 614 | .has_sibling = 0, |
| 615 | |
| 616 | .c = { |
| 617 | .dbg_name = "mmss_s0_axi_clk", |
| 618 | .ops = &clk_ops_branch, |
| 619 | }, |
| 620 | }; |
| 621 | |
| 622 | static struct branch_clk mdp_ahb_clk = { |
| 623 | .cbcr_reg = (uint32_t *) MDP_AHB_CBCR, |
| 624 | .has_sibling = 1, |
| 625 | |
| 626 | .c = { |
| 627 | .dbg_name = "mdp_ahb_clk", |
| 628 | .ops = &clk_ops_branch, |
| 629 | }, |
| 630 | }; |
| 631 | |
| 632 | static struct rcg_clk mdss_mdp_clk_src = { |
| 633 | .cmd_reg = (uint32_t *) MDP_CMD_RCGR, |
| 634 | .cfg_reg = (uint32_t *) MDP_CFG_RCGR, |
| 635 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 636 | .freq_tbl = ftbl_mdp_clk, |
| 637 | .current_freq = &rcg_dummy_freq, |
| 638 | |
| 639 | .c = { |
| 640 | .dbg_name = "mdss_mdp_clk_src", |
| 641 | .ops = &clk_ops_rcg, |
| 642 | }, |
| 643 | }; |
| 644 | |
| 645 | static struct branch_clk mdss_mdp_clk = { |
| 646 | .cbcr_reg = (uint32_t *) MDP_CBCR, |
| 647 | .parent = &mdss_mdp_clk_src.c, |
| 648 | .has_sibling = 1, |
| 649 | |
| 650 | .c = { |
| 651 | .dbg_name = "mdss_mdp_clk", |
| 652 | .ops = &clk_ops_branch, |
| 653 | }, |
| 654 | }; |
| 655 | |
| 656 | static struct branch_clk mdss_mdp_lut_clk = { |
| 657 | .cbcr_reg = MDP_LUT_CBCR, |
| 658 | .parent = &mdss_mdp_clk_src.c, |
| 659 | .has_sibling = 1, |
| 660 | |
| 661 | .c = { |
| 662 | .dbg_name = "mdss_mdp_lut_clk", |
| 663 | .ops = &clk_ops_branch, |
| 664 | }, |
| 665 | }; |
| 666 | |
| 667 | static struct branch_clk mdss_vsync_clk = { |
| 668 | .cbcr_reg = MDSS_VSYNC_CBCR, |
| 669 | .parent = &vsync_clk_src.c, |
| 670 | .has_sibling = 0, |
| 671 | |
| 672 | .c = { |
| 673 | .dbg_name = "mdss_vsync_clk", |
| 674 | .ops = &clk_ops_branch, |
| 675 | }, |
| 676 | }; |
| 677 | |
| 678 | static struct clk_freq_tbl ftbl_mdss_edpaux_clk[] = { |
| 679 | F_MM(19200000, cxo, 1, 0, 0), |
| 680 | F_END |
| 681 | }; |
| 682 | |
| 683 | static struct rcg_clk edpaux_clk_src = { |
| 684 | .cmd_reg = (uint32_t *) EDPAUX_CMD_RCGR, |
| 685 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 686 | .freq_tbl = ftbl_mdss_edpaux_clk, |
| 687 | |
| 688 | .c = { |
| 689 | .dbg_name = "edpaux_clk_src", |
| 690 | .ops = &clk_ops_rcg, |
| 691 | }, |
| 692 | }; |
| 693 | |
| 694 | static struct branch_clk mdss_edpaux_clk = { |
| 695 | .cbcr_reg = MDSS_EDPAUX_CBCR, |
| 696 | .parent = &edpaux_clk_src.c, |
| 697 | .has_sibling = 0, |
| 698 | |
| 699 | .c = { |
| 700 | .dbg_name = "mdss_edpaux_clk", |
| 701 | .ops = &clk_ops_branch, |
| 702 | }, |
| 703 | }; |
| 704 | |
| 705 | static struct clk_freq_tbl ftbl_mdss_edplink_clk[] = { |
| 706 | F_MDSS(162000000, edppll_270, 2, 0, 0), |
| 707 | F_MDSS(270000000, edppll_270, 11, 0, 0), |
| 708 | F_END |
| 709 | }; |
| 710 | |
| 711 | static struct rcg_clk edplink_clk_src = { |
| 712 | .cmd_reg = (uint32_t *)EDPLINK_CMD_RCGR, |
| 713 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 714 | .freq_tbl = ftbl_mdss_edplink_clk, |
| 715 | .current_freq = &rcg_dummy_freq, |
| 716 | .c = { |
| 717 | .dbg_name = "edplink_clk_src", |
| 718 | .ops = &clk_ops_rcg, |
| 719 | }, |
| 720 | }; |
| 721 | |
| 722 | static struct clk_freq_tbl ftbl_mdss_edppixel_clk[] = { |
| 723 | F_MDSS(138500000, edppll_350, 2, 0, 0), |
| 724 | F_MDSS(350000000, edppll_350, 11, 0, 0), |
| 725 | F_END |
| 726 | }; |
| 727 | |
| 728 | static struct rcg_clk edppixel_clk_src = { |
| 729 | .cmd_reg = (uint32_t *)EDPPIXEL_CMD_RCGR, |
| 730 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 731 | .freq_tbl = ftbl_mdss_edppixel_clk, |
| 732 | .current_freq = &rcg_dummy_freq, |
| 733 | .c = { |
| 734 | .dbg_name = "edppixel_clk_src", |
| 735 | .ops = &clk_ops_rcg_mnd, |
| 736 | }, |
| 737 | }; |
| 738 | |
| 739 | static struct branch_clk mdss_edplink_clk = { |
| 740 | .cbcr_reg = (uint32_t *)MDSS_EDPLINK_CBCR, |
| 741 | .has_sibling = 0, |
| 742 | .parent = &edplink_clk_src.c, |
| 743 | .c = { |
| 744 | .dbg_name = "mdss_edplink_clk", |
| 745 | .ops = &clk_ops_branch, |
| 746 | }, |
| 747 | }; |
| 748 | |
| 749 | static struct branch_clk mdss_edppixel_clk = { |
| 750 | .cbcr_reg = (uint32_t *)MDSS_EDPPIXEL_CBCR, |
| 751 | .has_sibling = 0, |
| 752 | .parent = &edppixel_clk_src.c, |
| 753 | .c = { |
| 754 | .dbg_name = "mdss_edppixel_clk", |
| 755 | .ops = &clk_ops_branch, |
| 756 | }, |
| 757 | }; |
Channagoud Kadabi | 3c2be1c | 2014-06-01 18:59:21 -0700 | [diff] [blame] | 758 | |
Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 759 | /* Clock lookup table */ |
Channagoud Kadabi | 608b6a7 | 2014-04-14 13:58:03 -0700 | [diff] [blame] | 760 | static struct clk_lookup msm_8994_clocks[] = |
Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 761 | { |
| 762 | CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c), |
| 763 | CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c), |
| 764 | |
| 765 | CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c), |
| 766 | CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c), |
| 767 | |
| 768 | CLK_LOOKUP("usb_iface_clk", gcc_usb_hs_ahb_clk.c), |
| 769 | CLK_LOOKUP("usb_core_clk", gcc_usb_hs_system_clk.c), |
Channagoud Kadabi | 3dcc4ed | 2014-04-10 14:59:41 -0700 | [diff] [blame] | 770 | |
| 771 | /* USB30 clocks */ |
| 772 | CLK_LOOKUP("usb2b_phy_sleep_clk", gcc_usb2b_phy_sleep_clk.c), |
| 773 | CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c), |
Channagoud Kadabi | 3c2be1c | 2014-06-01 18:59:21 -0700 | [diff] [blame] | 774 | CLK_LOOKUP("usb30_iface_clk", gcc_sys_noc_usb30_axi_clk.c), |
Channagoud Kadabi | 3dcc4ed | 2014-04-10 14:59:41 -0700 | [diff] [blame] | 775 | CLK_LOOKUP("usb30_mock_utmi_clk", gcc_usb30_mock_utmi_clk.c), |
| 776 | CLK_LOOKUP("usb30_sleep_clk", gcc_usb30_sleep_clk.c), |
| 777 | CLK_LOOKUP("usb30_phy_aux_clk", gcc_usb30_phy_aux_clk.c), |
| 778 | CLK_LOOKUP("usb30_pipe_clk", gcc_usb30_pipe_clk.c), |
| 779 | CLK_LOOKUP("usb30_phy_reset", gcc_usb30_phy_reset.c), |
Channagoud Kadabi | 3c2be1c | 2014-06-01 18:59:21 -0700 | [diff] [blame] | 780 | |
| 781 | CLK_LOOKUP("usb_phy_cfg_ahb2phy_clk", gcc_usb_phy_cfg_ahb2phy_clk.c), |
Channagoud Kadabi | b4c64b8 | 2014-07-24 17:18:46 -0700 | [diff] [blame] | 782 | |
| 783 | /* mdss clocks */ |
| 784 | CLK_LOOKUP("mdp_ahb_clk", mdp_ahb_clk.c), |
| 785 | CLK_LOOKUP("mdss_esc0_clk", mdss_esc0_clk.c), |
| 786 | CLK_LOOKUP("mdss_esc1_clk", mdss_esc1_clk.c), |
| 787 | CLK_LOOKUP("mdss_axi_clk", mdss_axi_clk.c), |
| 788 | CLK_LOOKUP("mmss_mmssnoc_axi_clk", mmss_mmssnoc_axi_clk.c), |
| 789 | CLK_LOOKUP("mmss_s0_axi_clk", mmss_s0_axi_clk.c), |
| 790 | CLK_LOOKUP("mdss_vsync_clk", mdss_vsync_clk.c), |
| 791 | CLK_LOOKUP("mdss_mdp_clk_src", mdss_mdp_clk_src.c), |
| 792 | CLK_LOOKUP("mdss_mdp_clk", mdss_mdp_clk.c), |
| 793 | CLK_LOOKUP("mdss_mdp_lut_clk", mdss_mdp_lut_clk.c), |
| 794 | |
| 795 | CLK_LOOKUP("edp_pixel_clk", mdss_edppixel_clk.c), |
| 796 | CLK_LOOKUP("edp_link_clk", mdss_edplink_clk.c), |
| 797 | CLK_LOOKUP("edp_aux_clk", mdss_edpaux_clk.c), |
Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 798 | }; |
| 799 | |
| 800 | void platform_clock_init(void) |
| 801 | { |
Channagoud Kadabi | 608b6a7 | 2014-04-14 13:58:03 -0700 | [diff] [blame] | 802 | clk_init(msm_8994_clocks, ARRAY_SIZE(msm_8994_clocks)); |
Channagoud Kadabi | 123c972 | 2014-02-06 13:22:50 -0800 | [diff] [blame] | 803 | } |