Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are met: |
| 5 | * * Redistributions of source code must retain the above copyright |
| 6 | * notice, this list of conditions and the following disclaimer. |
| 7 | * * Redistributions in binary form must reproduce the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer in the |
| 9 | * documentation and/or other materials provided with the distribution. |
| 10 | * * Neither the name of The Linux Foundation nor |
| 11 | * the names of its contributors may be used to endorse or promote |
| 12 | * products derived from this software without specific prior written |
| 13 | * permission. |
| 14 | * |
| 15 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 16 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 17 | * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 18 | * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 19 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 20 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 21 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; |
| 22 | * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 23 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR |
| 24 | * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF |
| 25 | * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 26 | */ |
| 27 | |
| 28 | #include <mdp5.h> |
| 29 | #include <debug.h> |
| 30 | #include <reg.h> |
| 31 | #include <target/display.h> |
| 32 | #include <platform/timer.h> |
| 33 | #include <platform/iomap.h> |
| 34 | #include <dev/lcdc.h> |
| 35 | #include <dev/fbcon.h> |
| 36 | #include <bits.h> |
| 37 | #include <msm_panel.h> |
| 38 | #include <mipi_dsi.h> |
| 39 | #include <err.h> |
| 40 | #include <clock.h> |
Siddhartha Agrawal | 8d69082 | 2013-01-28 12:18:58 -0800 | [diff] [blame] | 41 | #include <scm.h> |
| 42 | |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 43 | #define MDSS_MDP_MAX_PREFILL_FETCH 25 |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 44 | |
Siddhartha Agrawal | 8d69082 | 2013-01-28 12:18:58 -0800 | [diff] [blame] | 45 | int restore_secure_cfg(uint32_t id); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 46 | |
| 47 | static int mdp_rev; |
| 48 | |
| 49 | void mdp_set_revision(int rev) |
| 50 | { |
| 51 | mdp_rev = rev; |
| 52 | } |
| 53 | |
| 54 | int mdp_get_revision() |
| 55 | { |
| 56 | return mdp_rev; |
| 57 | } |
| 58 | |
Dhaval Patel | 4401467 | 2015-03-26 10:58:32 -0700 | [diff] [blame] | 59 | static inline bool is_software_pixel_ext_config_needed() |
| 60 | { |
Padmanabhan Komanduru | f1d58a3 | 2015-11-13 19:02:22 +0530 | [diff] [blame^] | 61 | return (MDSS_IS_MAJOR_MINOR_MATCHING(readl(MDP_HW_REV), |
| 62 | MDSS_MDP_HW_REV_107) || MDSS_IS_MAJOR_MINOR_MATCHING(readl(MDP_HW_REV), |
| 63 | MDSS_MDP_HW_REV_114)); |
Dhaval Patel | 4401467 | 2015-03-26 10:58:32 -0700 | [diff] [blame] | 64 | } |
| 65 | |
| 66 | static inline bool has_fixed_size_smp() |
| 67 | { |
Padmanabhan Komanduru | f1d58a3 | 2015-11-13 19:02:22 +0530 | [diff] [blame^] | 68 | return (MDSS_IS_MAJOR_MINOR_MATCHING(readl(MDP_HW_REV), |
| 69 | MDSS_MDP_HW_REV_107) || MDSS_IS_MAJOR_MINOR_MATCHING(readl(MDP_HW_REV), |
| 70 | MDSS_MDP_HW_REV_114)); |
Dhaval Patel | 4401467 | 2015-03-26 10:58:32 -0700 | [diff] [blame] | 71 | } |
| 72 | |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 73 | uint32_t mdss_mdp_intf_offset() |
| 74 | { |
| 75 | uint32_t mdss_mdp_intf_off; |
| 76 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 77 | |
Padmanabhan Komanduru | 3908d17 | 2014-06-04 18:00:56 +0530 | [diff] [blame] | 78 | if ((mdss_mdp_rev == MDSS_MDP_HW_REV_106) || |
Padmanabhan Komanduru | fdb5683 | 2015-04-09 21:08:28 -0700 | [diff] [blame] | 79 | (mdss_mdp_rev == MDSS_MDP_HW_REV_108) || |
Padmanabhan Komanduru | f912cfb | 2015-06-08 16:36:58 +0530 | [diff] [blame] | 80 | (mdss_mdp_rev == MDSS_MDP_HW_REV_111) || |
Padmanabhan Komanduru | f1d58a3 | 2015-11-13 19:02:22 +0530 | [diff] [blame^] | 81 | (mdss_mdp_rev == MDSS_MDP_HW_REV_112) || |
| 82 | (mdss_mdp_rev == MDSS_MDP_HW_REV_114)) |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 83 | mdss_mdp_intf_off = 0x59100; |
| 84 | else if (mdss_mdp_rev >= MDSS_MDP_HW_REV_102) |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 85 | mdss_mdp_intf_off = 0; |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 86 | else |
Chandan Uddaraju | aab5851 | 2013-06-25 17:47:39 -0700 | [diff] [blame] | 87 | mdss_mdp_intf_off = 0xEC00; |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 88 | |
| 89 | return mdss_mdp_intf_off; |
| 90 | } |
| 91 | |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 92 | static uint32_t mdss_mdp_get_ppb_offset() |
| 93 | { |
| 94 | uint32_t mdss_mdp_ppb_off = 0; |
| 95 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 96 | |
| 97 | /* return MMSS_MDP_PPB0_CONFIG offset from MDSS base */ |
Padmanabhan Komanduru | f912cfb | 2015-06-08 16:36:58 +0530 | [diff] [blame] | 98 | if ((mdss_mdp_rev == MDSS_MDP_HW_REV_108) || |
Ujwal Patel | 5c3227b | 2015-08-12 14:48:02 -0700 | [diff] [blame] | 99 | (mdss_mdp_rev == MDSS_MDP_HW_REV_111)) |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 100 | mdss_mdp_ppb_off = 0x1420; |
| 101 | else if (mdss_mdp_rev == MDSS_MDP_HW_REV_110) |
| 102 | mdss_mdp_ppb_off = 0x1334; |
Ujwal Patel | 5c3227b | 2015-08-12 14:48:02 -0700 | [diff] [blame] | 103 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_107)) |
| 104 | mdss_mdp_ppb_off = 0x1330; |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 105 | else |
| 106 | dprintf(CRITICAL,"Invalid PPB0_CONFIG offset\n"); |
| 107 | |
| 108 | return mdss_mdp_ppb_off; |
| 109 | } |
| 110 | |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 111 | static uint32_t mdss_mdp_vbif_qos_remap_get_offset() |
| 112 | { |
| 113 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 114 | |
Padmanabhan Komanduru | f912cfb | 2015-06-08 16:36:58 +0530 | [diff] [blame] | 115 | if ((mdss_mdp_rev == MDSS_MDP_HW_REV_110) || |
Padmanabhan Komanduru | f1d58a3 | 2015-11-13 19:02:22 +0530 | [diff] [blame^] | 116 | (mdss_mdp_rev == MDSS_MDP_HW_REV_111) || |
| 117 | (mdss_mdp_rev == MDSS_MDP_HW_REV_114)) |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 118 | return 0xB0020; |
Dhaval Patel | 225cde1 | 2015-05-04 11:14:12 -0700 | [diff] [blame] | 119 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_107)) |
| 120 | return 0xB0000; |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 121 | else |
| 122 | return 0xC8020; |
| 123 | } |
| 124 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 125 | void mdp_clk_gating_ctrl(void) |
| 126 | { |
Dhaval Patel | 225cde1 | 2015-05-04 11:14:12 -0700 | [diff] [blame] | 127 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 128 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_107)) |
| 129 | return; |
| 130 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 131 | writel(0x40000000, MDP_CLK_CTRL0); |
| 132 | udelay(20); |
| 133 | writel(0x40000040, MDP_CLK_CTRL0); |
| 134 | writel(0x40000000, MDP_CLK_CTRL1); |
| 135 | writel(0x00400000, MDP_CLK_CTRL3); |
| 136 | udelay(20); |
| 137 | writel(0x00404000, MDP_CLK_CTRL3); |
| 138 | writel(0x40000000, MDP_CLK_CTRL4); |
| 139 | } |
| 140 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 141 | static void mdp_select_pipe_type(struct msm_panel_info *pinfo, |
| 142 | uint32_t *left_pipe, uint32_t *right_pipe) |
| 143 | { |
| 144 | switch (pinfo->pipe_type) { |
| 145 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 146 | *left_pipe = MDP_VP_0_RGB_0_BASE; |
| 147 | *right_pipe = MDP_VP_0_RGB_1_BASE; |
| 148 | break; |
| 149 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 150 | *left_pipe = MDP_VP_0_DMA_0_BASE; |
| 151 | *right_pipe = MDP_VP_0_DMA_1_BASE; |
| 152 | break; |
| 153 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 154 | default: |
| 155 | *left_pipe = MDP_VP_0_VIG_0_BASE; |
| 156 | *right_pipe = MDP_VP_0_VIG_1_BASE; |
| 157 | break; |
| 158 | } |
| 159 | } |
| 160 | |
| 161 | static void mdss_mdp_set_flush(struct msm_panel_info *pinfo, |
| 162 | uint32_t *ctl0_reg_val, uint32_t *ctl1_reg_val) |
| 163 | { |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 164 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 165 | bool dual_pipe_single_ctl = pinfo->lcdc.dual_pipe && |
| 166 | !pinfo->mipi.dual_dsi && !pinfo->lcdc.split_display; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 167 | switch (pinfo->pipe_type) { |
| 168 | case MDSS_MDP_PIPE_TYPE_RGB: |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 169 | if (dual_pipe_single_ctl) |
| 170 | *ctl0_reg_val = 0x220D8; |
| 171 | else |
| 172 | *ctl0_reg_val = 0x22048; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 173 | *ctl1_reg_val = 0x24090; |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 174 | |
| 175 | if (pinfo->lcdc.dst_split) |
| 176 | *ctl0_reg_val |= BIT(4); |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 177 | break; |
| 178 | case MDSS_MDP_PIPE_TYPE_DMA: |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 179 | if (dual_pipe_single_ctl) |
| 180 | *ctl0_reg_val = 0x238C0; |
| 181 | else |
| 182 | *ctl0_reg_val = 0x22840; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 183 | *ctl1_reg_val = 0x25080; |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 184 | if (pinfo->lcdc.dst_split) |
| 185 | *ctl0_reg_val |= BIT(12); |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 186 | break; |
| 187 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 188 | default: |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 189 | if (dual_pipe_single_ctl) |
| 190 | *ctl0_reg_val = 0x220C3; |
| 191 | else |
| 192 | *ctl0_reg_val = 0x22041; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 193 | *ctl1_reg_val = 0x24082; |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 194 | if (pinfo->lcdc.dst_split) |
| 195 | *ctl0_reg_val |= BIT(1); |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 196 | break; |
| 197 | } |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 198 | /* For targets from MDP v1.5, MDP INTF registers are double buffered */ |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 199 | if ((mdss_mdp_rev == MDSS_MDP_HW_REV_106) || |
Padmanabhan Komanduru | fdb5683 | 2015-04-09 21:08:28 -0700 | [diff] [blame] | 200 | (mdss_mdp_rev == MDSS_MDP_HW_REV_108) || |
Padmanabhan Komanduru | f912cfb | 2015-06-08 16:36:58 +0530 | [diff] [blame] | 201 | (mdss_mdp_rev == MDSS_MDP_HW_REV_111) || |
Padmanabhan Komanduru | fdb5683 | 2015-04-09 21:08:28 -0700 | [diff] [blame] | 202 | (mdss_mdp_rev == MDSS_MDP_HW_REV_112)) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 203 | if (pinfo->dest == DISPLAY_2) { |
| 204 | *ctl0_reg_val |= BIT(31); |
| 205 | *ctl1_reg_val |= BIT(30); |
| 206 | } else { |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 207 | *ctl0_reg_val |= BIT(30); |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 208 | *ctl1_reg_val |= BIT(31); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 209 | } |
Chandan Uddaraju | 18a5037 | 2014-10-01 18:45:30 -0700 | [diff] [blame] | 210 | } else if ((mdss_mdp_rev == MDSS_MDP_HW_REV_105) || |
Jeevan Shriram | 47c936d | 2014-12-19 11:50:13 -0800 | [diff] [blame] | 211 | (mdss_mdp_rev == MDSS_MDP_HW_REV_109) || |
Dhaval Patel | 4401467 | 2015-03-26 10:58:32 -0700 | [diff] [blame] | 212 | MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, |
| 213 | MDSS_MDP_HW_REV_107) || |
Padmanabhan Komanduru | f1d58a3 | 2015-11-13 19:02:22 +0530 | [diff] [blame^] | 214 | (mdss_mdp_rev == MDSS_MDP_HW_REV_114) || |
Jeevan Shriram | 47c936d | 2014-12-19 11:50:13 -0800 | [diff] [blame] | 215 | (mdss_mdp_rev == MDSS_MDP_HW_REV_110)) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 216 | if (pinfo->dest == DISPLAY_2) { |
| 217 | *ctl0_reg_val |= BIT(29); |
| 218 | *ctl1_reg_val |= BIT(30); |
| 219 | } else { |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 220 | *ctl0_reg_val |= BIT(30); |
| 221 | *ctl1_reg_val |= BIT(29); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 222 | } |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 223 | } |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 224 | } |
| 225 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 226 | static void mdss_source_pipe_config(struct fbcon_config *fb, struct msm_panel_info |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 227 | *pinfo, uint32_t pipe_base) |
| 228 | { |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 229 | uint32_t img_size, out_size, stride; |
Siddhartha Agrawal | 6ef1e22 | 2013-06-12 18:24:58 -0700 | [diff] [blame] | 230 | uint32_t fb_off = 0; |
Prashant Nukala | 64eeff9 | 2014-07-11 07:35:34 +0530 | [diff] [blame] | 231 | uint32_t flip_bits = 0; |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 232 | uint32_t src_xy = 0, dst_xy = 0; |
| 233 | uint32_t height, width; |
| 234 | |
| 235 | height = fb->height - pinfo->border_top - pinfo->border_bottom; |
| 236 | width = fb->width - pinfo->border_left - pinfo->border_right; |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 237 | |
| 238 | /* write active region size*/ |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 239 | img_size = (height << 16) | width; |
| 240 | out_size = img_size; |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 241 | if (pinfo->lcdc.dual_pipe) { |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 242 | if ((pipe_base == MDP_VP_0_RGB_1_BASE) || |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 243 | (pipe_base == MDP_VP_0_DMA_1_BASE) || |
| 244 | (pipe_base == MDP_VP_0_VIG_1_BASE)) { |
Siddhartha Agrawal | 6ef1e22 | 2013-06-12 18:24:58 -0700 | [diff] [blame] | 245 | fb_off = (pinfo->xres / 2); |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 246 | out_size = (height << 16) + (pinfo->lm_split[1]); |
| 247 | } else { |
| 248 | out_size = (height << 16) + (pinfo->lm_split[0]); |
| 249 | } |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 250 | } |
| 251 | |
| 252 | stride = (fb->stride * fb->bpp/8); |
| 253 | |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 254 | if (fb_off == 0) { /* left */ |
| 255 | dst_xy = (pinfo->border_top << 16) | pinfo->border_left; |
| 256 | src_xy = dst_xy; |
| 257 | } else { /* right */ |
| 258 | dst_xy = (pinfo->border_top << 16); |
| 259 | src_xy = (pinfo->border_top << 16) | fb_off; |
| 260 | } |
| 261 | |
| 262 | dprintf(SPEW,"%s: src=%x fb_off=%x src_xy=%x dst_xy=%x\n", |
| 263 | __func__, out_size, fb_off, src_xy, dst_xy); |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 264 | writel((uint32_t) fb->base, pipe_base + PIPE_SSPP_SRC0_ADDR); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 265 | writel(stride, pipe_base + PIPE_SSPP_SRC_YSTRIDE); |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 266 | writel(img_size, pipe_base + PIPE_SSPP_SRC_IMG_SIZE); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 267 | writel(out_size, pipe_base + PIPE_SSPP_SRC_SIZE); |
| 268 | writel(out_size, pipe_base + PIPE_SSPP_SRC_OUT_SIZE); |
Kuogee Hsieh | 31b4ff9 | 2014-10-22 14:55:42 -0700 | [diff] [blame] | 269 | writel(src_xy, pipe_base + PIPE_SSPP_SRC_XY); |
| 270 | writel(dst_xy, pipe_base + PIPE_SSPP_OUT_XY); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 271 | |
| 272 | /* Tight Packing 3bpp 0-Alpha 8-bit R B G */ |
| 273 | writel(0x0002243F, pipe_base + PIPE_SSPP_SRC_FORMAT); |
| 274 | writel(0x00020001, pipe_base + PIPE_SSPP_SRC_UNPACK_PATTERN); |
Prashant Nukala | 64eeff9 | 2014-07-11 07:35:34 +0530 | [diff] [blame] | 275 | |
| 276 | /* bit(0) is set if hflip is required. |
| 277 | * bit(1) is set if vflip is required. |
| 278 | */ |
| 279 | if (pinfo->orientation & 0x1) |
| 280 | flip_bits |= MDSS_MDP_OP_MODE_FLIP_LR; |
| 281 | if (pinfo->orientation & 0x2) |
| 282 | flip_bits |= MDSS_MDP_OP_MODE_FLIP_UD; |
Dhaval Patel | 4401467 | 2015-03-26 10:58:32 -0700 | [diff] [blame] | 283 | |
| 284 | if (is_software_pixel_ext_config_needed()) { |
| 285 | flip_bits |= BIT(31); |
| 286 | writel(out_size, pipe_base + PIPE_SW_PIXEL_EXT_C0_REQ); |
| 287 | writel(out_size, pipe_base + PIPE_SW_PIXEL_EXT_C1C2_REQ); |
| 288 | writel(out_size, pipe_base + PIPE_SW_PIXEL_EXT_C3_REQ); |
| 289 | /* configure phase step 1 for all color components */ |
| 290 | writel(0x200000, pipe_base + PIPE_COMP0_3_PHASE_STEP_X); |
| 291 | writel(0x200000, pipe_base + PIPE_COMP0_3_PHASE_STEP_Y); |
| 292 | writel(0x200000, pipe_base + PIPE_COMP1_2_PHASE_STEP_X); |
| 293 | writel(0x200000, pipe_base + PIPE_COMP1_2_PHASE_STEP_Y); |
| 294 | } |
Prashant Nukala | 64eeff9 | 2014-07-11 07:35:34 +0530 | [diff] [blame] | 295 | writel(flip_bits, pipe_base + PIPE_SSPP_SRC_OP_MODE); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 296 | } |
| 297 | |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 298 | static void mdss_vbif_setup() |
| 299 | { |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 300 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
Dhaval Patel | 225cde1 | 2015-05-04 11:14:12 -0700 | [diff] [blame] | 301 | int access_secure = false; |
| 302 | if (!MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_107)) |
| 303 | access_secure = restore_secure_cfg(SECURE_DEVICE_MDSS); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 304 | |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 305 | if (!access_secure) { |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 306 | dprintf(SPEW, "MDSS VBIF registers unlocked by TZ.\n"); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 307 | |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 308 | /* Force VBIF Clocks on, needed for 8974 and 8x26 */ |
| 309 | if (mdp_hw_rev < MDSS_MDP_HW_REV_103) |
Ujwal Patel | 00e1985 | 2013-12-18 20:40:38 -0800 | [diff] [blame] | 310 | writel(0x1, VBIF_VBIF_DDR_FORCE_CLK_ON); |
| 311 | |
| 312 | /* |
| 313 | * Following configuration is needed because on some versions, |
| 314 | * recommended reset values are not stored. |
| 315 | */ |
| 316 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 317 | MDSS_MDP_HW_REV_100)) { |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 318 | writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST); |
| 319 | writel(0x00000030, VBIF_VBIF_DDR_ARB_CTRL ); |
| 320 | writel(0x00000001, VBIF_VBIF_DDR_RND_RBN_QOS_ARB); |
| 321 | writel(0x00000FFF, VBIF_VBIF_DDR_OUT_AOOO_AXI_EN); |
| 322 | writel(0x0FFF0FFF, VBIF_VBIF_DDR_OUT_AX_AOOO); |
| 323 | writel(0x22222222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0); |
| 324 | writel(0x00002222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1); |
Ujwal Patel | 00e1985 | 2013-12-18 20:40:38 -0800 | [diff] [blame] | 325 | } else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 326 | MDSS_MDP_HW_REV_101)) { |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 327 | writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST); |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 328 | writel(0x00000003, VBIF_VBIF_DDR_RND_RBN_QOS_ARB); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 329 | } |
| 330 | } |
| 331 | } |
| 332 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 333 | static uint32_t mdss_smp_alloc(uint32_t client_id, uint32_t smp_cnt, |
| 334 | uint32_t fixed_smp_cnt, uint32_t free_smp_offset) |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 335 | { |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 336 | uint32_t i, j; |
| 337 | uint32_t reg_val = 0; |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 338 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 339 | for (i = fixed_smp_cnt, j = 0; i < smp_cnt; i++) { |
| 340 | /* max 3 MMB per register */ |
| 341 | reg_val |= client_id << (((j++) % 3) * 8); |
| 342 | if ((j % 3) == 0) { |
| 343 | writel(reg_val, MMSS_MDP_SMP_ALLOC_W_BASE + |
| 344 | free_smp_offset); |
| 345 | writel(reg_val, MMSS_MDP_SMP_ALLOC_R_BASE + |
| 346 | free_smp_offset); |
| 347 | reg_val = 0; |
| 348 | free_smp_offset += 4; |
| 349 | } |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 350 | } |
| 351 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 352 | if (j % 3) { |
| 353 | writel(reg_val, MMSS_MDP_SMP_ALLOC_W_BASE + free_smp_offset); |
| 354 | writel(reg_val, MMSS_MDP_SMP_ALLOC_R_BASE + free_smp_offset); |
| 355 | free_smp_offset += 4; |
| 356 | } |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 357 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 358 | return free_smp_offset; |
| 359 | } |
| 360 | |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 361 | static void mdp_select_pipe_client_id(struct msm_panel_info *pinfo, |
| 362 | uint32_t *left_sspp_client_id, uint32_t *right_sspp_client_id) |
| 363 | { |
| 364 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 365 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_101) || |
| 366 | MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_106) || |
Padmanabhan Komanduru | fdb5683 | 2015-04-09 21:08:28 -0700 | [diff] [blame] | 367 | MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_108) || |
Padmanabhan Komanduru | f912cfb | 2015-06-08 16:36:58 +0530 | [diff] [blame] | 368 | MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_111) || |
Padmanabhan Komanduru | fdb5683 | 2015-04-09 21:08:28 -0700 | [diff] [blame] | 369 | MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_112)) { |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 370 | switch (pinfo->pipe_type) { |
| 371 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 372 | *left_sspp_client_id = 0x7; /* 7 */ |
Padmanabhan Komanduru | f912cfb | 2015-06-08 16:36:58 +0530 | [diff] [blame] | 373 | *right_sspp_client_id = 0x8; /* 8 */ |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 374 | break; |
| 375 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 376 | *left_sspp_client_id = 0x4; /* 4 */ |
| 377 | *right_sspp_client_id = 0xD; /* 13 */ |
| 378 | break; |
| 379 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 380 | default: |
| 381 | *left_sspp_client_id = 0x1; /* 1 */ |
Padmanabhan Komanduru | f912cfb | 2015-06-08 16:36:58 +0530 | [diff] [blame] | 382 | *right_sspp_client_id = 0x9; /* 9 */ |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 383 | break; |
| 384 | } |
| 385 | } else { |
| 386 | switch (pinfo->pipe_type) { |
| 387 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 388 | *left_sspp_client_id = 0x10; /* 16 */ |
| 389 | *right_sspp_client_id = 0x11; /* 17 */ |
| 390 | break; |
| 391 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 392 | *left_sspp_client_id = 0xA; /* 10 */ |
| 393 | *right_sspp_client_id = 0xD; /* 13 */ |
| 394 | break; |
| 395 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 396 | default: |
| 397 | *left_sspp_client_id = 0x1; /* 1 */ |
| 398 | *right_sspp_client_id = 0x4; /* 4 */ |
| 399 | break; |
| 400 | } |
| 401 | } |
| 402 | } |
| 403 | |
| 404 | static void mdp_select_pipe_xin_id(struct msm_panel_info *pinfo, |
| 405 | uint32_t *left_pipe_xin_id, uint32_t *right_pipe_xin_id) |
| 406 | { |
| 407 | switch (pinfo->pipe_type) { |
| 408 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 409 | *left_pipe_xin_id = 0x1; /* 1 */ |
| 410 | *right_pipe_xin_id = 0x5; /* 5 */ |
| 411 | break; |
| 412 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 413 | *left_pipe_xin_id = 0x2; /* 2 */ |
| 414 | *right_pipe_xin_id = 0xA; /* 10 */ |
| 415 | break; |
| 416 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 417 | default: |
| 418 | *left_pipe_xin_id = 0x0; /* 0 */ |
| 419 | *right_pipe_xin_id = 0x4; /* 4 */ |
| 420 | break; |
| 421 | } |
| 422 | } |
| 423 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 424 | static void mdss_smp_setup(struct msm_panel_info *pinfo, uint32_t left_pipe, |
| 425 | uint32_t right_pipe) |
| 426 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 427 | { |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 428 | uint32_t left_sspp_client_id, right_sspp_client_id; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 429 | uint32_t bpp = 3, free_smp_offset = 0, xres = MDSS_MAX_LINE_BUF_WIDTH; |
| 430 | uint32_t smp_cnt, smp_size = 4096, fixed_smp_cnt = 0; |
| 431 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 432 | |
Padmanabhan Komanduru | fdb5683 | 2015-04-09 21:08:28 -0700 | [diff] [blame] | 433 | if ((mdss_mdp_rev == MDSS_MDP_HW_REV_106) || |
| 434 | (mdss_mdp_rev == MDSS_MDP_HW_REV_112)) { |
| 435 | /* 8Kb per SMP on 8916/8952 */ |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 436 | smp_size = 8192; |
Padmanabhan Komanduru | f912cfb | 2015-06-08 16:36:58 +0530 | [diff] [blame] | 437 | } else if ((mdss_mdp_rev == MDSS_MDP_HW_REV_108) || |
| 438 | (mdss_mdp_rev == MDSS_MDP_HW_REV_111)) { |
| 439 | /* 10Kb per SMP on 8939/8956 */ |
Padmanabhan Komanduru | 3908d17 | 2014-06-04 18:00:56 +0530 | [diff] [blame] | 440 | smp_size = 10240; |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 441 | } else if ((mdss_mdp_rev >= MDSS_MDP_HW_REV_103) && |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 442 | (mdss_mdp_rev < MDSS_MDP_HW_REV_200)) { |
| 443 | smp_size = 8192; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 444 | free_smp_offset = 0xC; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 445 | if (pinfo->pipe_type == MDSS_MDP_PIPE_TYPE_RGB) |
| 446 | fixed_smp_cnt = 2; |
| 447 | else |
| 448 | fixed_smp_cnt = 0; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 449 | } |
| 450 | |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 451 | mdp_select_pipe_client_id(pinfo, |
| 452 | &left_sspp_client_id, &right_sspp_client_id); |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 453 | |
| 454 | /* Each pipe driving half the screen */ |
| 455 | if (pinfo->lcdc.dual_pipe) |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 456 | xres = pinfo->lm_split[0]; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 457 | |
| 458 | /* bpp = bytes per pixel of input image */ |
| 459 | smp_cnt = (xres * bpp * 2) + smp_size - 1; |
| 460 | smp_cnt /= smp_size; |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 461 | |
| 462 | if (smp_cnt > 4) { |
| 463 | dprintf(CRITICAL, "ERROR: %s: Out of SMP's, cnt=%d! \n", __func__, |
| 464 | smp_cnt); |
| 465 | ASSERT(0); /* Max 4 SMPs can be allocated per client */ |
| 466 | } |
| 467 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 468 | writel(smp_cnt * 0x40, left_pipe + REQPRIORITY_FIFO_WATERMARK0); |
| 469 | writel(smp_cnt * 0x80, left_pipe + REQPRIORITY_FIFO_WATERMARK1); |
| 470 | writel(smp_cnt * 0xc0, left_pipe + REQPRIORITY_FIFO_WATERMARK2); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 471 | |
| 472 | if (pinfo->lcdc.dual_pipe) { |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 473 | xres = pinfo->lm_split[1]; |
| 474 | |
| 475 | smp_cnt = (xres * bpp * 2) + smp_size - 1; |
| 476 | smp_cnt /= smp_size; |
| 477 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 478 | writel(smp_cnt * 0x40, right_pipe + REQPRIORITY_FIFO_WATERMARK0); |
| 479 | writel(smp_cnt * 0x80, right_pipe + REQPRIORITY_FIFO_WATERMARK1); |
| 480 | writel(smp_cnt * 0xc0, right_pipe + REQPRIORITY_FIFO_WATERMARK2); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 481 | } |
| 482 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 483 | free_smp_offset = mdss_smp_alloc(left_sspp_client_id, smp_cnt, |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 484 | fixed_smp_cnt, free_smp_offset); |
| 485 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 486 | mdss_smp_alloc(right_sspp_client_id, smp_cnt, fixed_smp_cnt, |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 487 | free_smp_offset); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 488 | } |
| 489 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 490 | static void mdss_intf_tg_setup(struct msm_panel_info *pinfo, uint32_t intf_base) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 491 | { |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 492 | uint32_t hsync_period, vsync_period; |
| 493 | uint32_t hsync_start_x, hsync_end_x; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 494 | uint32_t display_hctl, hsync_ctl, display_vstart, display_vend; |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 495 | uint32_t adjust_xres = 0; |
Dhaval Patel | 55c1217 | 2015-05-04 22:25:22 -0700 | [diff] [blame] | 496 | uint32_t upper = 0, lower = 0; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 497 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 498 | struct lcdc_panel_info *lcdc = NULL; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 499 | struct intf_timing_params itp = {0}; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 500 | |
| 501 | if (pinfo == NULL) |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 502 | return; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 503 | |
| 504 | lcdc = &(pinfo->lcdc); |
| 505 | if (lcdc == NULL) |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 506 | return; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 507 | |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 508 | adjust_xres = pinfo->xres; |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 509 | if (pinfo->lcdc.split_display) { |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 510 | if (pinfo->lcdc.dst_split) { |
| 511 | adjust_xres /= 2; |
| 512 | } else if(pinfo->lcdc.dual_pipe) { |
| 513 | if (intf_base == (MDP_INTF_1_BASE + mdss_mdp_intf_offset())) |
| 514 | adjust_xres = pinfo->lm_split[0]; |
| 515 | else |
| 516 | adjust_xres = pinfo->lm_split[1]; |
| 517 | } |
| 518 | |
Jayant Shekhar | 4e895d0 | 2015-03-30 12:30:14 +0530 | [diff] [blame] | 519 | if (intf_base == (MDP_INTF_1_BASE + mdss_mdp_intf_offset())) { |
Dhaval Patel | 55c1217 | 2015-05-04 22:25:22 -0700 | [diff] [blame] | 520 | if (pinfo->lcdc.pipe_swap) { |
| 521 | lower |= BIT(4); |
| 522 | upper |= BIT(8); |
| 523 | } else { |
| 524 | lower |= BIT(8); |
| 525 | upper |= BIT(4); |
| 526 | } |
| 527 | writel(lower, MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL); |
| 528 | writel(upper, MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 529 | writel(0x1, MDP_REG_SPLIT_DISPLAY_EN); |
| 530 | } |
| 531 | } |
| 532 | |
Ujwal Patel | 5c3227b | 2015-08-12 14:48:02 -0700 | [diff] [blame] | 533 | if (pinfo->lcdc.dst_split && (intf_base == (MDP_INTF_1_BASE + mdss_mdp_intf_offset()))) { |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 534 | uint32_t ppb_offset = mdss_mdp_get_ppb_offset(); |
Ujwal Patel | 5c3227b | 2015-08-12 14:48:02 -0700 | [diff] [blame] | 535 | writel(BIT(5), REG_MDP(ppb_offset)); /* MMSS_MDP_PPB0_CNTL */ |
| 536 | writel(BIT(16) | (0x3 << 20), REG_MDP(ppb_offset + 0x4)); /* MMSS_MDP_PPB0_CONFIG */ |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 537 | } |
| 538 | |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 539 | if (pinfo->compression_mode == COMPRESSION_FBC) |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 540 | if (!pinfo->fbc.enabled || !pinfo->fbc.comp_ratio) |
| 541 | pinfo->fbc.comp_ratio = 1; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 542 | |
| 543 | itp.xres = (adjust_xres / pinfo->fbc.comp_ratio); |
| 544 | itp.yres = pinfo->yres; |
| 545 | itp.width =((adjust_xres + pinfo->lcdc.xres_pad) / pinfo->fbc.comp_ratio); |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 546 | |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 547 | if (pinfo->compression_mode == COMPRESSION_DSC) { |
| 548 | itp.xres = pinfo->dsc.pclk_per_line; |
| 549 | itp.width = pinfo->dsc.pclk_per_line; |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 550 | } |
| 551 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 552 | itp.height = pinfo->yres + pinfo->lcdc.yres_pad; |
| 553 | itp.h_back_porch = pinfo->lcdc.h_back_porch; |
| 554 | itp.h_front_porch = pinfo->lcdc.h_front_porch; |
| 555 | itp.v_back_porch = pinfo->lcdc.v_back_porch; |
| 556 | itp.v_front_porch = pinfo->lcdc.v_front_porch; |
| 557 | itp.hsync_pulse_width = pinfo->lcdc.h_pulse_width; |
| 558 | itp.vsync_pulse_width = pinfo->lcdc.v_pulse_width; |
| 559 | |
| 560 | itp.border_clr = pinfo->lcdc.border_clr; |
| 561 | itp.underflow_clr = pinfo->lcdc.underflow_clr; |
| 562 | itp.hsync_skew = pinfo->lcdc.hsync_skew; |
| 563 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 564 | hsync_period = itp.hsync_pulse_width + itp.h_back_porch + |
| 565 | itp.width + itp.h_front_porch; |
| 566 | |
| 567 | vsync_period = itp.vsync_pulse_width + itp.v_back_porch + |
| 568 | itp.height + itp.v_front_porch; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 569 | |
| 570 | hsync_start_x = |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 571 | itp.hsync_pulse_width + |
| 572 | itp.h_back_porch; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 573 | hsync_end_x = |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 574 | hsync_period - itp.h_front_porch - 1; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 575 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 576 | display_vstart = (itp.vsync_pulse_width + |
| 577 | itp.v_back_porch) |
| 578 | * hsync_period + itp.hsync_skew; |
| 579 | display_vend = ((vsync_period - itp.v_front_porch) * hsync_period) |
| 580 | + itp.hsync_skew - 1; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 581 | |
Jayant Shekhar | 4e895d0 | 2015-03-30 12:30:14 +0530 | [diff] [blame] | 582 | if (intf_base == (MDP_INTF_0_BASE + mdss_mdp_intf_offset())) { /* eDP */ |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 583 | display_vstart += itp.hsync_pulse_width + itp.h_back_porch; |
| 584 | display_vend -= itp.h_front_porch; |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 585 | } |
| 586 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 587 | hsync_ctl = (hsync_period << 16) | itp.hsync_pulse_width; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 588 | display_hctl = (hsync_end_x << 16) | hsync_start_x; |
| 589 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 590 | writel(hsync_ctl, MDP_HSYNC_CTL + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 591 | writel(vsync_period*hsync_period, MDP_VSYNC_PERIOD_F0 + |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 592 | intf_base); |
| 593 | writel(0x00, MDP_VSYNC_PERIOD_F1 + intf_base); |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 594 | writel(itp.vsync_pulse_width*hsync_period, |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 595 | MDP_VSYNC_PULSE_WIDTH_F0 + |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 596 | intf_base); |
| 597 | writel(0x00, MDP_VSYNC_PULSE_WIDTH_F1 + intf_base); |
| 598 | writel(display_hctl, MDP_DISPLAY_HCTL + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 599 | writel(display_vstart, MDP_DISPLAY_V_START_F0 + |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 600 | intf_base); |
| 601 | writel(0x00, MDP_DISPLAY_V_START_F1 + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 602 | writel(display_vend, MDP_DISPLAY_V_END_F0 + |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 603 | intf_base); |
| 604 | writel(0x00, MDP_DISPLAY_V_END_F1 + intf_base); |
| 605 | writel(0x00, MDP_ACTIVE_HCTL + intf_base); |
| 606 | writel(0x00, MDP_ACTIVE_V_START_F0 + intf_base); |
| 607 | writel(0x00, MDP_ACTIVE_V_START_F1 + intf_base); |
| 608 | writel(0x00, MDP_ACTIVE_V_END_F0 + intf_base); |
| 609 | writel(0x00, MDP_ACTIVE_V_END_F1 + intf_base); |
| 610 | writel(0xFF, MDP_UNDERFFLOW_COLOR + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 611 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 612 | if (intf_base == (MDP_INTF_0_BASE + mdss_mdp_intf_offset())) /* eDP */ |
| 613 | writel(0x212A, MDP_PANEL_FORMAT + intf_base); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 614 | else |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 615 | writel(0x213F, MDP_PANEL_FORMAT + intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 616 | } |
| 617 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 618 | static void mdss_intf_fetch_start_config(struct msm_panel_info *pinfo, |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 619 | uint32_t intf_base) |
| 620 | { |
| 621 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 622 | uint32_t v_total, h_total, fetch_start, vfp_start; |
| 623 | uint32_t prefetch_avail, prefetch_needed; |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 624 | uint32_t adjust_xres = 0; |
Huaibin Yang | 617cbb0 | 2015-01-14 14:17:07 -0800 | [diff] [blame] | 625 | uint32_t fetch_enable = BIT(31); |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 626 | |
| 627 | struct lcdc_panel_info *lcdc = NULL; |
| 628 | |
| 629 | if (pinfo == NULL) |
| 630 | return; |
| 631 | |
| 632 | lcdc = &(pinfo->lcdc); |
| 633 | if (lcdc == NULL) |
| 634 | return; |
| 635 | |
| 636 | /* |
| 637 | * MDP programmable fetch is for MDP with rev >= 1.05. |
| 638 | * Programmable fetch is not needed if vertical back porch |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 639 | * plus vertical puls width is >= 25. |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 640 | */ |
| 641 | if (mdp_hw_rev < MDSS_MDP_HW_REV_105 || |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 642 | (lcdc->v_back_porch + lcdc->v_pulse_width) >= |
| 643 | MDSS_MDP_MAX_PREFILL_FETCH) |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 644 | return; |
| 645 | |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 646 | adjust_xres = pinfo->xres; |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 647 | if (pinfo->lcdc.split_display) { |
| 648 | if (pinfo->lcdc.dst_split) { |
| 649 | adjust_xres /= 2; |
| 650 | } else if(pinfo->lcdc.dual_pipe) { |
| 651 | if (intf_base == (MDP_INTF_1_BASE + mdss_mdp_intf_offset())) |
| 652 | adjust_xres = pinfo->lm_split[0]; |
| 653 | else |
| 654 | adjust_xres = pinfo->lm_split[1]; |
| 655 | } |
| 656 | } |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 657 | |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 658 | if (pinfo->compression_mode == COMPRESSION_DSC) { |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 659 | adjust_xres = pinfo->dsc.pclk_per_line; |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 660 | } else if (pinfo->compression_mode == COMPRESSION_FBC) { |
| 661 | if (pinfo->fbc.enabled && pinfo->fbc.comp_ratio) |
| 662 | adjust_xres /= pinfo->fbc.comp_ratio; |
| 663 | } |
Jeevan Shriram | 4466729 | 2015-03-17 17:28:39 -0700 | [diff] [blame] | 664 | |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 665 | /* |
| 666 | * Fetch should always be outside the active lines. If the fetching |
| 667 | * is programmed within active region, hardware behavior is unknown. |
| 668 | */ |
| 669 | v_total = lcdc->v_pulse_width + lcdc->v_back_porch + pinfo->yres + |
| 670 | lcdc->v_front_porch; |
| 671 | h_total = lcdc->h_pulse_width + lcdc->h_back_porch + adjust_xres + |
| 672 | lcdc->h_front_porch; |
| 673 | vfp_start = lcdc->v_pulse_width + lcdc->v_back_porch + pinfo->yres; |
| 674 | |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 675 | prefetch_avail = v_total - vfp_start; |
| 676 | prefetch_needed = MDSS_MDP_MAX_PREFILL_FETCH - |
| 677 | lcdc->v_back_porch - |
| 678 | lcdc->v_pulse_width; |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 679 | |
| 680 | /* |
| 681 | * In some cases, vertical front porch is too high. In such cases limit |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 682 | * the mdp fetch lines as the last (25 - vbp - vpw) lines of vertical front porch. |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 683 | */ |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 684 | if (prefetch_avail > prefetch_needed) |
| 685 | prefetch_avail = prefetch_needed; |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 686 | |
Ingrid Gallardo | 0a6cebb | 2015-02-13 17:18:26 -0800 | [diff] [blame] | 687 | fetch_start = (v_total - prefetch_avail) * h_total + 1; |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 688 | |
Huaibin Yang | 617cbb0 | 2015-01-14 14:17:07 -0800 | [diff] [blame] | 689 | if (pinfo->dfps.panel_dfps.enabled) |
| 690 | fetch_enable |= BIT(23); |
| 691 | |
| 692 | writel_relaxed(fetch_start, MDP_PROG_FETCH_START + intf_base); |
| 693 | writel_relaxed(fetch_enable, MDP_INTF_CONFIG + intf_base); |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 694 | } |
| 695 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 696 | void mdss_layer_mixer_setup(struct fbcon_config *fb, struct msm_panel_info |
| 697 | *pinfo) |
| 698 | { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 699 | uint32_t mdp_rgb_size, height, width; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 700 | uint32_t left_staging_level, right_staging_level; |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 701 | |
Dhaval Patel | 0a9ab81 | 2013-10-25 10:25:06 -0700 | [diff] [blame] | 702 | height = fb->height; |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 703 | width = fb->width; |
| 704 | |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 705 | if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split) |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 706 | width = pinfo->lm_split[0]; |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 707 | |
| 708 | /* write active region size*/ |
| 709 | mdp_rgb_size = (height << 16) | width; |
| 710 | |
| 711 | writel(mdp_rgb_size, MDP_VP_0_MIXER_0_BASE + LAYER_0_OUT_SIZE); |
| 712 | writel(0x00, MDP_VP_0_MIXER_0_BASE + LAYER_0_OP_MODE); |
| 713 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_0_BLEND_OP); |
| 714 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_0_BLEND0_FG_ALPHA); |
| 715 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_1_BLEND_OP); |
| 716 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_1_BLEND0_FG_ALPHA); |
| 717 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_2_BLEND_OP); |
| 718 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_2_BLEND0_FG_ALPHA); |
| 719 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_3_BLEND_OP); |
| 720 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_3_BLEND0_FG_ALPHA); |
| 721 | |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 722 | switch (pinfo->pipe_type) { |
| 723 | case MDSS_MDP_PIPE_TYPE_RGB: |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 724 | left_staging_level = 0x0000200; |
| 725 | right_staging_level = 0x1000; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 726 | break; |
| 727 | case MDSS_MDP_PIPE_TYPE_DMA: |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 728 | left_staging_level = 0x0040000; |
| 729 | right_staging_level = 0x200000; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 730 | break; |
| 731 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 732 | default: |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 733 | left_staging_level = 0x1; |
| 734 | right_staging_level = 0x8; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 735 | break; |
| 736 | } |
| 737 | |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 738 | /* |
| 739 | * When ping-pong split is enabled and two pipes are used, |
| 740 | * both the pipes need to be staged on the same layer mixer. |
| 741 | */ |
| 742 | if (pinfo->lcdc.dual_pipe && pinfo->lcdc.dst_split) |
| 743 | left_staging_level |= right_staging_level; |
| 744 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 745 | /* Base layer for layer mixer 0 */ |
| 746 | writel(left_staging_level, MDP_CTL_0_BASE + CTL_LAYER_0); |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 747 | |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 748 | if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split) { |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 749 | /* write active region size*/ |
| 750 | mdp_rgb_size = (height << 16) | pinfo->lm_split[1]; |
| 751 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 752 | writel(mdp_rgb_size, MDP_VP_0_MIXER_1_BASE + LAYER_0_OUT_SIZE); |
| 753 | writel(0x00, MDP_VP_0_MIXER_1_BASE + LAYER_0_OP_MODE); |
| 754 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_0_BLEND_OP); |
| 755 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_0_BLEND0_FG_ALPHA); |
| 756 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_1_BLEND_OP); |
| 757 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_1_BLEND0_FG_ALPHA); |
| 758 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_2_BLEND_OP); |
| 759 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_2_BLEND0_FG_ALPHA); |
| 760 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND_OP); |
| 761 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND0_FG_ALPHA); |
| 762 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 763 | /* Base layer for layer mixer 1 */ |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 764 | if (pinfo->lcdc.split_display) |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 765 | writel(right_staging_level, MDP_CTL_1_BASE + CTL_LAYER_1); |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 766 | else |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 767 | writel(right_staging_level, MDP_CTL_0_BASE + CTL_LAYER_1); |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 768 | } |
| 769 | } |
| 770 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 771 | void mdss_fbc_cfg(struct msm_panel_info *pinfo) |
| 772 | { |
| 773 | uint32_t mode = 0; |
| 774 | uint32_t budget_ctl = 0; |
| 775 | uint32_t lossy_mode = 0; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 776 | struct fbc_panel_info *fbc; |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 777 | uint32_t enc_mode, width; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 778 | |
| 779 | fbc = &pinfo->fbc; |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 780 | |
| 781 | if (!pinfo->fbc.enabled) |
| 782 | return; |
| 783 | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 784 | /* enc_mode defines FBC version. 0 = FBC 1.0 and 1 = FBC 2.0 */ |
| 785 | enc_mode = (fbc->comp_ratio == 2) ? 0 : 1; |
| 786 | |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 787 | width = pinfo->xres; |
| 788 | if (enc_mode) |
| 789 | width = (pinfo->xres/fbc->comp_ratio); |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 790 | |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 791 | if (pinfo->mipi.dual_dsi) |
| 792 | width /= 2; |
| 793 | |
| 794 | mode = ((width) << 16) | ((fbc->slice_height) << 11) | |
| 795 | ((fbc->pred_mode) << 10) | (enc_mode) << 9 | |
| 796 | ((fbc->comp_mode) << 8) | ((fbc->qerr_enable) << 7) | |
| 797 | ((fbc->cd_bias) << 4) | ((fbc->pat_enable) << 3) | |
| 798 | ((fbc->vlc_enable) << 2) | ((fbc->bflc_enable) << 1) | 1; |
| 799 | |
| 800 | dprintf(SPEW, "width = %d, slice height = %d, pred_mode =%d, enc_mode = %d, \ |
| 801 | comp_mode %d, qerr_enable = %d, cd_bias = %d\n", |
| 802 | width, fbc->slice_height, fbc->pred_mode, enc_mode, |
| 803 | fbc->comp_mode, fbc->qerr_enable, fbc->cd_bias); |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 804 | dprintf(SPEW, "pat_enable %d, vlc_enable = %d, bflc_enable = %d\n", |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 805 | fbc->pat_enable, fbc->vlc_enable, fbc->bflc_enable); |
| 806 | |
| 807 | budget_ctl = ((fbc->line_x_budget) << 12) | |
| 808 | ((fbc->block_x_budget) << 8) | fbc->block_budget; |
| 809 | |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 810 | lossy_mode = (((fbc->max_pred_err) << 28) | (fbc->lossless_mode_thd) << 16) | |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 811 | ((fbc->lossy_mode_thd) << 8) | |
| 812 | ((fbc->lossy_rgb_thd) << 4) | fbc->lossy_mode_idx; |
| 813 | |
Jeevan Shriram | 1b07e37 | 2014-11-30 22:03:50 -0800 | [diff] [blame] | 814 | dprintf(SPEW, "mode= 0x%x, budget_ctl = 0x%x, lossy_mode= 0x%x\n", |
| 815 | mode, budget_ctl, lossy_mode); |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 816 | writel(mode, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_MODE); |
| 817 | writel(budget_ctl, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_BUDGET_CTL); |
| 818 | writel(lossy_mode, MDP_PP_0_BASE + MDSS_MDP_REG_PP_FBC_LOSSY_MODE); |
| 819 | |
| 820 | if (pinfo->mipi.dual_dsi) { |
| 821 | writel(mode, MDP_PP_1_BASE + MDSS_MDP_REG_PP_FBC_MODE); |
| 822 | writel(budget_ctl, MDP_PP_1_BASE + |
| 823 | MDSS_MDP_REG_PP_FBC_BUDGET_CTL); |
| 824 | writel(lossy_mode, MDP_PP_1_BASE + |
| 825 | MDSS_MDP_REG_PP_FBC_LOSSY_MODE); |
| 826 | } |
| 827 | } |
| 828 | |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 829 | void mdss_qos_remapper_setup(void) |
| 830 | { |
| 831 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
| 832 | uint32_t map; |
| 833 | |
| 834 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_100) || |
| 835 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 836 | MDSS_MDP_HW_REV_102)) |
| 837 | map = 0xE9; |
| 838 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 839 | MDSS_MDP_HW_REV_101)) |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 840 | map = 0xA5; |
| 841 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | 3908d17 | 2014-06-04 18:00:56 +0530 | [diff] [blame] | 842 | MDSS_MDP_HW_REV_106) || |
| 843 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | fdb5683 | 2015-04-09 21:08:28 -0700 | [diff] [blame] | 844 | MDSS_MDP_HW_REV_108) || |
| 845 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | f912cfb | 2015-06-08 16:36:58 +0530 | [diff] [blame] | 846 | MDSS_MDP_HW_REV_111) || |
| 847 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | fdb5683 | 2015-04-09 21:08:28 -0700 | [diff] [blame] | 848 | MDSS_MDP_HW_REV_112)) |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 849 | map = 0xE4; |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 850 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Chandan Uddaraju | 18a5037 | 2014-10-01 18:45:30 -0700 | [diff] [blame] | 851 | MDSS_MDP_HW_REV_105) || |
| 852 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Jeevan Shriram | 47c936d | 2014-12-19 11:50:13 -0800 | [diff] [blame] | 853 | MDSS_MDP_HW_REV_109) || |
| 854 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Dhaval Patel | 4401467 | 2015-03-26 10:58:32 -0700 | [diff] [blame] | 855 | MDSS_MDP_HW_REV_107) || |
| 856 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Jeevan Shriram | 47c936d | 2014-12-19 11:50:13 -0800 | [diff] [blame] | 857 | MDSS_MDP_HW_REV_110)) |
Ingrid Gallardo | 998ea44 | 2014-09-10 17:22:08 -0700 | [diff] [blame] | 858 | map = 0xA4; |
| 859 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 860 | MDSS_MDP_HW_REV_103)) |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 861 | map = 0xFA; |
| 862 | else |
| 863 | return; |
| 864 | |
| 865 | writel(map, MDP_QOS_REMAPPER_CLASS_0); |
| 866 | } |
| 867 | |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 868 | void mdss_vbif_qos_remapper_setup(struct msm_panel_info *pinfo) |
| 869 | { |
| 870 | uint32_t mask, reg_val, i; |
| 871 | uint32_t left_pipe_xin_id, right_pipe_xin_id; |
| 872 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
| 873 | uint32_t vbif_qos[4] = {0, 0, 0, 0}; |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 874 | uint32_t vbif_offset; |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 875 | |
| 876 | mdp_select_pipe_xin_id(pinfo, |
| 877 | &left_pipe_xin_id, &right_pipe_xin_id); |
| 878 | |
| 879 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_106) || |
Padmanabhan Komanduru | fdb5683 | 2015-04-09 21:08:28 -0700 | [diff] [blame] | 880 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_108) || |
Padmanabhan Komanduru | f912cfb | 2015-06-08 16:36:58 +0530 | [diff] [blame] | 881 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_111) || |
Padmanabhan Komanduru | fdb5683 | 2015-04-09 21:08:28 -0700 | [diff] [blame] | 882 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_112)) { |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 883 | vbif_qos[0] = 2; |
| 884 | vbif_qos[1] = 2; |
| 885 | vbif_qos[2] = 2; |
| 886 | vbif_qos[3] = 2; |
Chandan Uddaraju | 18a5037 | 2014-10-01 18:45:30 -0700 | [diff] [blame] | 887 | } else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_105) || |
Jeevan Shriram | 47c936d | 2014-12-19 11:50:13 -0800 | [diff] [blame] | 888 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_109) || |
Dhaval Patel | 4401467 | 2015-03-26 10:58:32 -0700 | [diff] [blame] | 889 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_107) || |
Jeevan Shriram | 47c936d | 2014-12-19 11:50:13 -0800 | [diff] [blame] | 890 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_110)) { |
Ingrid Gallardo | 998ea44 | 2014-09-10 17:22:08 -0700 | [diff] [blame] | 891 | vbif_qos[0] = 1; |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 892 | vbif_qos[1] = 2; |
| 893 | vbif_qos[2] = 2; |
Ingrid Gallardo | 998ea44 | 2014-09-10 17:22:08 -0700 | [diff] [blame] | 894 | vbif_qos[3] = 2; |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 895 | } else { |
| 896 | return; |
| 897 | } |
| 898 | |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 899 | vbif_offset = mdss_mdp_vbif_qos_remap_get_offset(); |
| 900 | |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 901 | for (i = 0; i < 4; i++) { |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 902 | /* VBIF_VBIF_QOS_REMAP_00 */ |
| 903 | reg_val = readl(REG_MDP(vbif_offset) + i*4); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 904 | mask = 0x3 << (left_pipe_xin_id * 2); |
| 905 | reg_val &= ~(mask); |
| 906 | reg_val |= vbif_qos[i] << (left_pipe_xin_id * 2); |
| 907 | |
| 908 | if (pinfo->lcdc.dual_pipe) { |
| 909 | mask = 0x3 << (right_pipe_xin_id * 2); |
| 910 | reg_val &= ~(mask); |
| 911 | reg_val |= vbif_qos[i] << (right_pipe_xin_id * 2); |
| 912 | } |
Jeevan Shriram | d8f99a3 | 2015-01-07 19:07:05 -0800 | [diff] [blame] | 913 | writel(reg_val, REG_MDP(vbif_offset) + i*4); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 914 | } |
| 915 | } |
| 916 | |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 917 | static uint32_t mdss_mdp_ctl_out_sel(struct msm_panel_info *pinfo, |
| 918 | int is_main_ctl) |
| 919 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 920 | uint32_t mctl_intf_sel; |
| 921 | uint32_t sctl_intf_sel; |
| 922 | |
| 923 | if ((pinfo->dest == DISPLAY_2) || |
| 924 | ((pinfo->dest = DISPLAY_1) && (pinfo->lcdc.pipe_swap))) { |
| 925 | mctl_intf_sel = BIT(4) | BIT(5); /* Interface 2 */ |
| 926 | sctl_intf_sel = BIT(5); /* Interface 1 */ |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 927 | } else { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 928 | mctl_intf_sel = BIT(5); /* Interface 1 */ |
| 929 | sctl_intf_sel = BIT(4) | BIT(5); /* Interface 2 */ |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 930 | } |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 931 | dprintf(SPEW, "%s: main ctl dest=%s sec ctl dest=%s\n", __func__, |
| 932 | (mctl_intf_sel & BIT(4)) ? "Intf2" : "Intf1", |
| 933 | (sctl_intf_sel & BIT(4)) ? "Intf2" : "Intf1"); |
| 934 | return is_main_ctl ? mctl_intf_sel : sctl_intf_sel; |
| 935 | } |
| 936 | |
| 937 | static void mdp_set_intf_base(struct msm_panel_info *pinfo, |
| 938 | uint32_t *intf_sel, uint32_t *sintf_sel, |
| 939 | uint32_t *intf_base, uint32_t *sintf_base) |
| 940 | { |
| 941 | if (pinfo->dest == DISPLAY_2) { |
| 942 | *intf_sel = BIT(16); |
| 943 | *sintf_sel = BIT(8); |
| 944 | *intf_base = MDP_INTF_2_BASE + mdss_mdp_intf_offset(); |
| 945 | *sintf_base = MDP_INTF_1_BASE + mdss_mdp_intf_offset(); |
| 946 | } else { |
| 947 | *intf_sel = BIT(8); |
| 948 | *sintf_sel = BIT(16); |
| 949 | *intf_base = MDP_INTF_1_BASE + mdss_mdp_intf_offset(); |
| 950 | *sintf_base = MDP_INTF_2_BASE + mdss_mdp_intf_offset(); |
| 951 | } |
| 952 | dprintf(SPEW, "%s: main intf=%s, sec intf=%s\n", __func__, |
| 953 | (pinfo->dest == DISPLAY_2) ? "Intf2" : "Intf1", |
| 954 | (pinfo->dest == DISPLAY_2) ? "Intf1" : "Intf2"); |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 955 | } |
| 956 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 957 | int mdp_dsi_video_config(struct msm_panel_info *pinfo, |
| 958 | struct fbcon_config *fb) |
| 959 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 960 | uint32_t intf_sel, sintf_sel; |
| 961 | uint32_t intf_base, sintf_base; |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 962 | uint32_t left_pipe, right_pipe; |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 963 | uint32_t reg; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 964 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 965 | mdp_set_intf_base(pinfo, &intf_sel, &sintf_sel, &intf_base, &sintf_base); |
| 966 | |
| 967 | mdss_intf_tg_setup(pinfo, intf_base); |
| 968 | mdss_intf_fetch_start_config(pinfo, intf_base); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 969 | |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 970 | if (pinfo->mipi.dual_dsi) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 971 | mdss_intf_tg_setup(pinfo, sintf_base); |
| 972 | mdss_intf_fetch_start_config(pinfo, sintf_base); |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 973 | } |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 974 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 975 | mdp_clk_gating_ctrl(); |
| 976 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 977 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 978 | mdss_vbif_setup(); |
Dhaval Patel | 4401467 | 2015-03-26 10:58:32 -0700 | [diff] [blame] | 979 | if (!has_fixed_size_smp()) |
| 980 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
Siddhartha Agrawal | b1b5a1f | 2013-04-17 19:53:41 -0700 | [diff] [blame] | 981 | |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 982 | mdss_qos_remapper_setup(); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 983 | mdss_vbif_qos_remapper_setup(pinfo); |
Siddhartha Agrawal | b1b5a1f | 2013-04-17 19:53:41 -0700 | [diff] [blame] | 984 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 985 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
| 986 | |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 987 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 988 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 989 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 990 | mdss_layer_mixer_setup(fb, pinfo); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 991 | |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 992 | reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo, 1); |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 993 | |
| 994 | /* enable 3D mux for dual_pipe but single interface config */ |
| 995 | if (pinfo->lcdc.dual_pipe && !pinfo->mipi.dual_dsi && |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 996 | !pinfo->lcdc.split_display) { |
| 997 | |
| 998 | if (pinfo->num_dsc_enc != 2) |
| 999 | reg |= BIT(19) | BIT(20); |
| 1000 | } |
Ujwal Patel | 190369c | 2014-11-06 14:18:55 -0800 | [diff] [blame] | 1001 | |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 1002 | writel(reg, MDP_CTL_0_BASE + CTL_TOP); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1003 | |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 1004 | if ((pinfo->compression_mode == COMPRESSION_DSC) && |
| 1005 | pinfo->dsc.mdp_dsc_config) { |
| 1006 | struct dsc_desc *dsc = &pinfo->dsc; |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 1007 | |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 1008 | if (pinfo->lcdc.dual_pipe && !pinfo->mipi.dual_dsi && |
| 1009 | !pinfo->lcdc.split_display && (pinfo->num_dsc_enc == 2)) { |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 1010 | |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 1011 | dsc->mdp_dsc_config(pinfo, MDP_PP_0_BASE, |
| 1012 | MDP_DSC_0_BASE, true, true); |
| 1013 | dsc->mdp_dsc_config(pinfo, MDP_PP_1_BASE, |
| 1014 | MDP_DSC_1_BASE, true, true); |
| 1015 | } else { |
| 1016 | dsc->mdp_dsc_config(pinfo, MDP_PP_0_BASE, |
| 1017 | MDP_DSC_0_BASE, false, false); |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 1018 | } |
| 1019 | } else if (pinfo->compression_mode == COMPRESSION_FBC) { |
| 1020 | if (pinfo->fbc.enabled) |
| 1021 | mdss_fbc_cfg(pinfo); |
| 1022 | } |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 1023 | |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 1024 | /* |
| 1025 | * if dst_split is enabled, intf 1 & 2 needs to be enabled but |
| 1026 | * CTL_1 path should not be set since CTL_0 itself is going |
| 1027 | * to split after DSPP block and drive both intf. |
| 1028 | */ |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 1029 | if (pinfo->mipi.dual_dsi) { |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 1030 | if (!pinfo->lcdc.dst_split) { |
| 1031 | reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo,0); |
| 1032 | writel(reg, MDP_CTL_1_BASE + CTL_TOP); |
| 1033 | } |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1034 | intf_sel |= sintf_sel; /* INTF 2 enable */ |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 1035 | } |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 1036 | |
| 1037 | writel(intf_sel, MDP_DISP_INTF_SEL); |
| 1038 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1039 | writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); |
| 1040 | writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); |
| 1041 | writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); |
| 1042 | |
| 1043 | return 0; |
| 1044 | } |
| 1045 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1046 | int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb) |
| 1047 | { |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1048 | uint32_t left_pipe, right_pipe; |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1049 | |
| 1050 | mdss_intf_tg_setup(pinfo, MDP_INTF_0_BASE); |
| 1051 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 1052 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1053 | mdp_clk_gating_ctrl(); |
| 1054 | |
| 1055 | mdss_vbif_setup(); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1056 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1057 | |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 1058 | mdss_qos_remapper_setup(); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 1059 | mdss_vbif_qos_remapper_setup(pinfo); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1060 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1061 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 1062 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1063 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1064 | |
| 1065 | mdss_layer_mixer_setup(fb, pinfo); |
| 1066 | |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 1067 | if (pinfo->lcdc.dual_pipe) |
| 1068 | writel(0x181F10, MDP_CTL_0_BASE + CTL_TOP); |
| 1069 | else |
| 1070 | writel(0x1F10, MDP_CTL_0_BASE + CTL_TOP); |
| 1071 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1072 | writel(0x9, MDP_DISP_INTF_SEL); |
| 1073 | writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); |
| 1074 | writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); |
| 1075 | writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); |
| 1076 | |
| 1077 | return 0; |
| 1078 | } |
| 1079 | |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 1080 | int mdss_hdmi_config(struct msm_panel_info *pinfo, struct fbcon_config *fb) |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 1081 | { |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 1082 | uint32_t left_pipe, right_pipe; |
Casey Piper | 77f69c5 | 2015-03-20 15:55:12 -0700 | [diff] [blame] | 1083 | dprintf(SPEW, "ENTER: %s\n", __func__); |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 1084 | |
Casey Piper | 77f69c5 | 2015-03-20 15:55:12 -0700 | [diff] [blame] | 1085 | mdss_intf_tg_setup(pinfo, MDP_INTF_3_BASE + mdss_mdp_intf_offset()); |
| 1086 | pinfo->pipe_type = MDSS_MDP_PIPE_TYPE_RGB; |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 1087 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
| 1088 | |
| 1089 | mdp_clk_gating_ctrl(); |
| 1090 | mdss_vbif_setup(); |
| 1091 | |
| 1092 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
| 1093 | |
| 1094 | mdss_qos_remapper_setup(); |
| 1095 | |
| 1096 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
| 1097 | if (pinfo->lcdc.dual_pipe) |
| 1098 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
| 1099 | |
| 1100 | mdss_layer_mixer_setup(fb, pinfo); |
| 1101 | |
| 1102 | if (pinfo->lcdc.dual_pipe) |
| 1103 | writel(0x181F40, MDP_CTL_0_BASE + CTL_TOP); |
| 1104 | else |
| 1105 | writel(0x40, MDP_CTL_0_BASE + CTL_TOP); |
| 1106 | |
| 1107 | writel(BIT(24) | BIT(25), MDP_DISP_INTF_SEL); |
| 1108 | writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); |
| 1109 | writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); |
| 1110 | writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); |
| 1111 | |
| 1112 | return 0; |
| 1113 | } |
| 1114 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1115 | int mdp_dsi_cmd_config(struct msm_panel_info *pinfo, |
| 1116 | struct fbcon_config *fb) |
| 1117 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1118 | uint32_t intf_sel, sintf_sel; |
| 1119 | uint32_t intf_base, sintf_base; |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 1120 | uint32_t reg; |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1121 | int ret = NO_ERROR; |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1122 | uint32_t left_pipe, right_pipe; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1123 | |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1124 | struct lcdc_panel_info *lcdc = NULL; |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1125 | |
| 1126 | if (pinfo == NULL) |
| 1127 | return ERR_INVALID_ARGS; |
| 1128 | |
| 1129 | lcdc = &(pinfo->lcdc); |
| 1130 | if (lcdc == NULL) |
| 1131 | return ERR_INVALID_ARGS; |
| 1132 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1133 | mdp_set_intf_base(pinfo, &intf_sel, &sintf_sel, &intf_base, &sintf_base); |
| 1134 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1135 | if (pinfo->lcdc.split_display) { |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 1136 | reg = BIT(1); /* Command mode */ |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 1137 | if (pinfo->lcdc.dst_split) |
| 1138 | reg |= BIT(2); /* Enable SMART_PANEL_FREE_RUN mode */ |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 1139 | if (pinfo->lcdc.pipe_swap) |
| 1140 | reg |= BIT(4); /* Use intf2 as trigger */ |
| 1141 | else |
| 1142 | reg |= BIT(8); /* Use intf1 as trigger */ |
| 1143 | writel(reg, MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL); |
| 1144 | writel(reg, MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL); |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1145 | writel(0x1, MDP_REG_SPLIT_DISPLAY_EN); |
| 1146 | } |
| 1147 | |
Padmanabhan Komanduru | 4677a12 | 2014-09-26 16:55:05 +0530 | [diff] [blame] | 1148 | if (pinfo->lcdc.dst_split) { |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 1149 | uint32_t ppb_offset = mdss_mdp_get_ppb_offset(); |
Ujwal Patel | 5c3227b | 2015-08-12 14:48:02 -0700 | [diff] [blame] | 1150 | writel(BIT(5), REG_MDP(ppb_offset)); /* MMSS_MDP_PPB0_CNTL */ |
| 1151 | writel(BIT(16) | (0x3 << 20), REG_MDP(ppb_offset + 0x4)); /* MMSS_MDP_PPB0_CONFIG */ |
Padmanabhan Komanduru | 4677a12 | 2014-09-26 16:55:05 +0530 | [diff] [blame] | 1152 | } |
| 1153 | |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1154 | mdp_clk_gating_ctrl(); |
| 1155 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1156 | if (pinfo->mipi.dual_dsi) |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1157 | intf_sel |= sintf_sel; /* INTF 2 enable */ |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1158 | |
| 1159 | writel(intf_sel, MDP_DISP_INTF_SEL); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1160 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 1161 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 1162 | mdss_vbif_setup(); |
Padmanabhan Komanduru | f1d58a3 | 2015-11-13 19:02:22 +0530 | [diff] [blame^] | 1163 | if (!has_fixed_size_smp()) |
| 1164 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 1165 | mdss_qos_remapper_setup(); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 1166 | mdss_vbif_qos_remapper_setup(pinfo); |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 1167 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1168 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
| 1169 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1170 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1171 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1172 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 1173 | mdss_layer_mixer_setup(fb, pinfo); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1174 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1175 | writel(0x213F, MDP_PANEL_FORMAT + intf_base); |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 1176 | reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 1); |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 1177 | |
| 1178 | /* enable 3D mux for dual_pipe but single interface config */ |
| 1179 | if (pinfo->lcdc.dual_pipe && !pinfo->mipi.dual_dsi && |
| 1180 | !pinfo->lcdc.split_display) { |
| 1181 | |
| 1182 | if (pinfo->num_dsc_enc != 2) |
| 1183 | reg |= BIT(19) | BIT(20); |
| 1184 | } |
| 1185 | |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 1186 | writel(reg, MDP_CTL_0_BASE + CTL_TOP); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1187 | |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 1188 | if ((pinfo->compression_mode == COMPRESSION_DSC) && |
| 1189 | pinfo->dsc.mdp_dsc_config) { |
| 1190 | struct dsc_desc *dsc = &pinfo->dsc; |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 1191 | |
Ujwal Patel | 41a665a | 2015-07-17 13:51:30 -0700 | [diff] [blame] | 1192 | if (pinfo->lcdc.dual_pipe && !pinfo->mipi.dual_dsi && |
| 1193 | !pinfo->lcdc.split_display && (pinfo->num_dsc_enc == 2)) { |
| 1194 | |
| 1195 | dsc->mdp_dsc_config(pinfo, MDP_PP_0_BASE, |
| 1196 | MDP_DSC_0_BASE, true, true); |
| 1197 | dsc->mdp_dsc_config(pinfo, MDP_PP_1_BASE, |
| 1198 | MDP_DSC_1_BASE, true, true); |
| 1199 | } else { |
| 1200 | dsc->mdp_dsc_config(pinfo, MDP_PP_0_BASE, |
| 1201 | MDP_DSC_0_BASE, false, false); |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 1202 | } |
| 1203 | } else if (pinfo->compression_mode == COMPRESSION_FBC) { |
| 1204 | if (pinfo->fbc.enabled) |
| 1205 | mdss_fbc_cfg(pinfo); |
| 1206 | } |
Siddhartha Agrawal | fe64dcb | 2014-10-07 12:41:01 -0700 | [diff] [blame] | 1207 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1208 | if (pinfo->mipi.dual_dsi) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1209 | writel(0x213F, sintf_base + MDP_PANEL_FORMAT); |
Padmanabhan Komanduru | 4677a12 | 2014-09-26 16:55:05 +0530 | [diff] [blame] | 1210 | if (!pinfo->lcdc.dst_split) { |
| 1211 | reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 0); |
| 1212 | writel(reg, MDP_CTL_1_BASE + CTL_TOP); |
| 1213 | } |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 1214 | } |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1215 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1216 | return ret; |
| 1217 | } |
| 1218 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1219 | int mdp_dsi_video_on(struct msm_panel_info *pinfo) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1220 | { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1221 | uint32_t ctl0_reg_val, ctl1_reg_val; |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1222 | uint32_t timing_engine_en; |
| 1223 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 1224 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1225 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 1226 | if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split) |
| 1227 | writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1228 | |
| 1229 | if (pinfo->dest == DISPLAY_1) |
| 1230 | timing_engine_en = MDP_INTF_1_TIMING_ENGINE_EN; |
| 1231 | else |
| 1232 | timing_engine_en = MDP_INTF_2_TIMING_ENGINE_EN; |
| 1233 | writel(0x01, timing_engine_en + mdss_mdp_intf_offset()); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1234 | |
| 1235 | return NO_ERROR; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1236 | } |
| 1237 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1238 | int mdp_dsi_video_off(struct msm_panel_info *pinfo) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1239 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1240 | uint32_t timing_engine_en; |
| 1241 | |
| 1242 | if (pinfo->dest == DISPLAY_1) |
| 1243 | timing_engine_en = MDP_INTF_1_TIMING_ENGINE_EN; |
| 1244 | else |
| 1245 | timing_engine_en = MDP_INTF_2_TIMING_ENGINE_EN; |
| 1246 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1247 | if(!target_cont_splash_screen()) |
| 1248 | { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 1249 | writel(0x00000000, timing_engine_en + mdss_mdp_intf_offset()); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1250 | mdelay(60); |
| 1251 | /* Ping-Pong done Tear Check Read/Write */ |
| 1252 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 1253 | writel(0xFF777713, MDP_INTR_CLEAR); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1254 | } |
| 1255 | |
Siddhartha Agrawal | 6a59822 | 2013-02-17 18:33:27 -0800 | [diff] [blame] | 1256 | writel(0x00000000, MDP_INTR_EN); |
| 1257 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1258 | return NO_ERROR; |
| 1259 | } |
| 1260 | |
| 1261 | int mdp_dsi_cmd_off() |
| 1262 | { |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 1263 | if(!target_cont_splash_screen()) |
| 1264 | { |
| 1265 | /* Ping-Pong done Tear Check Read/Write */ |
| 1266 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 1267 | writel(0xFF777713, MDP_INTR_CLEAR); |
| 1268 | } |
| 1269 | writel(0x00000000, MDP_INTR_EN); |
| 1270 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1271 | return NO_ERROR; |
| 1272 | } |
| 1273 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1274 | int mdp_dma_on(struct msm_panel_info *pinfo) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1275 | { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1276 | uint32_t ctl0_reg_val, ctl1_reg_val; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 1277 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1278 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
Jeevan Shriram | d9c1265 | 2015-01-07 19:09:14 -0800 | [diff] [blame] | 1279 | if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split) |
| 1280 | writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH); |
| 1281 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 1282 | writel(0x01, MDP_CTL_0_BASE + CTL_START); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 1283 | return NO_ERROR; |
| 1284 | } |
| 1285 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 1286 | int mdp_edp_on(struct msm_panel_info *pinfo) |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1287 | { |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 1288 | uint32_t ctl0_reg_val, ctl1_reg_val; |
| 1289 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 1290 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1291 | writel(0x01, MDP_INTF_0_TIMING_ENGINE_EN + mdss_mdp_intf_offset()); |
| 1292 | return NO_ERROR; |
| 1293 | } |
| 1294 | |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 1295 | int mdss_hdmi_on(struct msm_panel_info *pinfo) |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 1296 | { |
| 1297 | uint32_t ctl0_reg_val, ctl1_reg_val; |
| 1298 | |
| 1299 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
| 1300 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
| 1301 | |
| 1302 | writel(0x01, MDP_INTF_3_TIMING_ENGINE_EN + mdss_mdp_intf_offset()); |
| 1303 | |
| 1304 | return NO_ERROR; |
| 1305 | } |
| 1306 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1307 | int mdp_edp_off(void) |
| 1308 | { |
| 1309 | if (!target_cont_splash_screen()) { |
| 1310 | |
| 1311 | writel(0x00000000, MDP_INTF_0_TIMING_ENGINE_EN + |
| 1312 | mdss_mdp_intf_offset()); |
| 1313 | mdelay(60); |
| 1314 | /* Ping-Pong done Tear Check Read/Write */ |
| 1315 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 1316 | writel(0xFF777713, MDP_INTR_CLEAR); |
| 1317 | writel(0x00000000, MDP_INTR_EN); |
| 1318 | } |
| 1319 | |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 1320 | writel(0x00000000, MDP_INTR_EN); |
| 1321 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 1322 | return NO_ERROR; |
| 1323 | } |