Travis Geiselbrecht | 6ec9c27 | 2008-09-06 01:34:37 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2008 Travis Geiselbrecht |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining |
| 5 | * a copy of this software and associated documentation files |
| 6 | * (the "Software"), to deal in the Software without restriction, |
| 7 | * including without limitation the rights to use, copy, modify, merge, |
| 8 | * publish, distribute, sublicense, and/or sell copies of the Software, |
| 9 | * and to permit persons to whom the Software is furnished to do so, |
| 10 | * subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice shall be |
| 13 | * included in all copies or substantial portions of the Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 16 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 17 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| 18 | * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY |
| 19 | * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 20 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 21 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 22 | */ |
| 23 | #ifndef __TWL4030_HW_H |
| 24 | #define __TWL4030_HW_H |
| 25 | |
| 26 | /* TWL i2c addresses */ |
| 27 | #define TWL_I2C_ADDR0 0x48 |
| 28 | #define TWL_I2C_ADDR1 0x49 |
| 29 | #define TWL_I2C_ADDR2 0x4a |
| 30 | #define TWL_I2C_ADDR3 0x4b |
| 31 | |
| 32 | #define TWL_USB_ADDR TWL_I2C_ADDR0 |
| 33 | #define TWL_INTBR_ADDR TWL_I2C_ADDR1 |
| 34 | #define TWL_PM_RECEIVER_ADDR TWL_I2C_ADDR3 |
| 35 | |
| 36 | /* TWL registers */ |
| 37 | #define PROTECT_KEY 0x44 |
| 38 | #define VAUX1_DEV_GRP 0x72 |
| 39 | #define VAUX1_TYPE 0x73 |
| 40 | #define VAUX1_REMAP 0x74 |
| 41 | #define VAUX1_DEDICATED 0x75 |
| 42 | #define VAUX2_DEV_GRP 0x76 |
| 43 | #define VAUX2_TYPE 0x77 |
| 44 | #define VAUX2_REMAP 0x78 |
| 45 | #define VAUX2_DEDICATED 0x79 |
| 46 | #define VAUX3_DEV_GRP 0x7a |
| 47 | #define VAUX3_TYPE 0x7b |
| 48 | #define VAUX3_REMAP 0x7c |
| 49 | #define VAUX3_DEDICATED 0x7d |
| 50 | #define VAUX4_DEV_GRP 0x7e |
| 51 | #define VAUX4_TYPE 0x7f |
| 52 | #define VAUX4_REMAP 0x80 |
| 53 | #define VAUX4_DEDICATED 0x81 |
| 54 | #define VMMC1_DEV_GRP 0x82 |
| 55 | #define VMMC1_TYPE 0x83 |
| 56 | #define VMMC1_REMAP 0x84 |
| 57 | #define VMMC1_DEDICATED 0x85 |
| 58 | #define VMMC2_DEV_GRP 0x86 |
| 59 | #define VMMC2_TYPE 0x87 |
| 60 | #define VMMC2_REMAP 0x88 |
| 61 | #define VMMC2_DEDICATED 0x89 |
| 62 | #define VPLL1_DEV_GRP 0x8a |
| 63 | #define VPLL1_TYPE 0x8b |
| 64 | #define VPLL1_REMAP 0x8c |
| 65 | #define VPLL1_DEDICATED 0x8d |
| 66 | #define VPLL2_DEV_GRP 0x8e |
| 67 | #define VPLL2_TYPE 0x8f |
| 68 | #define VPLL2_REMAP 0x90 |
| 69 | #define VPLL2_DEDICATED 0x91 |
| 70 | #define VDAC_DEV_GRP 0x96 |
| 71 | #define VDAC_DEDICATED 0x99 |
| 72 | #define VDD2_DEV_GRP 0xBE |
| 73 | #define VDD2_TYPE 0xBF |
| 74 | #define VDD2_REMAP 0xC0 |
| 75 | #define VDD2_CFG 0xC1 |
| 76 | #define VSIM_DEV_GRP 0x92 |
| 77 | #define VSIM_TYPE 0x93 |
| 78 | #define VSIM_REMAP 0x94 |
| 79 | #define VSIM_DEDICATED 0x95 |
| 80 | #define PMBR1 0x92 |
| 81 | |
| 82 | #define SECONDS_REG 0x1C |
| 83 | #define MINUTES_REG 0x1D |
| 84 | #define ALARM_SECONDS_REG 0x23 |
| 85 | #define ALARM_MINUTES_REG 0x24 |
| 86 | #define ALARM_HOURS_REG 0x25 |
| 87 | |
| 88 | #define RTC_STATUS_REG 0x2A |
| 89 | #define RTC_INTERRUPTS_REG 0x2B |
| 90 | |
| 91 | #define PWR_ISR1 0x2E |
| 92 | #define PWR_IMR1 0x2F |
| 93 | #define PWR_ISR2 0x30 |
| 94 | #define PWR_IMR2 0x31 |
| 95 | #define PWR_EDR1 0x33 |
| 96 | |
| 97 | #define CFG_PWRANA2 0x3F |
| 98 | #define RTC_INTERRUPTS_REG 0x2B |
| 99 | #define STS_HW_CONDITIONS 0x45 |
| 100 | |
| 101 | #define P1_SW_EVENTS 0x46 |
| 102 | #define P2_SW_EVENTS 0x47 |
| 103 | #define P3_SW_EVENTS 0x48 |
| 104 | |
| 105 | #define VDD1_TRIM1 0x62 |
| 106 | #define VDD1_TRIM2 0x63 |
| 107 | #define VDD1_VFLOOR 0xBB |
| 108 | #define VDD1_VROOF 0xBC |
| 109 | #define PB_CFG 0x4A |
| 110 | #define PB_WORD_MSB 0x4B |
| 111 | #define PB_WORD_LSB 0x4C |
| 112 | |
| 113 | #define VSIM_REMAP 0x94 |
| 114 | #define VDAC_REMAP 0x98 |
| 115 | #define VINTANA1_DEV_GRP 0x9A |
| 116 | #define VINTANA1_REMAP 0x9C |
| 117 | #define VINTANA2_REMAP 0xA0 |
| 118 | #define VINTANA2_DEV_GRP 0x9E |
| 119 | #define VINTDIG_DEV_GRP 0xA2 |
| 120 | #define VINTDIG_REMAP 0xA4 |
| 121 | #define VIO_DEV_GRP 0xA6 |
| 122 | #define VIO_REMAP 0xA8 |
| 123 | #define VDD1_REMAP 0xB2 |
| 124 | #define VDD2_REMAP 0xC0 |
| 125 | #define REGEN_REMAP 0xDC |
| 126 | #define NRESPWRON_REMAP 0xDF |
| 127 | #define CLKEN_REMAP 0xE2 |
| 128 | #define SYSEN_REMAP 0xE5 |
| 129 | #define HFCLKOUT_REMAP 0xE8 |
| 130 | #define HFCLKOUT_DEV_GRP 0xE6 |
| 131 | #define T32KCLKOUT_REMAP 0xEB |
| 132 | #define TRITON_RESET_REMAP 0xEE |
| 133 | #define MAINREF_REMAP 0xF1 |
| 134 | #define VIBRA_CTL 0x45 |
| 135 | |
| 136 | |
| 137 | #define VUSB1V5_DEV_GRP 0xCC |
| 138 | #define VUSB1V5_TYPE 0xCD |
| 139 | #define VUSB1V5_REMAP 0xCE |
| 140 | #define VUSB1V8_DEV_GRP 0xCF |
| 141 | #define VUSB1V8_TYPE 0xD0 |
| 142 | #define VUSB1V8_REMAP 0xD1 |
| 143 | #define VUSB3V1_DEV_GRP 0xD2 |
| 144 | #define VUSB3V1_TYPE 0xD3 |
| 145 | #define VUSB3V1_REMAP 0xD4 |
| 146 | #define VUSBCP_DEV_GRP 0xD5 |
| 147 | #define VUSBCP_TYPE 0xD6 |
| 148 | #define VUSBCP_REMAP 0xD7 |
| 149 | #define VUSB_DEDICATED1 0xD8 |
| 150 | #define VUSB_DEDICATED2 0xD9 |
| 151 | |
| 152 | /* USB registers */ |
| 153 | #define VENDOR_ID_LO 0x0 |
| 154 | #define VENDOR_ID_HI 0x1 |
| 155 | #define PRODUCT_ID_LO 0x2 |
| 156 | #define PRODUCT_ID_HI 0x3 |
| 157 | #define FUNC_CTRL 0x4 |
| 158 | #define FUNC_CTRL_SET 0x5 |
| 159 | #define FUNC_CTRL_CLR 0x6 |
| 160 | # define SUSPENDM (1 << 6) |
| 161 | # define RESET (1 << 5) |
| 162 | # define OPMODE_MASK (3 << 3) /* bits 3 and 4 */ |
| 163 | # define OPMODE_NORMAL (0 << 3) |
| 164 | # define OPMODE_NONDRIVING (1 << 3) |
| 165 | # define OPMODE_DISABLE_BIT_NRZI (2 << 3) |
| 166 | # define TERMSELECT (1 << 2) |
| 167 | # define XCVRSELECT_MASK (3 << 0) /* bits 0 and 1 */ |
| 168 | # define XCVRSELECT_HS (0 << 0) |
| 169 | # define XCVRSELECT_FS (1 << 0) |
| 170 | # define XCVRSELECT_LS (2 << 0) |
| 171 | # define XCVRSELECT_FS4LS (3 << 0) |
| 172 | #define IFC_CTRL 0x7 |
| 173 | #define IFC_CTRL_SET 0x8 |
| 174 | #define IFC_CTRL_CLR 0x9 |
| 175 | # define INTERFACE_PROTECT_DISABLE (1 << 7) |
| 176 | # define AUTORESUME (1 << 4) |
| 177 | # define CLOCKSUSPENDM (1 << 3) |
| 178 | # define CARKITMODE (1 << 2) |
| 179 | # define FSLSSERIALMODE_3PIN (1 << 1) |
| 180 | #define OTG_CTRL 0xa |
| 181 | #define OTG_CTRL_SET 0xb |
| 182 | #define OTG_CTRL_CLR 0xc |
| 183 | #define DRVVBUS (1 << 5) |
| 184 | #define CHRGVBUS (1 << 4) |
| 185 | #define DISCHRGVBUS (1 << 3) |
| 186 | #define DMPULLDOWN (1 << 2) |
| 187 | #define DPPULLDOWN (1 << 1) |
| 188 | #define IDPULLUP (1 << 0) |
| 189 | #define USB_INT_EN_RISE 0xd |
| 190 | #define USB_INT_EN_RISE_SET 0xe |
| 191 | #define USB_INT_EN_RISE_CLR 0xf |
| 192 | #define USB_INT_EN_FALL 0x10 |
| 193 | #define USB_INT_EN_FALL_SET 0x11 |
| 194 | #define USB_INT_EN_FALL_CLR 0x12 |
| 195 | # define HOSTDISCONNECT (1 << 0) |
| 196 | #define USB_INT_STS 0x13 |
| 197 | #define USB_INT_LATCH 0x14 |
| 198 | #define USB_DEBUG 0x15 |
| 199 | #define SCRATCH_REG 0x16 |
| 200 | #define SCRATCH_REG_SET 0x17 |
| 201 | #define SCRATCH_REG_CLR 0x18 |
| 202 | #define CARKIT_CTRL 0x19 |
| 203 | #define CARKIT_CTRL_SET 0x1a |
| 204 | #define CARKIT_CTRL_CLR 0x1b |
| 205 | #define MICEN (1 << 6) |
| 206 | #define SPKRIGHTEN (1 << 5) |
| 207 | #define SPKLEFTEN (1 << 4) |
| 208 | #define RXDEN (1 << 3) |
| 209 | #define TXDEN (1 << 2) |
| 210 | #define IDGNDDRV (1 << 1) |
| 211 | #define CARKITPWR (1 << 0) |
| 212 | #define CARKIT_INT_DELAY 0x1c |
| 213 | #define CARKIT_INT_EN 0x1d |
| 214 | #define CARKIT_INT_EN_SET 0x1e |
| 215 | #define CARKIT_INT_EN_CLR 0x1f |
| 216 | #define CARKIT_INT_STS 0x20 |
| 217 | #define CARKIT_INT_LATCH 0x21 |
| 218 | #define CARKIT_PLS_CTRL 0x22 |
| 219 | #define CARKIT_PLS_CTRL_SET 0x23 |
| 220 | #define CARKIT_PLS_CTRL_CLR 0x24 |
| 221 | # define SPKRRIGHT_BIASEN (1 << 3) |
| 222 | # define SPKRLEFT_BIASEN (1 << 2) |
| 223 | # define RXPLSEN (1 << 1) |
| 224 | # define TXPLSEN (1 << 0) |
| 225 | #define TRANS_POS_WIDTH 0x25 |
| 226 | #define TRANS_NEG_WIDTH 0x26 |
| 227 | #define RCV_PLTY_RECOVERY 0x27 |
| 228 | #define MCPC_CTRL 0x30 |
| 229 | #define MCPC_CTRL_SET 0x31 |
| 230 | #define MCPC_CTRL_CLR 0x32 |
| 231 | #define RTSOL (1 << 7) |
| 232 | #define EXTSWR (1 << 6) |
| 233 | #define EXTSWC (1 << 5) |
| 234 | #define VOICESW (1 << 4) |
| 235 | #define OUT64K (1 << 3) |
| 236 | #define RTSCTSSW (1 << 2) |
| 237 | #define HS_UART (1 << 0) |
| 238 | #define MCPC_IO_CTRL 0x033 |
| 239 | #define MCPC_IO_CTRL_SET 0x034 |
| 240 | #define MCPC_IO_CTRL_CLR 0x035 |
| 241 | #define MICBIASEN (1<< 5) |
| 242 | #define CTS_NPU (1 << 4) |
| 243 | #define RXD_PU (1 << 3) |
| 244 | #define TXDTYP (1 << 2) |
| 245 | #define CTSTYP (1 << 1) |
| 246 | #define RTSTYP (1 << 0) |
| 247 | #define MCPC_CTRL2 0x036 |
| 248 | #define MCPC_CTRL2_SET 0x037 |
| 249 | #define MCPC_CTRL2_CLR 0x038 |
| 250 | # define MCPC_CK_EN (1 << 0) |
| 251 | #define OTHER_FUNC_CTRL 0x080 |
| 252 | #define OTHER_FUNC_CTRL_SET 0x081 |
| 253 | #define OTHER_FUNC_CTRL_CLR 0x082 |
| 254 | #define BDIS_ACON_EN (1<< 4) |
| 255 | #define FIVEWIRE_MODE (1 << 2) |
| 256 | #define OTHER_IFC_CTRL 0x083 |
| 257 | #define OTHER_IFC_CTRL_SET 0x084 |
| 258 | #define OTHER_IFC_CTRL_CLR 0x085 |
| 259 | # define OE_INT_EN (1 << 6) |
| 260 | # define CEA2011_MODE (1 << 5) |
| 261 | # define FSLSSERIALMODE_4PIN (1 << 4) |
| 262 | # define HIZ_ULPI_60MHZ_OUT (1 << 3) |
| 263 | # define HIZ_ULPI (1 << 2) |
| 264 | # define ALT_INT_REROUTE (1 << 0) |
| 265 | #define OTHER_INT_EN_RISE 0x086 |
| 266 | #define OTHER_INT_EN_RISE_SET 0x087 |
| 267 | #define OTHER_INT_EN_RISE_CLR 0x088 |
| 268 | #define OTHER_INT_EN_FALL 0x089 |
| 269 | #define OTHER_INT_EN_FALL_SET 0x08A |
| 270 | #define OTHER_INT_EN_FALL_CLR 0x08B |
| 271 | #define OTHER_INT_STS 0x8C |
| 272 | #define OTHER_INT_LATCH 0x8D |
| 273 | #define ID_INT_EN_RISE 0x08E |
| 274 | #define ID_INT_EN_RISE_SET 0x08F |
| 275 | #define ID_INT_EN_RISE_CLR 0x090 |
| 276 | #define ID_INT_EN_FALL 0x091 |
| 277 | #define ID_INT_EN_FALL_SET 0x092 |
| 278 | #define ID_INT_EN_FALL_CLR 0x093 |
| 279 | #define ID_INT_STS 0x094 |
| 280 | #define ID_INT_LATCH 0x95 |
| 281 | #define ID_STATUS 0x96 |
| 282 | #define CARKIT_SM_1_INT_EN 0x097 |
| 283 | #define CARKIT_SM_1_INT_EN_SET 0x098 |
| 284 | #define CARKIT_SM_1_INT_EN_CLR 0x099 |
| 285 | #define CARKIT_SM_1_INT_STS 0x09A |
| 286 | #define CARKIT_SM_1_INT_LATCH 0x9B |
| 287 | #define CARKIT_SM_2_INT_EN 0x09C |
| 288 | #define CARKIT_SM_2_INT_EN_SET 0x09D |
| 289 | #define CARKIT_SM_2_INT_EN_CLR 0x09E |
| 290 | #define CARKIT_SM_2_INT_STS 0x09F |
| 291 | #define CARKIT_SM_2_INT_LATCH 0xA0 |
| 292 | #define CARKIT_SM_CTRL 0x0A1 |
| 293 | #define CARKIT_SM_CTRL_SET 0x0A2 |
| 294 | #define CARKIT_SM_CTRL_CLR 0x0A3 |
| 295 | #define CARKIT_SM_CMD 0x0A4 |
| 296 | #define CARKIT_SM_CMD_SET 0x0A5 |
| 297 | #define CARKIT_SM_CMD_CLR 0x0A6 |
| 298 | #define CARKIT_SM_CMD_STS 0xA7 |
| 299 | #define CARKIT_SM_STATUS 0xA8 |
| 300 | #define CARKIT_SM_NEXT_STATUS 0xA9 |
| 301 | #define CARKIT_SM_ERR_STATUS 0xAA |
| 302 | #define CARKIT_SM_CTRL_STATE 0xAB |
| 303 | #define POWER_CTRL 0xAC |
| 304 | #define POWER_CTRL_SET 0xAD |
| 305 | #define POWER_CTRL_CLR 0xAE |
| 306 | # define OTG_ENAB (1 << 5) |
| 307 | #define OTHER_IFC_CTRL2 0xAF |
| 308 | #define OTHER_IFC_CTRL2_SET 0xB0 |
| 309 | #define OTHER_IFC_CTRL2_CLR 0xB1 |
| 310 | # define ULPI_TXEN_POL (1 << 3) |
| 311 | # define ULPI_4PIN_2430 (1 << 2) |
| 312 | #define REG_CTRL_EN 0xB2 |
| 313 | #define REG_CTRL_EN_SET 0xB3 |
| 314 | #define REG_CTRL_EN_CLR 0xB4 |
| 315 | #define REG_CTRL_ERROR 0xB5 |
| 316 | #define ULPI_I2C_CONFLICT_INTEN (1 << 0) |
| 317 | #define OTHER_FUNC_CTRL2 0xB8 |
| 318 | #define OTHER_FUNC_CTRL2_SET 0xB9 |
| 319 | #define OTHER_FUNC_CTRL2_CLR 0xBA |
| 320 | #define VBAT_TIMER_EN (1 << 0) |
| 321 | #define CARKIT_ANA_CTRL 0xBB |
| 322 | #define CARKIT_ANA_CTRL_SET 0xBC |
| 323 | #define CARKIT_ANA_CTRL_CLR 0xBD |
| 324 | #define VBUS_DEBOUNCE 0xC0 |
| 325 | #define ID_DEBOUNCE 0xC1 |
| 326 | #define TPH_DP_CON_MIN 0xC2 |
| 327 | #define TPH_DP_CON_MAX 0xC3 |
| 328 | #define TCR_DP_CON_MIN 0xC4 |
| 329 | #define TCR_DP_CON_MAX 0xC5 |
| 330 | #define TPH_DP_PD_SHORT 0xC6 |
| 331 | #define TPH_CMD_DLY 0xC7 |
| 332 | #define TPH_DET_RST 0xC8 |
| 333 | #define TPH_AUD_BIAS 0xC9 |
| 334 | #define TCR_UART_DET_MIN 0xCA |
| 335 | #define TCR_UART_DET_MAX 0xCB |
| 336 | #define TPH_ID_INT_PW 0xCD |
| 337 | #define TACC_ID_INT_WAIT 0xCE |
| 338 | #define TACC_ID_INT_PW 0xCF |
| 339 | #define TPH_CMD_WAIT 0xD0 |
| 340 | #define TPH_ACK_WAIT 0xD1 |
| 341 | #define TPH_DP_DISC_DET 0xD2 |
| 342 | #define VBAT_TIMER 0xD3 |
| 343 | #define CARKIT_4W_DEBUG 0xE0 |
| 344 | #define CARKIT_5W_DEBUG 0xE1 |
| 345 | #define CARKIT_5W_DEBUG 0xE1 |
| 346 | #define TEST_CTRL_CLR 0xEB |
| 347 | #define TEST_CARKIT_SET 0xEC |
| 348 | #define TEST_CARKIT_CLR 0xED |
| 349 | #define TEST_POWER_SET 0xEE |
| 350 | #define TEST_POWER_CLR 0xEF |
| 351 | #define TEST_ULPI 0xF0 |
| 352 | #define TXVR_EN_TEST_SET 0xF2 |
| 353 | #define TXVR_EN_TEST_CLR 0xF3 |
| 354 | #define VBUS_EN_TEST 0xF4 |
| 355 | #define ID_EN_TEST 0xF5 |
| 356 | #define PSM_EN_TEST_SET 0xF6 |
| 357 | #define PSM_EN_TEST_CLR 0xF7 |
| 358 | #define PHY_TRIM_CTRL 0xFC |
| 359 | #define PHY_PWR_CTRL 0xFD |
| 360 | # define PHYPWD (1 << 0) |
| 361 | #define PHY_CLK_CTRL 0xFE |
| 362 | # define CLOCKGATING_EN (1 << 2) |
| 363 | # define CLK32K_EN (1 << 1) |
| 364 | # define REQ_PHY_DPLL_CLK (1 << 0) |
| 365 | #define PHY_CLK_CTRL_STS 0xFF |
| 366 | # define PHY_DPLL_CLK (1 << 0) |
| 367 | |
| 368 | #endif |
| 369 | |