Duy Truong | f3ac7b3 | 2013-02-13 01:07:28 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2010, The Linux Foundation. All rights reserved. |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2 | |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
Duy Truong | f3ac7b3 | 2013-02-13 01:07:28 -0800 | [diff] [blame] | 12 | * * Neither the name of The Linux Foundation nor the names of its |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #ifndef __UART_DM_H__ |
| 30 | #define __UART_DM_H__ |
| 31 | |
| 32 | #include <platform/iomap.h> |
| 33 | |
| 34 | #define MSM_BOOT_UART_DM_EXTR_BITS(value, start_pos, end_pos) \ |
| 35 | ((value << (32 - end_pos))\ |
| 36 | >> (32 - (end_pos - start_pos))) |
| 37 | |
| 38 | /* UART Parity Mode */ |
| 39 | enum MSM_BOOT_UART_DM_PARITY_MODE { |
| 40 | MSM_BOOT_UART_DM_NO_PARITY, |
| 41 | MSM_BOOT_UART_DM_ODD_PARITY, |
| 42 | MSM_BOOT_UART_DM_EVEN_PARITY, |
| 43 | MSM_BOOT_UART_DM_SPACE_PARITY |
| 44 | }; |
| 45 | |
| 46 | /* UART Stop Bit Length */ |
| 47 | enum MSM_BOOT_UART_DM_STOP_BIT_LEN { |
| 48 | MSM_BOOT_UART_DM_SBL_9_16, |
| 49 | MSM_BOOT_UART_DM_SBL_1, |
| 50 | MSM_BOOT_UART_DM_SBL_1_9_16, |
| 51 | MSM_BOOT_UART_DM_SBL_2 |
| 52 | }; |
| 53 | |
| 54 | /* UART Bits per Char */ |
| 55 | enum MSM_BOOT_UART_DM_BITS_PER_CHAR { |
| 56 | MSM_BOOT_UART_DM_5_BPS, |
| 57 | MSM_BOOT_UART_DM_6_BPS, |
| 58 | MSM_BOOT_UART_DM_7_BPS, |
| 59 | MSM_BOOT_UART_DM_8_BPS |
| 60 | }; |
| 61 | |
| 62 | /* 8-N-1 Configuration */ |
| 63 | #define MSM_BOOT_UART_DM_8_N_1_MODE (MSM_BOOT_UART_DM_NO_PARITY | \ |
| 64 | (MSM_BOOT_UART_DM_SBL_1 << 2) | \ |
| 65 | (MSM_BOOT_UART_DM_8_BPS << 4)) |
| 66 | |
| 67 | /* UART_DM Registers */ |
| 68 | |
| 69 | /* UART Operational Mode Register */ |
Amol Jadi | a63aaff | 2012-02-01 15:51:50 -0800 | [diff] [blame] | 70 | #define MSM_BOOT_UART_DM_MR1(base) ((base) + 0x00) |
| 71 | #define MSM_BOOT_UART_DM_MR2(base) ((base) + 0x04) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 72 | #define MSM_BOOT_UART_DM_RXBRK_ZERO_CHAR_OFF (1 << 8) |
| 73 | #define MSM_BOOT_UART_DM_LOOPBACK (1 << 7) |
| 74 | |
| 75 | /* UART Clock Selection Register */ |
Deepa Dinamani | bce9d9e | 2012-05-17 13:53:17 -0700 | [diff] [blame] | 76 | #if PERIPH_BLK_BLSP |
| 77 | #define MSM_BOOT_UART_DM_CSR(base) ((base) + 0xA0) |
| 78 | #else |
Amol Jadi | a63aaff | 2012-02-01 15:51:50 -0800 | [diff] [blame] | 79 | #define MSM_BOOT_UART_DM_CSR(base) ((base) + 0x08) |
Deepa Dinamani | bce9d9e | 2012-05-17 13:53:17 -0700 | [diff] [blame] | 80 | #endif |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 81 | |
| 82 | /* UART DM TX FIFO Registers - 4 */ |
Deepa Dinamani | bce9d9e | 2012-05-17 13:53:17 -0700 | [diff] [blame] | 83 | #if PERIPH_BLK_BLSP |
Deepa Dinamani | 26e9326 | 2012-05-21 17:35:14 -0700 | [diff] [blame] | 84 | #define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x100+(4*(x))) |
Deepa Dinamani | bce9d9e | 2012-05-17 13:53:17 -0700 | [diff] [blame] | 85 | #else |
Amol Jadi | a63aaff | 2012-02-01 15:51:50 -0800 | [diff] [blame] | 86 | #define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x70+(4*(x))) |
Deepa Dinamani | bce9d9e | 2012-05-17 13:53:17 -0700 | [diff] [blame] | 87 | #endif |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 88 | |
| 89 | /* UART Command Register */ |
Deepa Dinamani | bce9d9e | 2012-05-17 13:53:17 -0700 | [diff] [blame] | 90 | #if PERIPH_BLK_BLSP |
| 91 | #define MSM_BOOT_UART_DM_CR(base) ((base) + 0xA8) |
| 92 | #else |
Amol Jadi | a63aaff | 2012-02-01 15:51:50 -0800 | [diff] [blame] | 93 | #define MSM_BOOT_UART_DM_CR(base) ((base) + 0x10) |
Deepa Dinamani | bce9d9e | 2012-05-17 13:53:17 -0700 | [diff] [blame] | 94 | #endif |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 95 | #define MSM_BOOT_UART_DM_CR_RX_ENABLE (1 << 0) |
| 96 | #define MSM_BOOT_UART_DM_CR_RX_DISABLE (1 << 1) |
| 97 | #define MSM_BOOT_UART_DM_CR_TX_ENABLE (1 << 2) |
| 98 | #define MSM_BOOT_UART_DM_CR_TX_DISABLE (1 << 3) |
| 99 | |
| 100 | /* UART Channel Command */ |
| 101 | #define MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) ((x & 0x0f) << 4) |
| 102 | #define MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x) ((x >> 4 ) << 11 ) |
Deepa Dinamani | bce9d9e | 2012-05-17 13:53:17 -0700 | [diff] [blame] | 103 | #define MSM_BOOT_UART_DM_CR_CH_CMD(x) (MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x)\ |
| 104 | | MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x)) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 105 | #define MSM_BOOT_UART_DM_CMD_NULL MSM_BOOT_UART_DM_CR_CH_CMD(0) |
| 106 | #define MSM_BOOT_UART_DM_CMD_RESET_RX MSM_BOOT_UART_DM_CR_CH_CMD(1) |
| 107 | #define MSM_BOOT_UART_DM_CMD_RESET_TX MSM_BOOT_UART_DM_CR_CH_CMD(2) |
| 108 | #define MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT MSM_BOOT_UART_DM_CR_CH_CMD(3) |
| 109 | #define MSM_BOOT_UART_DM_CMD_RES_BRK_CHG_INT MSM_BOOT_UART_DM_CR_CH_CMD(4) |
| 110 | #define MSM_BOOT_UART_DM_CMD_START_BRK MSM_BOOT_UART_DM_CR_CH_CMD(5) |
| 111 | #define MSM_BOOT_UART_DM_CMD_STOP_BRK MSM_BOOT_UART_DM_CR_CH_CMD(6) |
| 112 | #define MSM_BOOT_UART_DM_CMD_RES_CTS_N MSM_BOOT_UART_DM_CR_CH_CMD(7) |
| 113 | #define MSM_BOOT_UART_DM_CMD_RES_STALE_INT MSM_BOOT_UART_DM_CR_CH_CMD(8) |
| 114 | #define MSM_BOOT_UART_DM_CMD_PACKET_MODE MSM_BOOT_UART_DM_CR_CH_CMD(9) |
| 115 | #define MSM_BOOT_UART_DM_CMD_MODE_RESET MSM_BOOT_UART_DM_CR_CH_CMD(C) |
| 116 | #define MSM_BOOT_UART_DM_CMD_SET_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(D) |
| 117 | #define MSM_BOOT_UART_DM_CMD_RES_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(E) |
| 118 | #define MSM_BOOT_UART_DM_CMD_RES_TX_ERR MSM_BOOT_UART_DM_CR_CH_CMD(10) |
| 119 | #define MSM_BOOT_UART_DM_CMD_CLR_TX_DONE MSM_BOOT_UART_DM_CR_CH_CMD(11) |
| 120 | #define MSM_BOOT_UART_DM_CMD_RES_BRKSTRT_INT MSM_BOOT_UART_DM_CR_CH_CMD(12) |
| 121 | #define MSM_BOOT_UART_DM_CMD_RES_BRKEND_INT MSM_BOOT_UART_DM_CR_CH_CMD(13) |
| 122 | #define MSM_BOOT_UART_DM_CMD_RES_PER_FRM_INT MSM_BOOT_UART_DM_CR_CH_CMD(14) |
| 123 | |
| 124 | /*UART General Command */ |
| 125 | #define MSM_BOOT_UART_DM_CR_GENERAL_CMD(x) ((x) << 8) |
| 126 | |
| 127 | #define MSM_BOOT_UART_DM_GCMD_NULL MSM_BOOT_UART_DM_CR_GENERAL_CMD(0) |
| 128 | #define MSM_BOOT_UART_DM_GCMD_CR_PROT_EN MSM_BOOT_UART_DM_CR_GENERAL_CMD(1) |
| 129 | #define MSM_BOOT_UART_DM_GCMD_CR_PROT_DIS MSM_BOOT_UART_DM_CR_GENERAL_CMD(2) |
| 130 | #define MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT MSM_BOOT_UART_DM_CR_GENERAL_CMD(3) |
| 131 | #define MSM_BOOT_UART_DM_GCMD_SW_FORCE_STALE MSM_BOOT_UART_DM_CR_GENERAL_CMD(4) |
| 132 | #define MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(5) |
| 133 | #define MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(6) |
| 134 | |
| 135 | /* UART Interrupt Mask Register */ |
Deepa Dinamani | bce9d9e | 2012-05-17 13:53:17 -0700 | [diff] [blame] | 136 | #if PERIPH_BLK_BLSP |
| 137 | #define MSM_BOOT_UART_DM_IMR(base) ((base) + 0xB0) |
| 138 | #else |
Amol Jadi | a63aaff | 2012-02-01 15:51:50 -0800 | [diff] [blame] | 139 | #define MSM_BOOT_UART_DM_IMR(base) ((base) + 0x14) |
Deepa Dinamani | bce9d9e | 2012-05-17 13:53:17 -0700 | [diff] [blame] | 140 | #endif |
| 141 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 142 | #define MSM_BOOT_UART_DM_TXLEV (1 << 0) |
| 143 | #define MSM_BOOT_UART_DM_RXHUNT (1 << 1) |
| 144 | #define MSM_BOOT_UART_DM_RXBRK_CHNG (1 << 2) |
| 145 | #define MSM_BOOT_UART_DM_RXSTALE (1 << 3) |
| 146 | #define MSM_BOOT_UART_DM_RXLEV (1 << 4) |
| 147 | #define MSM_BOOT_UART_DM_DELTA_CTS (1 << 5) |
| 148 | #define MSM_BOOT_UART_DM_CURRENT_CTS (1 << 6) |
| 149 | #define MSM_BOOT_UART_DM_TX_READY (1 << 7) |
| 150 | #define MSM_BOOT_UART_DM_TX_ERROR (1 << 8) |
| 151 | #define MSM_BOOT_UART_DM_TX_DONE (1 << 9) |
| 152 | #define MSM_BOOT_UART_DM_RXBREAK_START (1 << 10) |
| 153 | #define MSM_BOOT_UART_DM_RXBREAK_END (1 << 11) |
| 154 | #define MSM_BOOT_UART_DM_PAR_FRAME_ERR_IRQ (1 << 12) |
| 155 | |
| 156 | #define MSM_BOOT_UART_DM_IMR_ENABLED (MSM_BOOT_UART_DM_TX_READY | \ |
| 157 | MSM_BOOT_UART_DM_TXLEV | \ |
| 158 | MSM_BOOT_UART_DM_RXLEV | \ |
| 159 | MSM_BOOT_UART_DM_RXSTALE) |
| 160 | |
| 161 | /* UART Interrupt Programming Register */ |
Amol Jadi | a63aaff | 2012-02-01 15:51:50 -0800 | [diff] [blame] | 162 | #define MSM_BOOT_UART_DM_IPR(base) ((base) + 0x18) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 163 | #define MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB 0x0f |
| 164 | #define MSM_BOOT_UART_DM_STALE_TIMEOUT_MSB 0 /* Not used currently */ |
| 165 | |
| 166 | /* UART Transmit/Receive FIFO Watermark Register */ |
Amol Jadi | a63aaff | 2012-02-01 15:51:50 -0800 | [diff] [blame] | 167 | #define MSM_BOOT_UART_DM_TFWR(base) ((base) + 0x1C) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 168 | /* Interrupt is generated when FIFO level is less than or equal to this value */ |
| 169 | #define MSM_BOOT_UART_DM_TFW_VALUE 0 |
| 170 | |
Amol Jadi | a63aaff | 2012-02-01 15:51:50 -0800 | [diff] [blame] | 171 | #define MSM_BOOT_UART_DM_RFWR(base) ((base) + 0x20) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 172 | /*Interrupt generated when no of words in RX FIFO is greater than this value */ |
| 173 | #define MSM_BOOT_UART_DM_RFW_VALUE 0 |
| 174 | |
| 175 | /* UART Hunt Character Register */ |
Amol Jadi | a63aaff | 2012-02-01 15:51:50 -0800 | [diff] [blame] | 176 | #define MSM_BOOT_UART_DM_HCR(base) ((base) + 0x24) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 177 | |
| 178 | /* Used for RX transfer initialization */ |
Amol Jadi | a63aaff | 2012-02-01 15:51:50 -0800 | [diff] [blame] | 179 | #define MSM_BOOT_UART_DM_DMRX(base) ((base) + 0x34) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 180 | |
| 181 | /* Default DMRX value - any value bigger than FIFO size would be fine */ |
| 182 | #define MSM_BOOT_UART_DM_DMRX_DEF_VALUE 0x220 |
| 183 | |
| 184 | /* Register to enable IRDA function */ |
Deepa Dinamani | bce9d9e | 2012-05-17 13:53:17 -0700 | [diff] [blame] | 185 | #if PERIPH_BLK_BLSP |
| 186 | #define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0xB8) |
| 187 | #else |
Amol Jadi | a63aaff | 2012-02-01 15:51:50 -0800 | [diff] [blame] | 188 | #define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0x38) |
Deepa Dinamani | bce9d9e | 2012-05-17 13:53:17 -0700 | [diff] [blame] | 189 | #endif |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 190 | |
| 191 | /* UART Data Mover Enable Register */ |
Amol Jadi | a63aaff | 2012-02-01 15:51:50 -0800 | [diff] [blame] | 192 | #define MSM_BOOT_UART_DM_DMEN(base) ((base) + 0x3C) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 193 | |
| 194 | /* Number of characters for Transmission */ |
Amol Jadi | a63aaff | 2012-02-01 15:51:50 -0800 | [diff] [blame] | 195 | #define MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base) ((base) + 0x040) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 196 | |
| 197 | /* UART RX FIFO Base Address */ |
Amol Jadi | a63aaff | 2012-02-01 15:51:50 -0800 | [diff] [blame] | 198 | #define MSM_BOOT_UART_DM_BADR(base) ((base) + 0x44) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 199 | |
| 200 | /* UART Status Register */ |
Deepa Dinamani | bce9d9e | 2012-05-17 13:53:17 -0700 | [diff] [blame] | 201 | #if PERIPH_BLK_BLSP |
| 202 | #define MSM_BOOT_UART_DM_SR(base) ((base) + 0x0A4) |
| 203 | #else |
Amol Jadi | a63aaff | 2012-02-01 15:51:50 -0800 | [diff] [blame] | 204 | #define MSM_BOOT_UART_DM_SR(base) ((base) + 0x008) |
Deepa Dinamani | bce9d9e | 2012-05-17 13:53:17 -0700 | [diff] [blame] | 205 | #endif |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 206 | #define MSM_BOOT_UART_DM_SR_RXRDY (1 << 0) |
| 207 | #define MSM_BOOT_UART_DM_SR_RXFULL (1 << 1) |
| 208 | #define MSM_BOOT_UART_DM_SR_TXRDY (1 << 2) |
| 209 | #define MSM_BOOT_UART_DM_SR_TXEMT (1 << 3) |
| 210 | #define MSM_BOOT_UART_DM_SR_UART_OVERRUN (1 << 4) |
| 211 | #define MSM_BOOT_UART_DM_SR_PAR_FRAME_ERR (1 << 5) |
| 212 | #define MSM_BOOT_UART_DM_RX_BREAK (1 << 6) |
| 213 | #define MSM_BOOT_UART_DM_HUNT_CHAR (1 << 7) |
| 214 | #define MSM_BOOT_UART_DM_RX_BRK_START_LAST (1 << 8) |
| 215 | |
| 216 | /* UART Receive FIFO Registers - 4 in numbers */ |
Deepa Dinamani | bce9d9e | 2012-05-17 13:53:17 -0700 | [diff] [blame] | 217 | #if PERIPH_BLK_BLSP |
| 218 | #define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x140 + (4*(x))) |
| 219 | #else |
Amol Jadi | a63aaff | 2012-02-01 15:51:50 -0800 | [diff] [blame] | 220 | #define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x70 + (4*(x))) |
Deepa Dinamani | bce9d9e | 2012-05-17 13:53:17 -0700 | [diff] [blame] | 221 | #endif |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 222 | |
| 223 | /* UART Masked Interrupt Status Register */ |
Deepa Dinamani | bce9d9e | 2012-05-17 13:53:17 -0700 | [diff] [blame] | 224 | #if PERIPH_BLK_BLSP |
| 225 | #define MSM_BOOT_UART_DM_MISR(base) ((base) + 0xAC) |
| 226 | #else |
Amol Jadi | a63aaff | 2012-02-01 15:51:50 -0800 | [diff] [blame] | 227 | #define MSM_BOOT_UART_DM_MISR(base) ((base) + 0x10) |
Deepa Dinamani | bce9d9e | 2012-05-17 13:53:17 -0700 | [diff] [blame] | 228 | #endif |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 229 | |
| 230 | /* UART Interrupt Status Register */ |
Deepa Dinamani | bce9d9e | 2012-05-17 13:53:17 -0700 | [diff] [blame] | 231 | #if PERIPH_BLK_BLSP |
| 232 | #define MSM_BOOT_UART_DM_ISR(base) ((base) + 0xB4) |
| 233 | #else |
Amol Jadi | a63aaff | 2012-02-01 15:51:50 -0800 | [diff] [blame] | 234 | #define MSM_BOOT_UART_DM_ISR(base) ((base) + 0x14) |
Deepa Dinamani | bce9d9e | 2012-05-17 13:53:17 -0700 | [diff] [blame] | 235 | #endif |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 236 | |
| 237 | /* Number of characters received since the end of last RX transfer */ |
Deepa Dinamani | bce9d9e | 2012-05-17 13:53:17 -0700 | [diff] [blame] | 238 | #if PERIPH_BLK_BLSP |
| 239 | #define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0xBC) |
| 240 | #else |
Amol Jadi | a63aaff | 2012-02-01 15:51:50 -0800 | [diff] [blame] | 241 | #define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0x38) |
Deepa Dinamani | bce9d9e | 2012-05-17 13:53:17 -0700 | [diff] [blame] | 242 | #endif |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 243 | |
| 244 | /* UART TX FIFO Status Register */ |
Amol Jadi | a63aaff | 2012-02-01 15:51:50 -0800 | [diff] [blame] | 245 | #define MSM_BOOT_UART_DM_TXFS(base) ((base) + 0x4C) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 246 | #define MSM_BOOT_UART_DM_TXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6) |
| 247 | #define MSM_BOOT_UART_DM_TXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31) |
| 248 | #define MSM_BOOT_UART_DM_TXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9) |
| 249 | #define MSM_BOOT_UART_DM_TXFS_ASYNC_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,10,13) |
| 250 | |
| 251 | /* UART RX FIFO Status Register */ |
Amol Jadi | a63aaff | 2012-02-01 15:51:50 -0800 | [diff] [blame] | 252 | #define MSM_BOOT_UART_DM_RXFS(base) ((base) + 0x50) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 253 | #define MSM_BOOT_UART_DM_RXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6) |
| 254 | #define MSM_BOOT_UART_DM_RXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31) |
| 255 | #define MSM_BOOT_UART_DM_RXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9) |
| 256 | #define MSM_BOOT_UART_DM_RXFS_ASYNC_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,10,13) |
| 257 | |
| 258 | /* Macros for Common Errors */ |
| 259 | #define MSM_BOOT_UART_DM_E_SUCCESS 0 |
| 260 | #define MSM_BOOT_UART_DM_E_FAILURE 1 |
| 261 | #define MSM_BOOT_UART_DM_E_TIMEOUT 2 |
| 262 | #define MSM_BOOT_UART_DM_E_INVAL 3 |
| 263 | #define MSM_BOOT_UART_DM_E_MALLOC_FAIL 4 |
| 264 | #define MSM_BOOT_UART_DM_E_RX_NOT_READY 5 |
| 265 | |
Amol Jadi | a63aaff | 2012-02-01 15:51:50 -0800 | [diff] [blame] | 266 | void uart_dm_init(uint8_t id, |
| 267 | uint32_t gsbi_base, |
| 268 | uint32_t uart_dm_base); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 269 | #endif /* __UART_DM_H__ */ |