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Kuogee Hsieh7c3982a2013-12-18 14:13:45 -08001/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -08002 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions
5 * are met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above copyright
9 * notice, this list of conditions and the following disclaimer in
10 * the documentation and/or other materials provided with the
11 * distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
19 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
20 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
23 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
26 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30#include <debug.h>
31#include <smem.h>
Casey Piper7d7b0522013-09-09 20:42:15 -070032#include <err.h>
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -080033#include <msm_panel.h>
Casey Piper7d7b0522013-09-09 20:42:15 -070034#include <mipi_dsi.h>
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -080035#include <pm8x41.h>
36#include <pm8x41_wled.h>
37#include <board.h>
38#include <mdp5.h>
39#include <platform/gpio.h>
Asaf Pensoc9080dc2013-05-21 21:53:50 +030040#include <platform/clock.h>
Siddhartha Agrawal1b2ed842013-05-29 18:02:28 -070041#include <platform/iomap.h>
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -080042#include <target/display.h>
Casey Piper7d7b0522013-09-09 20:42:15 -070043#include "include/panel.h"
44#include "include/display_resource.h"
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -080045
46static struct msm_fb_panel_data panel;
Casey Piper7d7b0522013-09-09 20:42:15 -070047static uint8_t edp_enable;
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -080048
Casey Piper7d7b0522013-09-09 20:42:15 -070049#define HFPLL_LDO_ID 12
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -080050
Asaf Penso0ecd86f2013-05-29 14:49:19 +030051static struct pm8x41_wled_data wled_ctrl = {
Amy Maloche543b5842013-07-31 18:07:38 -070052 .mod_scheme = 0x00,
Asaf Penso0ecd86f2013-05-29 14:49:19 +030053 .led1_brightness = (0x0F << 8) | 0xEF,
54 .led2_brightness = (0x0F << 8) | 0xEF,
55 .led3_brightness = (0x0F << 8) | 0xEF,
56 .max_duty_cycle = 0x01,
57 .ovp = 0x2,
58 .full_current_scale = 0x19
59};
60
Dhaval Patele9331fc2014-03-18 11:45:53 -070061static uint32_t dsi_pll_lock_status(uint32_t ctl_base)
Casey Piper7d7b0522013-09-09 20:42:15 -070062{
Dhaval Patele9331fc2014-03-18 11:45:53 -070063 uint32_t counter, status;
Casey Piper7d7b0522013-09-09 20:42:15 -070064
Dhaval Patele9331fc2014-03-18 11:45:53 -070065 udelay(100);
66 mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
67
68 status = readl(ctl_base + 0x02c0) & 0x01;
69 for (counter = 0; counter < 5 && !status; counter++) {
70 udelay(100);
71 status = readl(ctl_base + 0x02c0) & 0x01;
72 }
73
74 return status;
75}
76
77static uint32_t dsi_pll_enable_seq_b(uint32_t ctl_base)
78{
Casey Piper7d7b0522013-09-09 20:42:15 -070079 mdss_dsi_uniphy_pll_sw_reset(ctl_base);
80
81 writel(0x01, ctl_base + 0x0220); /* GLB CFG */
Dhaval Patele9331fc2014-03-18 11:45:53 -070082 udelay(1);
Casey Piper7d7b0522013-09-09 20:42:15 -070083 writel(0x05, ctl_base + 0x0220); /* GLB CFG */
Dhaval Patele9331fc2014-03-18 11:45:53 -070084 udelay(200);
Casey Piper7d7b0522013-09-09 20:42:15 -070085 writel(0x07, ctl_base + 0x0220); /* GLB CFG */
Dhaval Patele9331fc2014-03-18 11:45:53 -070086 udelay(500);
Casey Piper7d7b0522013-09-09 20:42:15 -070087 writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
Dhaval Patele9331fc2014-03-18 11:45:53 -070088 udelay(500);
Casey Piper7d7b0522013-09-09 20:42:15 -070089
Dhaval Patele9331fc2014-03-18 11:45:53 -070090 return dsi_pll_lock_status(ctl_base);
91}
Casey Piper7d7b0522013-09-09 20:42:15 -070092
Dhaval Patele9331fc2014-03-18 11:45:53 -070093static uint32_t dsi_pll_enable_seq_d(uint32_t ctl_base)
94{
95 mdss_dsi_uniphy_pll_sw_reset(ctl_base);
96
97 writel(0x01, ctl_base + 0x0220); /* GLB CFG */
98 udelay(1);
99 writel(0x05, ctl_base + 0x0220); /* GLB CFG */
100 udelay(200);
101 writel(0x07, ctl_base + 0x0220); /* GLB CFG */
102 udelay(250);
103 writel(0x05, ctl_base + 0x0220); /* GLB CFG */
104 udelay(200);
105 writel(0x07, ctl_base + 0x0220); /* GLB CFG */
106 udelay(500);
107 writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
108 udelay(500);
109
110 return dsi_pll_lock_status(ctl_base);
111}
112
113static void dsi_pll_enable_seq(uint32_t ctl_base)
114{
115 uint32_t counter, status;
116
117 for (counter = 0; counter < 3; counter++) {
118 status = dsi_pll_enable_seq_b(ctl_base);
119 if (status)
120 break;
121 status = dsi_pll_enable_seq_d(ctl_base);
122 if (status)
123 break;
124 status = dsi_pll_enable_seq_d(ctl_base);
125 if(status)
126 break;
Casey Piper7d7b0522013-09-09 20:42:15 -0700127 }
Dhaval Patele9331fc2014-03-18 11:45:53 -0700128
129 if (!status)
130 dprintf(CRITICAL, "Pll lock sequence failed\n");
Casey Piper7d7b0522013-09-09 20:42:15 -0700131}
132
Kuogee Hsieh7c3982a2013-12-18 14:13:45 -0800133static int msm8974_wled_backlight_ctrl(uint8_t enable)
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -0800134{
Chandan Uddarajud1bcbeb2013-07-01 18:13:48 -0700135 uint32_t platform_id = board_platform_id();
136 uint32_t hardware_id = board_hardware_id();
Casey Piper7d7b0522013-09-09 20:42:15 -0700137 uint8_t slave_id = 1;
Chandan Uddarajud1bcbeb2013-07-01 18:13:48 -0700138
Casey Piper7d7b0522013-09-09 20:42:15 -0700139 if (enable) {
140 if (platform_id == MSM8974AC)
141 if ((hardware_id == HW_PLATFORM_MTP)
142 || (hardware_id == HW_PLATFORM_LIQUID))
143 slave_id = 3;
Chandan Uddarajud1bcbeb2013-07-01 18:13:48 -0700144
Casey Piper7d7b0522013-09-09 20:42:15 -0700145 pm8x41_wled_config_slave_id(slave_id);
146 pm8x41_wled_config(&wled_ctrl);
147 pm8x41_wled_sink_control(enable);
148 pm8x41_wled_iled_sync_control(enable);
Jayant Shekhar4f3d2b22013-12-06 17:36:07 +0530149 pm8x41_wled_led_mod_enable(enable);
Casey Piper7d7b0522013-09-09 20:42:15 -0700150 }
151 pm8x41_wled_enable(enable);
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -0800152
Casey Piper7d7b0522013-09-09 20:42:15 -0700153 return NO_ERROR;
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -0800154}
155
Kuogee Hsieh7c3982a2013-12-18 14:13:45 -0800156static int msm8974_pwm_backlight_ctrl(int gpio_num, int lpg_chan, int enable)
157{
158 struct pm8x41_gpio gpio_param = {
159 .direction = PM_GPIO_DIR_OUT,
160 .function = PM_GPIO_FUNC_2,
161 .vin_sel = 2, /* VIN_2 */
162 .pull = PM_GPIO_PULL_UP_1_5 | PM_GPIO_PULLDOWN_10,
163 .output_buffer = PM_GPIO_OUT_CMOS,
164 .out_strength = PM_GPIO_OUT_DRIVE_HIGH,
165 };
166
167 dprintf(SPEW, "%s: gpio=%d lpg=%d enable=%d\n", __func__,
168 gpio_num, lpg_chan, enable);
169
170 if (enable) {
171 pm8x41_gpio_config(gpio_num, &gpio_param);
172 pm8x41_lpg_write(lpg_chan, 0x41, 0x33); /* LPG_PWM_SIZE_CLK, */
173 pm8x41_lpg_write(lpg_chan, 0x42, 0x01); /* LPG_PWM_FREQ_PREDIV */
174 pm8x41_lpg_write(lpg_chan, 0x43, 0x20); /* LPG_PWM_TYPE_CONFIG */
175 pm8x41_lpg_write(lpg_chan, 0x44, 0xb2); /* LPG_VALUE_LSB */
176 pm8x41_lpg_write(lpg_chan, 0x45, 0x01); /* LPG_VALUE_MSB */
177 pm8x41_lpg_write(lpg_chan, 0x46, 0xe4); /* LPG_ENABLE_CONTROL */
178 } else {
179 pm8x41_lpg_write(lpg_chan, 0x46, 0x00);
180 }
181
182 return NO_ERROR;
183}
184
185int target_backlight_ctrl(struct backlight *bl, uint8_t enable)
186{
187 uint32_t ret = NO_ERROR;
188
189 if (!bl) {
190 dprintf(CRITICAL, "backlight structure is not available\n");
191 return ERR_INVALID_ARGS;
192 }
193
194 switch (bl->bl_interface_type) {
195 case BL_WLED:
196 ret = msm8974_wled_backlight_ctrl(enable);
197 break;
198 case BL_PWM:
Dhaval Patel18bf4c62014-01-07 21:57:30 -0800199 ret = msm8974_pwm_backlight_ctrl(pwm_gpio.pin_id,
200 PWM_BL_LPG_CHAN_ID,
Kuogee Hsieh7c3982a2013-12-18 14:13:45 -0800201 enable);
202 break;
203 default:
204 dprintf(CRITICAL, "backlight type:%d not supported\n",
205 bl->bl_interface_type);
206 return ERR_NOT_SUPPORTED;
207 }
208
209 return ret;
210}
211
Casey Piper7d7b0522013-09-09 20:42:15 -0700212int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -0800213{
Casey Piper7d7b0522013-09-09 20:42:15 -0700214 struct mdss_dsi_pll_config *pll_data;
215 uint32_t dual_dsi = pinfo->mipi.dual_dsi;
216 dprintf(SPEW, "target_panel_clock\n");
217
218 pll_data = pinfo->mipi.dsi_pll_config;
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -0800219 if (enable) {
220 mdp_gdsc_ctrl(enable);
221 mdp_clock_init();
Siddhartha Agrawalf7ae5da2013-09-26 13:30:33 -0700222 mdss_dsi_auto_pll_config(MIPI_DSI0_BASE, pll_data);
Casey Piper7d7b0522013-09-09 20:42:15 -0700223 dsi_pll_enable_seq(MIPI_DSI0_BASE);
Casey Piper7d7b0522013-09-09 20:42:15 -0700224 mmss_clock_auto_pll_init(DSI0_PHY_PLL_OUT, dual_dsi,
225 pll_data->pclk_m,
226 pll_data->pclk_n,
227 pll_data->pclk_d);
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -0800228 } else if(!target_cont_splash_screen()) {
229 // * Add here for continuous splash *
Siddhartha Agrawalc88737b2013-05-29 20:41:35 -0700230 mmss_clock_disable(dual_dsi);
231 mdp_clock_disable(dual_dsi);
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -0800232 }
233
Casey Piper7d7b0522013-09-09 20:42:15 -0700234 return NO_ERROR;
Asaf Penso325f43a2013-05-21 21:55:48 +0300235}
236
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -0800237/* Pull DISP_RST_N high to get panel out of reset */
Casey Piper7d7b0522013-09-09 20:42:15 -0700238int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
239 struct msm_panel_info *pinfo)
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -0800240{
Casey Piper7d7b0522013-09-09 20:42:15 -0700241 uint32_t rst_gpio = reset_gpio.pin_id;
Chandan Uddarajud1bcbeb2013-07-01 18:13:48 -0700242 uint32_t platform_id = board_platform_id();
243 uint32_t hardware_id = board_hardware_id();
244
Casey Piper7d7b0522013-09-09 20:42:15 -0700245 struct pm8x41_gpio resetgpio_param = {
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -0800246 .direction = PM_GPIO_DIR_OUT,
247 .output_buffer = PM_GPIO_OUT_CMOS,
248 .out_strength = PM_GPIO_OUT_DRIVE_MED,
249 };
250
Chandan Uddarajud1bcbeb2013-07-01 18:13:48 -0700251 if (platform_id == MSM8974AC)
Chandan Uddarajub2cee902013-09-05 18:31:23 -0700252 if ((hardware_id == HW_PLATFORM_MTP)
Chandan Uddarajud1bcbeb2013-07-01 18:13:48 -0700253 || (hardware_id == HW_PLATFORM_LIQUID))
254 rst_gpio = 20;
255
256 dprintf(SPEW, "platform_id: %u, rst_gpio: %u\n",
257 platform_id, rst_gpio);
258
Casey Piper7d7b0522013-09-09 20:42:15 -0700259 pm8x41_gpio_config(rst_gpio, &resetgpio_param);
Siddhartha Agrawalc43c4872013-04-21 16:23:16 -0700260 if (enable) {
Casey Piper7d7b0522013-09-09 20:42:15 -0700261 gpio_tlmm_config(enable_gpio.pin_id, 0,
262 enable_gpio.pin_direction, enable_gpio.pin_pull,
263 enable_gpio.pin_strength, enable_gpio.pin_state);
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -0800264
Casey Piper7d7b0522013-09-09 20:42:15 -0700265 gpio_set(enable_gpio.pin_id, resetseq->pin_direction);
266 pm8x41_gpio_set(rst_gpio, resetseq->pin_state[0]);
267 mdelay(resetseq->sleep[0]);
268 pm8x41_gpio_set(rst_gpio, resetseq->pin_state[1]);
269 mdelay(resetseq->sleep[1]);
270 pm8x41_gpio_set(rst_gpio, resetseq->pin_state[2]);
271 mdelay(resetseq->sleep[2]);
Siddhartha Agrawalc43c4872013-04-21 16:23:16 -0700272 } else {
Casey Piper7d7b0522013-09-09 20:42:15 -0700273 resetgpio_param.out_strength = PM_GPIO_OUT_DRIVE_LOW;
274 pm8x41_gpio_config(rst_gpio, &resetgpio_param);
Chandan Uddarajud1bcbeb2013-07-01 18:13:48 -0700275 pm8x41_gpio_set(rst_gpio, PM_GPIO_FUNC_LOW);
Casey Piper7d7b0522013-09-09 20:42:15 -0700276 gpio_set(enable_gpio.pin_id, resetseq->pin_direction);
Siddhartha Agrawalc43c4872013-04-21 16:23:16 -0700277 }
Casey Piper7d7b0522013-09-09 20:42:15 -0700278 return NO_ERROR;
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -0800279}
280
Casey Piper7d7b0522013-09-09 20:42:15 -0700281int target_ldo_ctrl(uint8_t enable)
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -0800282{
Casey Piper7d7b0522013-09-09 20:42:15 -0700283 uint32_t ldocounter = 0;
284 uint32_t pm8x41_ldo_base = 0x13F00;
Deepa Dinamaniec4835b2013-06-03 16:14:24 -0700285
Casey Piper7d7b0522013-09-09 20:42:15 -0700286 while (ldocounter < TOTAL_LDO_DEFINED) {
287 struct pm8x41_ldo ldo_entry = LDO((pm8x41_ldo_base +
288 0x100 * ldo_entry_array[ldocounter].ldo_id),
289 ldo_entry_array[ldocounter].ldo_type);
Deepa Dinamaniec4835b2013-06-03 16:14:24 -0700290
Casey Piper7d7b0522013-09-09 20:42:15 -0700291 dprintf(SPEW, "Setting %s\n",
292 ldo_entry_array[ldocounter].ldo_id);
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -0800293
Casey Piper7d7b0522013-09-09 20:42:15 -0700294 /* Set voltage during power on */
295 if (enable) {
296 pm8x41_ldo_set_voltage(&ldo_entry,
297 ldo_entry_array[ldocounter].ldo_voltage);
298 pm8x41_ldo_control(&ldo_entry, enable);
299 } else if(ldo_entry_array[ldocounter].ldo_id != HFPLL_LDO_ID) {
300 pm8x41_ldo_control(&ldo_entry, enable);
301 }
302 ldocounter++;
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -0800303 }
304
Casey Piper7d7b0522013-09-09 20:42:15 -0700305 return NO_ERROR;
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -0800306}
307
Asaf Pensoe6870ff2013-07-07 17:23:56 +0300308static int msm8974_mdss_edp_panel_clock(int enable)
309{
310 if (enable) {
311 mdp_gdsc_ctrl(enable);
312 mdp_clock_init();
313 edp_clk_enable();
Asaf Pensoe6870ff2013-07-07 17:23:56 +0300314 } else if (!target_cont_splash_screen()) {
315 /* Add here for continuous splash */
Kuogee Hsiehdf636eb2013-08-01 14:52:08 -0700316 edp_clk_disable();
317 mdp_clock_disable();
318 mdp_gdsc_ctrl(enable);
Asaf Pensoe6870ff2013-07-07 17:23:56 +0300319 }
320
321 return 0;
322}
323
324static int msm8974_edp_panel_power(int enable)
325{
326 struct pm8x41_gpio gpio36_param = {
327 .direction = PM_GPIO_DIR_OUT,
Kuogee Hsieh60ac92e2013-10-04 15:51:37 -0700328 .function = PM_GPIO_FUNC_2,
329 .vin_sel = 2, /* VIN_2 */
330 .pull = PM_GPIO_PULL_UP_1_5 | PM_GPIO_PULLDOWN_10,
Asaf Pensoe6870ff2013-07-07 17:23:56 +0300331 .output_buffer = PM_GPIO_OUT_CMOS,
Kuogee Hsieh60ac92e2013-10-04 15:51:37 -0700332 .out_strength = PM_GPIO_OUT_DRIVE_HIGH,
Asaf Pensoe6870ff2013-07-07 17:23:56 +0300333 };
334
335 struct pm8x41_ldo ldo12 = LDO(PM8x41_LDO12, PLDO_TYPE);
336
337 if (enable) {
338 /* Enable backlight */
339 dprintf(SPEW, "Enable Backlight\n");
Kuogee Hsieh7c3982a2013-12-18 14:13:45 -0800340 msm8974_pwm_backlight_ctrl(36, 8, 1);
Asaf Pensoe6870ff2013-07-07 17:23:56 +0300341 dprintf(SPEW, "Enable Backlight Done\n");
342
343 /* Turn on LDO12 for edp vdda */
344 dprintf(SPEW, "Setting LDO12 n");
345 pm8x41_ldo_set_voltage(&ldo12, 1800000);
346 pm8x41_ldo_control(&ldo12, enable);
347 dprintf(SPEW, "Setting LDO12 Done\n");
348
349 /* Panel Enable */
350 dprintf(SPEW, "Panel Enable\n");
351 gpio_tlmm_config(58, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_8MA,
352 GPIO_DISABLE);
353 gpio_set(58, 2);
354 dprintf(SPEW, "Panel Enable Done\n");
355 } else {
356 /* Keep LDO12 on, otherwise kernel will not boot */
Kuogee Hsiehdf636eb2013-08-01 14:52:08 -0700357 gpio_set(58, 0);
Kuogee Hsieh7c3982a2013-12-18 14:13:45 -0800358 msm8974_pwm_backlight_ctrl(36, 8, 0);
Asaf Pensoe6870ff2013-07-07 17:23:56 +0300359 }
360
361 return 0;
362}
363
Aravind Venkateswaran35d110b2014-02-25 16:45:11 -0800364void target_display_init(const char *panel_name)
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -0800365{
366 uint32_t hw_id = board_hardware_id();
Casey Piper8ac505c2013-09-05 15:00:30 -0700367 uint32_t panel_loop = 0;
368 uint32_t ret = 0;
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -0800369 switch (hw_id) {
Asaf Pensoe6870ff2013-07-07 17:23:56 +0300370 case HW_PLATFORM_LIQUID:
Kuogee Hsiehdf636eb2013-08-01 14:52:08 -0700371 edp_panel_init(&(panel.panel_info));
Asaf Pensoe6870ff2013-07-07 17:23:56 +0300372 panel.clk_func = msm8974_mdss_edp_panel_clock;
373 panel.power_func = msm8974_edp_panel_power;
374 panel.fb.base = (void *)EDP_FB_ADDR;
Asaf Pensoe6870ff2013-07-07 17:23:56 +0300375 panel.fb.format = FB_FORMAT_RGB888;
376 panel.mdp_rev = MDP_REV_50;
Casey Piper7d7b0522013-09-09 20:42:15 -0700377
378 if (msm_display_init(&panel)) {
379 dprintf(CRITICAL, "edp init failed!\n");
380 return;
381 }
382
383 edp_enable = 1;
Asaf Pensoe6870ff2013-07-07 17:23:56 +0300384 break;
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -0800385 default:
Casey Piper8ac505c2013-09-05 15:00:30 -0700386 do {
Justin Philipd4b293a2014-09-17 12:26:49 +0530387 target_force_cont_splash_disable(false);
Aravind Venkateswaran927e9102014-02-25 17:16:49 -0800388 ret = gcdb_display_init(panel_name, MDP_REV_50,
389 MIPI_FB_ADDR);
Casey Piper9cdb75d2013-10-01 15:51:04 -0700390 if (!ret || ret == ERR_NOT_SUPPORTED) {
391 break;
392 } else {
Casey Piper8ac505c2013-09-05 15:00:30 -0700393 target_force_cont_splash_disable(true);
394 msm_display_off();
Casey Piper8ac505c2013-09-05 15:00:30 -0700395 }
Casey Piper8ac505c2013-09-05 15:00:30 -0700396 } while (++panel_loop <= oem_panel_max_auto_detect_panels());
Casey Piper7d7b0522013-09-09 20:42:15 -0700397 break;
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -0800398 }
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -0800399}
400
Aravind Venkateswaran497653f2014-02-25 14:42:43 -0800401void target_display_shutdown(void)
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -0800402{
Casey Piper7d7b0522013-09-09 20:42:15 -0700403 uint32_t hw_id = board_hardware_id();
404 switch (hw_id) {
405 case HW_PLATFORM_LIQUID:
406 if (edp_enable)
407 msm_display_off();
408 break;
409 default:
410 gcdb_display_shutdown();
411 break;
412 }
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -0800413}