ACPI / LPSS: mask the UART TX completion interrupt
Intel LPSS provides an extra TX byte counter and an extra TX
completion interrupt for some of its bus controllers. However,
there is no use for the extra UART interrupt and it has to be
masked out during initialization.
Otherwise, if the firmware does not mask the interrupt and
the driver does not clear it, it may cause an interrupt flood
freezing the board to happen.
Add code masking that problematic interrupt to the ACPI LPSS driver.
[rjw: Changelog]
Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
1 file changed