ide: use PIO/MMIO operations directly where possible (v2)
This results in smaller/faster/simpler code and allows future optimizations.
Also remove no longer needed ide[_mm]_{inl,outl}() and ide_hwif_t.{INL,OUTL}.
v2:
* updated for scc_pata
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
diff --git a/drivers/ide/pci/tc86c001.c b/drivers/ide/pci/tc86c001.c
index 4e89380..b408508 100644
--- a/drivers/ide/pci/tc86c001.c
+++ b/drivers/ide/pci/tc86c001.c
@@ -45,7 +45,7 @@
scr &= (speed < XFER_MW_DMA_0) ? 0xf8ff : 0xff0f;
scr |= mode;
- hwif->OUTW(scr, scr_port);
+ outw(scr, scr_port);
return ide_config_drive_speed(drive, speed);
}
@@ -89,15 +89,15 @@
"attempting recovery...\n", drive->name);
/* Stop DMA */
- hwif->OUTB(dma_cmd & ~0x01, hwif->dma_command);
+ outb(dma_cmd & ~0x01, hwif->dma_command);
/* Setup the dummy DMA transfer */
- hwif->OUTW(0, sc_base + 0x0a); /* Sector Count */
- hwif->OUTW(0, twcr_port); /* Transfer Word Count 1 or 2 */
+ outw(0, sc_base + 0x0a); /* Sector Count */
+ outw(0, twcr_port); /* Transfer Word Count 1 or 2 */
/* Start the dummy DMA transfer */
- hwif->OUTB(0x00, hwif->dma_command); /* clear R_OR_WCTR for write */
- hwif->OUTB(0x01, hwif->dma_command); /* set START_STOPBM */
+ outb(0x00, hwif->dma_command); /* clear R_OR_WCTR for write */
+ outb(0x01, hwif->dma_command); /* set START_STOPBM */
/*
* If an interrupt was pending, it should come thru shortly.
@@ -128,8 +128,8 @@
* the appropriate system control registers for DMA to work
* with LBA48 and ATAPI devices...
*/
- hwif->OUTW(nsectors, sc_base + 0x0a); /* Sector Count */
- hwif->OUTW(SECTOR_SIZE / 2, twcr_port); /* Transfer Word Count 1/2 */
+ outw(nsectors, sc_base + 0x0a); /* Sector Count */
+ outw(SECTOR_SIZE / 2, twcr_port); /* Transfer Word Count 1/2 */
/* Install our timeout expiry hook, saving the current handler... */
ide_set_hwifdata(hwif, hwgroup->expiry);
@@ -168,7 +168,7 @@
}
/* System Control 1 Register bit 11 (ATA Hard Reset) write */
- hwif->OUTW(scr1, sc_base + 0x00);
+ outw(scr1, sc_base + 0x00);
return 0;
}
@@ -204,13 +204,13 @@
u16 scr1 = hwif->INW(sc_base + 0x00);;
/* System Control 1 Register bit 15 (Soft Reset) set */
- hwif->OUTW(scr1 | 0x8000, sc_base + 0x00);
+ outw(scr1 | 0x8000, sc_base + 0x00);
/* System Control 1 Register bit 14 (FIFO Reset) set */
- hwif->OUTW(scr1 | 0x4000, sc_base + 0x00);
+ outw(scr1 | 0x4000, sc_base + 0x00);
/* System Control 1 Register: reset clear */
- hwif->OUTW(scr1 & ~0xc000, sc_base + 0x00);
+ outw(scr1 & ~0xc000, sc_base + 0x00);
/* Store the system control register base for convenience... */
hwif->config_data = sc_base;
@@ -228,7 +228,7 @@
* Sector Count Control Register bits 0 and 1 set:
* software sets Sector Count Register for master and slave device
*/
- hwif->OUTW(0x0003, sc_base + 0x0c);
+ outw(0x0003, sc_base + 0x0c);
/* Sector Count Register limit */
hwif->rqsize = 0xffff;