commit | 0f630fcbe5409aaab1a29b48434b28f41bc360ff | [log] [tgz] |
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author | Arkadi Sharshevsky <arkadis@mellanox.com> | Tue Mar 28 17:24:11 2017 +0200 |
committer | David S. Miller <davem@davemloft.net> | Tue Mar 28 17:11:54 2017 -0700 |
tree | c39071828e549a5a1dc337a55cfd855c1b164c8d | |
parent | 1555d204e743b6956d2be294a317121f6112238d [diff] |
mlxsw: reg: Add counter fields to RITR register Update RITR for counter support. This allows adding counters for ASIC's router ports. Signed-off-by: Arkadi Sharshevsky <arkadis@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>