tree cdef5ea90c240a79b45cbbc8645bd5a635f95463
parent 2d2843e614f6f7aced9dd351a056ac1150d3f82f
parent a701fe3851d9c7f6bd27bc0b92ca1668a42c8406
author Linus Torvalds <torvalds@linux-foundation.org> 1376672418 -0700
committer Linus Torvalds <torvalds@linux-foundation.org> 1376672418 -0700
mergetag object a701fe3851d9c7f6bd27bc0b92ca1668a42c8406
 type commit
 tag clk-fixes-for-linus
 tagger Mike Turquette <mturquette@linaro.org> 1376413353 -0700
 
 Two small fixes for the Zynq clock controller introduced in 3.11-rc1 and
 another Exynos clock patch which fixes a regression that prevents the
 video pipeline from functioning on that platform.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.12 (GNU/Linux)
 
 iQIcBAABAgAGBQJSCma3AAoJEDqPOy9afJhJI/QP/R5kIvB3osg7ZGXYXzHtC4nu
 EamZXz77Wg/fvpktaLP6C5eDjJgYKgUV2qwLvjurxRjpeJ4GmLlf0ieB8XknI8XQ
 8BFjIk4ugvfqjWJ3VxO5Gcc1VdTAgpyZHVUbrmRMmAa/lWDO0BUFDdmyIguY7DoN
 ydrWKBESnT/4tQ2e+a0i+/mzBqaLOrc5hzL2g76TUHDNO0XlFQpVIO4buI9+dlpb
 maH9Be+Mg7q6JbTg6RdetZuJ7IowaYSOL5fDmGJPBuzbclpZ4fmDjpWCt//vAH4c
 M+2mi6E0PjOXNv5F5R+A5Vg4oYAnXFLBay8eg+ss4ffSdV4XA0gRHUVUA4MF11FJ
 rGJPhvNSOiuhnA2P3gNJd7EMHXLsZedLLHd00N5ZoOrSB9sTs7Q8qUiBnh1cCms/
 /amCZBJQV8qZpyutn4lQC575JmGwysmou6Upg1f97GsqCVSIGQle+JjqcKJJ70Qr
 jjTxg5/JKupcDhvJntfWm17z8dRdScsjzRnpWTNa1QeD48JJGyottbbX739pjtzC
 afz8RqW3NDI7gwFMHcz6uo5hTsDByXP9NHexIDmgoDjxVu/NGOrQTegjRdFiE3k8
 AZ1VNQZoa+nwp8TDxbc7XMxW/fg+noTZw3E+IvExw+jo+x0HSiYnsL3VxGlDBPlA
 b4D9DkTR2z+u5EAMztnC
 =C3go
 -----END PGP SIGNATURE-----

Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mturquette/linux

Pull clock controller fixes from Michael Turquette:
 "Two small fixes for the Zynq clock controller introduced in 3.11-rc1
  and another Exynos clock patch which fixes a regression that prevents
  the video pipeline from functioning on that platform"

* tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mturquette/linux:
  clk: exynos4: Add CLK_GET_RATE_NOCACHE flag for the Exynos4x12 ISP clocks
  clk/zynq/clkc: Add CLK_SET_RATE_PARENT flag to ethernet muxes
  clk/zynq/clkc: Add dedicated spinlock for the SWDT