| commit | 108f303f0ed92549b061e08a18361ad4bd540b27 | [log] [tgz] |
|---|---|---|
| author | Robert Jarzmik <robert.jarzmik@free.fr> | Wed Jul 30 22:51:01 2014 +0200 |
| committer | Mike Turquette <mturquette@linaro.org> | Tue Sep 30 12:31:31 2014 -0700 |
| tree | d2351bf8d0f576d4ea0cc18ccf6b7a4376939331 | |
| parent | 53f3394a0fe97420ec260e4dad7854add90a66dd [diff] |
arm: pxa: add clock pll selection bits Add missing bits for CCCR and CCSR : - CPLL and PPLL selection, either full speed or 13MHz - CPSR masks Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Mike Turquette <mturquette@linaro.org>