commit 119537c092638bf8a0672415024639353c773bb1
author Thiemo Seufer <ths@networkno.de> Mon Mar 19 00:13:37 2007 +0000
committer Ralf Baechle <ralf@linux-mips.org> Mon Mar 19 20:22:43 2007 +0000
tree af3fc85f2d5a4bf93fd1cd82b228054ac6b5fe42
parent 72ede9b18967e7a8a62a88f164f003193f6d891f

[MIPS] Misc fixes for plat_irq_dispatch functions

 o adds missing ST0_IM masks, which caused the logging of valid interrupts
   as spurious
 o stops pnx8550 to log every interrupt as spurious
 o adds cause register masks for ip22/ip32, which caused handling of masked
   interrupts
 o removes some superfluous parentheses in the SNI interrupt code

Signed-Off-By: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

arch/mips/sni/pcit.c

diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c
index 8d6b3d5..1dfc3f0 100644
--- a/arch/mips/sni/pcit.c
+++ b/arch/mips/sni/pcit.c
@@ -271,7 +271,7 @@
 
 static void sni_pcit_hwint(void)
 {
-	u32 pending = (read_c0_cause() & read_c0_status());
+	u32 pending = read_c0_cause() & read_c0_status();
 
 	if (pending & C_IRQ1)
 		pcit_hwint1();
@@ -285,7 +285,7 @@
 
 static void sni_pcit_hwint_cplus(void)
 {
-	u32 pending = (read_c0_cause() & read_c0_status());
+	u32 pending = read_c0_cause() & read_c0_status();
 
 	if (pending & C_IRQ0)
 		pcit_hwint0();