tree 785e5972266aabba11ed9ea5d825918acae8c929
parent 2a0609c02e6558df6075f258af98a54a74b050ff
author Chrzaniuk, Hubert <hubert.chrzaniuk@intel.com> 1455118517 +0100
committer Len Brown <len.brown@intel.com> 1457855737 -0400

tools/power turbostat: Intel Xeon x200: fix erroneous bclk value

x200 does not enable any way to programmatically obtain bus clock
speed. Bclk for the architecture has a fixed value of 100 MHz.
At the same time x200 cannot be included in has_snb_msrs since
it does not support C7 idle state.

prior to this patch, MHz values reported on this chip
were erroneously calculated using bclk of 133MHz,
causing MHz values to be reported 33% higher than actual.

Signed-off-by: Hubert Chrzaniuk <hubert.chrzaniuk@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>