| commit | 4b8f7a11c9fb680895e5079788653a59d6bdde16 | [log] [tgz] |
|---|---|---|
| author | Andrew Lunn <andrew@lunn.ch> | Sat Feb 22 20:14:52 2014 +0100 |
| committer | Jason Cooper <jason@lakedaemon.net> | Sat Feb 22 20:43:49 2014 +0000 |
| tree | d20f78bd55eb043f8f9e1be5e702301263b73079 | |
| parent | 3c317d00ba4a9489c161857a574432c61fde4a2a [diff] |
ARM: MM: Add DT binding for Feroceon L2 cache Instantiate the L2 cache from DT. Indicate in DT where the cache control register is so that it is possible to enable/disable write through on the CPU. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>