| commit | 86576fbe201b7617e9dc689df0e5df0807acdd30 | [log] [tgz] |
|---|---|---|
| author | Tomasz Figa <t.figa@samsung.com> | Sat Dec 21 07:58:38 2013 +0900 |
| committer | Kukjin Kim <kgene.kim@samsung.com> | Sat Dec 21 07:58:38 2013 +0900 |
| tree | c24f9da39e2d6f9a61bd070a87b4fd0bf238c508 | |
| parent | a98e3190fc7dbb6157ef51ce8d92a36b06d282bb [diff] |
clk: samsung: exynos4: Fix definition of div_mmc_pre4 divider The clock was missing CLK_SET_RATE_PARENT flag, which caused rate setting failures due to inability of reconfiguration of second divider behind it. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>