| commit | 170594502cf591fd0789d7e5239937b1a87af4c6 | [log] [tgz] |
|---|---|---|
| author | Chris Wilson <chris@chris-wilson.co.uk> | Mon Feb 13 17:15:32 2017 +0000 |
| committer | Chris Wilson <chris@chris-wilson.co.uk> | Mon Feb 13 20:45:45 2017 +0000 |
| tree | 77757a21dd505037cace248c180f0d79f7c09d00 | |
| parent | 3d81d589d6e3c89b687771074f65cb8f3b59ccf3 [diff] |
drm/i915: Test coherency of and barriers between cache domains Write into an object using WB, WC, GTT, and GPU paths and make sure that our internal API is sufficient to ensure coherent reads and writes. v2: Avoid invalid free upon allocation error Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170213171558.20942-21-chris@chris-wilson.co.uk