tree 2c00dd66c1fba12ce3b3b89cd77cf87a025c8e49
parent 8ccb6dc6e999008bc5d50bdb5badedd636f58e1c
author Andrew Jeffery <andrew@aj.id.au> 1485238606 +1030
committer Linus Walleij <linus.walleij@linaro.org> 1485438343 +0100

gpio: aspeed: Add banks Y, Z, AA, AB and AC

This is less straight-forward than one would hope, as some banks only
have 4 pins rather than 8, others are output only, yet more (W and
X, already supported) are input-only, and in the case of the g4 SoC bank
AC doesn't exist.

Add some structs to describe the varying properties of different banks
and integrate mechanisms to deny requests for unsupported
configurations.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>