ARM: dts: msm: add ipa nodes for kona target
Add devicetree nodes for IPA and GSI drivers. This
is to enable IPA and GSI H/W blocks for embedded
and tethered IP packet processing offload.
Change-Id: I8e5a54b1a0850c58ab8484257da13abf29e38c60
Signed-off-by: Ghanim Fodi <gfodi@codeaurora.org>
diff --git a/arch/arm64/boot/dts/qcom/kona.dtsi b/arch/arm64/boot/dts/qcom/kona.dtsi
index 274e13e..543e45b 100644
--- a/arch/arm64/boot/dts/qcom/kona.dtsi
+++ b/arch/arm64/boot/dts/qcom/kona.dtsi
@@ -1292,6 +1292,103 @@
};
};
+ qcom,msm_gsi {
+ compatible = "qcom,msm_gsi";
+ };
+
+ qcom,rmnet-ipa {
+ compatible = "qcom,rmnet-ipa3";
+ qcom,rmnet-ipa-ssr;
+ qcom,ipa-platform-type-msm;
+ qcom,ipa-advertise-sg-support;
+ qcom,ipa-napi-enable;
+ };
+
+ qcom,ipa_fws {
+ compatible = "qcom,pil-tz-generic";
+ qcom,pas-id = <0xf>;
+ qcom,firmware-name = "ipa_fws";
+ qcom,pil-force-shutdown;
+ memory-region = <&pil_ipa_fw_mem>;
+ };
+
+ ipa_hw: qcom,ipa@1e00000 {
+ compatible = "qcom,ipa";
+ reg =
+ <0x1e00000 0x84000>,
+ <0x1e04000 0x23000>;
+ reg-names = "ipa-base", "gsi-base";
+ interrupts =
+ <0 311 IRQ_TYPE_LEVEL_HIGH>,
+ <0 432 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ipa-irq", "gsi-irq";
+ qcom,ipa-hw-ver = <17>; /* IPA core version = IPAv4.5 */
+ qcom,ipa-hw-mode = <0>;
+ qcom,ee = <0>;
+ qcom,use-ipa-tethering-bridge;
+ qcom,mhi-event-ring-id-limits = <9 11>; /* start and end */
+ qcom,modem-cfg-emb-pipe-flt;
+ qcom,use-ipa-pm;
+ qcom,bandwidth-vote-for-ipa;
+ qcom,use-64-bit-dma-mask;
+ qcom,msm-bus,name = "ipa";
+ qcom,msm-bus,num-cases = <5>;
+ qcom,msm-bus,num-paths = <4>;
+ qcom,msm-bus,vectors-KBps =
+ /* No vote */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 0 0>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 0>,
+ <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 0>,
+
+ /* SVS2 */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 80000 600000>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 80000 350000>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 40000 40000>,
+ <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 125>,
+
+ /* SVS */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 80000 640000>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 80000 640000>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 80000 80000>,
+ <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 250>,
+
+ /* NOMINAL */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 206000 960000>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 206000 960000>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 206000 160000>,
+ <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 500>,
+
+ /* TURBO */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 206000 3600000>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 206000 3600000>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 206000 300000>,
+ <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 600>;
+
+ qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL",
+ "TURBO";
+ qcom,throughput-threshold = <310 600 1000>;
+ qcom,scaling-exceptions = <>;
+ };
+
+ ipa_smmu_ap: ipa_smmu_ap {
+ compatible = "qcom,ipa-smmu-ap-cb";
+ iommus = <&apps_smmu 0x5C0 0x0>;
+ qcom,iommu-dma = "bypass";
+ };
+
+ ipa_smmu_wlan: ipa_smmu_wlan {
+ compatible = "qcom,ipa-smmu-wlan-cb";
+ iommus = <&apps_smmu 0x5C1 0x0>;
+ qcom,iommu-dma = "bypass";
+ };
+
+ ipa_smmu_uc: ipa_smmu_uc {
+ compatible = "qcom,ipa-smmu-uc-cb";
+ iommus = <&apps_smmu 0x5C2 0x0>;
+ qcom,iommu-dma = "bypass";
+ };
+
qcom,glink {
compatible = "qcom,glink";
#address-cells = <1>;