tree 3debf735ae039342cfad036c965904d5a0ffe5c4
parent cdab0d4ecc1a890aece7102c2074bf73175b9935
author Ben Zhang <benzh@chromium.org> 1450216285 -0800
committer Mark Brown <broonie@kernel.org> 1450293659 +0000

ASoC: rt5677: Reconfigure PLL1 after resume

Sometimes PLL1 stops working if the codec loses power
during suspend (when pow-ldo2 or reset gpio is used).
MX-7Bh(RT5677_PLL1_CTRL2) is cleared and won't be restored
by regcache since it's volatile. MX-7Bh has one status bit
and M code for PLL1. rt5677_set_dai_pll doesn't reconfigure
PLL1 after resume because it thinks the PLL params are not
changed.

This patch clears the cached PLL params at resume so that
rt5677_set_dai_pll can reconfigure the PLL after resume.

Signed-off-by: Ben Zhang <benzh@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>