arch/arm/boot/dts/armada-xp-mv78260.dtsi - kernel/msm-4.19 - Gitiles

 /*
  * Device Tree Include file for Marvell Armada XP family SoC
  *
  * Copyright (C) 2012 Marvell
  *
  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  *
  * This file is dual-licensed: you can use it either under the terms
  * of the GPL or the X11 license, at your option. Note that this dual
  * licensing only applies to this file, and not this project as a
  * whole.
  *
  *  a) This file is free software; you can redistribute it and/or
  *     modify it under the terms of the GNU General Public License as
  *     published by the Free Software Foundation; either version 2 of the
  *     License, or (at your option) any later version.
  *
  *     This file is distributed in the hope that it will be useful,
  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  *     GNU General Public License for more details.
  *
  * Or, alternatively,
  *
  *  b) Permission is hereby granted, free of charge, to any person
  *     obtaining a copy of this software and associated documentation
  *     files (the "Software"), to deal in the Software without
  *     restriction, including without limitation the rights to use,
  *     copy, modify, merge, publish, distribute, sublicense, and/or
  *     sell copies of the Software, and to permit persons to whom the
  *     Software is furnished to do so, subject to the following
  *     conditions:
  *
  *     The above copyright notice and this permission notice shall be
  *     included in all copies or substantial portions of the Software.
  *
  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  *     OTHER DEALINGS IN THE SOFTWARE.
  *
  * Contains definitions specific to the Armada XP MV78260 SoC that are not
  * common to all Armada XP SoCs.
  */

 #include "armada-xp.dtsi"

 / {
 	model = "Marvell Armada XP MV78260 SoC";
 	compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";

 	aliases {
 		gpio0 = &gpio0;
 		gpio1 = &gpio1;
 		gpio2 = &gpio2;
 	};

 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
 		enable-method = "marvell,armada-xp-smp";

 		cpu@0 {
 			device_type = "cpu";
 			compatible = "marvell,sheeva-v7";
 			reg = <0>;
 			clocks = <&cpuclk 0>;
 			clock-latency = <1000000>;
 		};

 		cpu@1 {
 			device_type = "cpu";
 			compatible = "marvell,sheeva-v7";
 			reg = <1>;
 			clocks = <&cpuclk 1>;
 			clock-latency = <1000000>;
 		};
 	};

 	soc {
 		/*
 		 * MV78260 has 3 PCIe units Gen2.0: Two units can be
 		 * configured as x4 or quad x1 lanes. One unit is
 		 * x4 only.
 		 */
 		pciec: pcie-controller@82000000 {
 			compatible = "marvell,armada-xp-pcie";
 			status = "disabled";
 			device_type = "pci";

 			#address-cells = <3>;
 			#size-cells = <2>;

 			msi-parent = <&mpic>;
 			bus-range = <0x00 0xff>;

 			ranges =
 			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
 				0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000   /* Port 2.0 registers */
 				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
 				0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
 				0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
 				0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000   /* Port 1.0 registers */
 				0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000   /* Port 1.1 registers */
 				0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000   /* Port 1.2 registers */
 				0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000   /* Port 1.3 registers */
 				0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
 				0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
 				0x82000000 0x2 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
 				0x81000000 0x2 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
 				0x82000000 0x3 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
 				0x81000000 0x3 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
 				0x82000000 0x4 0     MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
 				0x81000000 0x4 0     MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */

 				0x82000000 0x5 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
 				0x81000000 0x5 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO  */
 				0x82000000 0x6 0     MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
 				0x81000000 0x6 0     MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO  */
 				0x82000000 0x7 0     MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
 				0x81000000 0x7 0     MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO  */
 				0x82000000 0x8 0     MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
 				0x81000000 0x8 0     MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO  */

 				0x82000000 0x9 0     MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
 				0x81000000 0x9 0     MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO  */>;

 			pcie1: pcie@1,0 {
 				device_type = "pci";
 				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
 				reg = <0x0800 0 0 0 0>;
 				#address-cells = <3>;
 				#size-cells = <2>;
 				#interrupt-cells = <1>;
 				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
 					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
 				interrupt-map-mask = <0 0 0 0>;
 				interrupt-map = <0 0 0 0 &mpic 58>;
 				marvell,pcie-port = <0>;
 				marvell,pcie-lane = <0>;
 				clocks = <&gateclk 5>;
 				status = "disabled";
 			};

 			pcie2: pcie@2,0 {
 				device_type = "pci";
 				assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
 				reg = <0x1000 0 0 0 0>;
 				#address-cells = <3>;
 				#size-cells = <2>;
 				#interrupt-cells = <1>;
 				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
 					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
 				interrupt-map-mask = <0 0 0 0>;
 				interrupt-map = <0 0 0 0 &mpic 59>;
 				marvell,pcie-port = <0>;
 				marvell,pcie-lane = <1>;
 				clocks = <&gateclk 6>;
 				status = "disabled";
 			};

 			pcie3: pcie@3,0 {
 				device_type = "pci";
 				assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
 				reg = <0x1800 0 0 0 0>;
 				#address-cells = <3>;
 				#size-cells = <2>;
 				#interrupt-cells = <1>;
 				ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
 					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
 				interrupt-map-mask = <0 0 0 0>;
 				interrupt-map = <0 0 0 0 &mpic 60>;
 				marvell,pcie-port = <0>;
 				marvell,pcie-lane = <2>;
 				clocks = <&gateclk 7>;
 				status = "disabled";
 			};

 			pcie4: pcie@4,0 {
 				device_type = "pci";
 				assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
 				reg = <0x2000 0 0 0 0>;
 				#address-cells = <3>;
 				#size-cells = <2>;
 				#interrupt-cells = <1>;
 				ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
 					  0x81000000 0 0 0x81000000 0x4 0 1 0>;
 				interrupt-map-mask = <0 0 0 0>;
 				interrupt-map = <0 0 0 0 &mpic 61>;
 				marvell,pcie-port = <0>;
 				marvell,pcie-lane = <3>;
 				clocks = <&gateclk 8>;
 				status = "disabled";
 			};

 			pcie5: pcie@5,0 {
 				device_type = "pci";
 				assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
 				reg = <0x2800 0 0 0 0>;
 				#address-cells = <3>;
 				#size-cells = <2>;
 				#interrupt-cells = <1>;
 				ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
 					  0x81000000 0 0 0x81000000 0x5 0 1 0>;
 				interrupt-map-mask = <0 0 0 0>;
 				interrupt-map = <0 0 0 0 &mpic 62>;
 				marvell,pcie-port = <1>;
 				marvell,pcie-lane = <0>;
 				clocks = <&gateclk 9>;
 				status = "disabled";
 			};

 			pcie6: pcie@6,0 {
 				device_type = "pci";
 				assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
 				reg = <0x3000 0 0 0 0>;
 				#address-cells = <3>;
 				#size-cells = <2>;
 				#interrupt-cells = <1>;
 				ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
 					  0x81000000 0 0 0x81000000 0x6 0 1 0>;
 				interrupt-map-mask = <0 0 0 0>;
 				interrupt-map = <0 0 0 0 &mpic 63>;
 				marvell,pcie-port = <1>;
 				marvell,pcie-lane = <1>;
 				clocks = <&gateclk 10>;
 				status = "disabled";
 			};

 			pcie7: pcie@7,0 {
 				device_type = "pci";
 				assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
 				reg = <0x3800 0 0 0 0>;
 				#address-cells = <3>;
 				#size-cells = <2>;
 				#interrupt-cells = <1>;
 				ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
 					  0x81000000 0 0 0x81000000 0x7 0 1 0>;
 				interrupt-map-mask = <0 0 0 0>;
 				interrupt-map = <0 0 0 0 &mpic 64>;
 				marvell,pcie-port = <1>;
 				marvell,pcie-lane = <2>;
 				clocks = <&gateclk 11>;
 				status = "disabled";
 			};

 			pcie8: pcie@8,0 {
 				device_type = "pci";
 				assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
 				reg = <0x4000 0 0 0 0>;
 				#address-cells = <3>;
 				#size-cells = <2>;
 				#interrupt-cells = <1>;
 				ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
 					  0x81000000 0 0 0x81000000 0x8 0 1 0>;
 				interrupt-map-mask = <0 0 0 0>;
 				interrupt-map = <0 0 0 0 &mpic 65>;
 				marvell,pcie-port = <1>;
 				marvell,pcie-lane = <3>;
 				clocks = <&gateclk 12>;
 				status = "disabled";
 			};

 			pcie9: pcie@9,0 {
 				device_type = "pci";
 				assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
 				reg = <0x4800 0 0 0 0>;
 				#address-cells = <3>;
 				#size-cells = <2>;
 				#interrupt-cells = <1>;
 				ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
 					  0x81000000 0 0 0x81000000 0x9 0 1 0>;
 				interrupt-map-mask = <0 0 0 0>;
 				interrupt-map = <0 0 0 0 &mpic 99>;
 				marvell,pcie-port = <2>;
 				marvell,pcie-lane = <0>;
 				clocks = <&gateclk 26>;
 				status = "disabled";
 			};
 		};

 		internal-regs {
 			gpio0: gpio@18100 {
 				compatible = "marvell,orion-gpio";
 				reg = <0x18100 0x40>;
 				ngpios = <32>;
 				gpio-controller;
 				#gpio-cells = <2>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
 				interrupts = <82>, <83>, <84>, <85>;
 			};

 			gpio1: gpio@18140 {
 				compatible = "marvell,orion-gpio";
 				reg = <0x18140 0x40>;
 				ngpios = <32>;
 				gpio-controller;
 				#gpio-cells = <2>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
 				interrupts = <87>, <88>, <89>, <90>;
 			};

 			gpio2: gpio@18180 {
 				compatible = "marvell,orion-gpio";
 				reg = <0x18180 0x40>;
 				ngpios = <3>;
 				gpio-controller;
 				#gpio-cells = <2>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
 				interrupts = <91>;
 			};

 			eth3: ethernet@34000 {
 				compatible = "marvell,armada-xp-neta";
 				reg = <0x34000 0x4000>;
 				interrupts = <14>;
 				clocks = <&gateclk 1>;
 				status = "disabled";
 			};
 		};
 	};
 };

 &pinctrl {
 	compatible = "marvell,mv78260-pinctrl";
 };
	/*
	* Device Tree Include file for Marvell Armada XP family SoC
	*
	* Copyright (C) 2012 Marvell
	*
	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	*
	* This file is dual-licensed: you can use it either under the terms
	* of the GPL or the X11 license, at your option. Note that this dual
	* licensing only applies to this file, and not this project as a
	* whole.
	*
	* a) This file is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License as
	* published by the Free Software Foundation; either version 2 of the
	* License, or (at your option) any later version.
	*
	* This file is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* Or, alternatively,
	*
	* b) Permission is hereby granted, free of charge, to any person
	* obtaining a copy of this software and associated documentation
	* files (the "Software"), to deal in the Software without
	* restriction, including without limitation the rights to use,
	* copy, modify, merge, publish, distribute, sublicense, and/or
	* sell copies of the Software, and to permit persons to whom the
	* Software is furnished to do so, subject to the following
	* conditions:
	*
	* The above copyright notice and this permission notice shall be
	* included in all copies or substantial portions of the Software.
	*
	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	* OTHER DEALINGS IN THE SOFTWARE.
	*
	* Contains definitions specific to the Armada XP MV78260 SoC that are not
	* common to all Armada XP SoCs.
	*/

	#include "armada-xp.dtsi"

	/ {
	model = "Marvell Armada XP MV78260 SoC";
	compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";

	aliases {
	gpio0 = &gpio0;
	gpio1 = &gpio1;
	gpio2 = &gpio2;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	enable-method = "marvell,armada-xp-smp";

	cpu@0 {
	device_type = "cpu";
	compatible = "marvell,sheeva-v7";
	reg = <0>;
	clocks = <&cpuclk 0>;
	clock-latency = <1000000>;
	};

	cpu@1 {
	device_type = "cpu";
	compatible = "marvell,sheeva-v7";
	reg = <1>;
	clocks = <&cpuclk 1>;
	clock-latency = <1000000>;
	};
	};

	soc {
	/*
	* MV78260 has 3 PCIe units Gen2.0: Two units can be
	* configured as x4 or quad x1 lanes. One unit is
	* x4 only.
	*/
	pciec: pcie-controller@82000000 {
	compatible = "marvell,armada-xp-pcie";
	status = "disabled";
	device_type = "pci";

	#address-cells = <3>;
	#size-cells = <2>;

	msi-parent = <&mpic>;
	bus-range = <0x00 0xff>;

	ranges =
	<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
	0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
	0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
	0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
	0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
	0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
	0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
	0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
	0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
	0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
	0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
	0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
	0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
	0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
	0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
	0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
	0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */

	0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
	0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
	0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
	0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
	0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
	0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
	0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
	0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */

	0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
	0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;

	pcie1: pcie@1,0 {
	device_type = "pci";
	assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
	reg = <0x0800 0 0 0 0>;
	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
	0x81000000 0 0 0x81000000 0x1 0 1 0>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &mpic 58>;
	marvell,pcie-port = <0>;
	marvell,pcie-lane = <0>;
	clocks = <&gateclk 5>;
	status = "disabled";
	};

	pcie2: pcie@2,0 {
	device_type = "pci";
	assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
	reg = <0x1000 0 0 0 0>;
	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
	0x81000000 0 0 0x81000000 0x2 0 1 0>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &mpic 59>;
	marvell,pcie-port = <0>;
	marvell,pcie-lane = <1>;
	clocks = <&gateclk 6>;
	status = "disabled";
	};

	pcie3: pcie@3,0 {
	device_type = "pci";
	assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
	reg = <0x1800 0 0 0 0>;
	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
	0x81000000 0 0 0x81000000 0x3 0 1 0>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &mpic 60>;
	marvell,pcie-port = <0>;
	marvell,pcie-lane = <2>;
	clocks = <&gateclk 7>;
	status = "disabled";
	};

	pcie4: pcie@4,0 {
	device_type = "pci";
	assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
	reg = <0x2000 0 0 0 0>;
	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
	0x81000000 0 0 0x81000000 0x4 0 1 0>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &mpic 61>;
	marvell,pcie-port = <0>;
	marvell,pcie-lane = <3>;
	clocks = <&gateclk 8>;
	status = "disabled";
	};

	pcie5: pcie@5,0 {
	device_type = "pci";
	assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
	reg = <0x2800 0 0 0 0>;
	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
	0x81000000 0 0 0x81000000 0x5 0 1 0>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &mpic 62>;
	marvell,pcie-port = <1>;
	marvell,pcie-lane = <0>;
	clocks = <&gateclk 9>;
	status = "disabled";
	};

	pcie6: pcie@6,0 {
	device_type = "pci";
	assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
	reg = <0x3000 0 0 0 0>;
	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
	0x81000000 0 0 0x81000000 0x6 0 1 0>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &mpic 63>;
	marvell,pcie-port = <1>;
	marvell,pcie-lane = <1>;
	clocks = <&gateclk 10>;
	status = "disabled";
	};

	pcie7: pcie@7,0 {
	device_type = "pci";
	assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
	reg = <0x3800 0 0 0 0>;
	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
	0x81000000 0 0 0x81000000 0x7 0 1 0>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &mpic 64>;
	marvell,pcie-port = <1>;
	marvell,pcie-lane = <2>;
	clocks = <&gateclk 11>;
	status = "disabled";
	};

	pcie8: pcie@8,0 {
	device_type = "pci";
	assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
	reg = <0x4000 0 0 0 0>;
	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
	0x81000000 0 0 0x81000000 0x8 0 1 0>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &mpic 65>;
	marvell,pcie-port = <1>;
	marvell,pcie-lane = <3>;
	clocks = <&gateclk 12>;
	status = "disabled";
	};

	pcie9: pcie@9,0 {
	device_type = "pci";
	assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
	reg = <0x4800 0 0 0 0>;
	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
	0x81000000 0 0 0x81000000 0x9 0 1 0>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &mpic 99>;
	marvell,pcie-port = <2>;
	marvell,pcie-lane = <0>;
	clocks = <&gateclk 26>;
	status = "disabled";
	};
	};

	internal-regs {
	gpio0: gpio@18100 {
	compatible = "marvell,orion-gpio";
	reg = <0x18100 0x40>;
	ngpios = <32>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	interrupts = <82>, <83>, <84>, <85>;
	};

	gpio1: gpio@18140 {
	compatible = "marvell,orion-gpio";
	reg = <0x18140 0x40>;
	ngpios = <32>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	interrupts = <87>, <88>, <89>, <90>;
	};

	gpio2: gpio@18180 {
	compatible = "marvell,orion-gpio";
	reg = <0x18180 0x40>;
	ngpios = <3>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	interrupts = <91>;
	};

	eth3: ethernet@34000 {
	compatible = "marvell,armada-xp-neta";
	reg = <0x34000 0x4000>;
	interrupts = <14>;
	clocks = <&gateclk 1>;
	status = "disabled";
	};
	};
	};
	};

	&pinctrl {
	compatible = "marvell,mv78260-pinctrl";
	};