tree f3831b0a1978eb3eeb0abf22d90e6c839a66f6f0
parent 9387bfd19b457085189d918ef117ffd63c4d67a0
author Xing Zheng <zhengxing@rock-chips.com> 1457491023 +0800
committer Heiko Stuebner <heiko@sntech.de> 1459076613 +0200

clk: rockchip: allow varying mux parameters for cpuclk pll-sources

Thers are only two parent PLLs that APLL and GPLL for core on the
previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed
GPLL as alternate parent when core is switching freq.

Since RK3399 big.LITTLE architecture, we need to select and adapt
more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>