tree ad65f1b369d44458f3e8900a6e8a3255dfd67d56
parent 1a695a905c18548062509178b98bc91e67510864
author Xing Zheng <zhengxing@rock-chips.com> 1464166316 +0800
committer Heiko Stuebner <heiko@sntech.de> 1464594266 +0200

clk: rockchip: add a dummy clock for the watchdog pclk on rk3399

Like rk3288, the pclk supplying the watchdog is controlled via the
SGRF register area. Additionally the SGRF isn't even writable in
every boot mode.

But still the clock control is available and in the future someone
might want to use it. Therefore define a simple clock for the time
being so that the watchdog driver can read its rate.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Reviewed-by: Stephen Barber <smbarber@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>