commit 32ce4652dc9074385e00f3a5e6fa995e612aa113
author Alex Deucher <alexander.deucher@amd.com> Mon Mar 18 17:03:01 2013 -0400
committer Alex Deucher <alexander.deucher@amd.com> Thu Jun 27 19:16:33 2013 -0400
tree 822e0c3f72c16b65704aa95752349a3d33b315b2
parent f8f84ac5d48c2377131a3c6b8c14e3bdcbf9349e

drm/radeon/dpm: add an enum for pcie gen selection

This makes it easier the understand what the code is
doing.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/radeon/cypress_dpm.c

diff --git a/drivers/gpu/drm/radeon/cypress_dpm.c b/drivers/gpu/drm/radeon/cypress_dpm.c
index c7cb19e..1c6c3a3 100644
--- a/drivers/gpu/drm/radeon/cypress_dpm.c
+++ b/drivers/gpu/drm/radeon/cypress_dpm.c
@@ -344,7 +344,7 @@
 
 }
 
-static u32 cypress_get_maximum_link_speed(struct radeon_ps *radeon_state)
+static enum radeon_pcie_gen cypress_get_maximum_link_speed(struct radeon_ps *radeon_state)
 {
 	struct rv7xx_ps *state = rv770_get_ps(radeon_state);
 
@@ -357,14 +357,16 @@
 							 struct radeon_ps *radeon_new_state,
 							 struct radeon_ps *radeon_current_state)
 {
-	u32 pcie_link_speed_target =  cypress_get_maximum_link_speed(radeon_new_state);
-	u32 pcie_link_speed_current = cypress_get_maximum_link_speed(radeon_current_state);
+	enum radeon_pcie_gen pcie_link_speed_target =
+		cypress_get_maximum_link_speed(radeon_new_state);
+	enum radeon_pcie_gen pcie_link_speed_current =
+		cypress_get_maximum_link_speed(radeon_current_state);
 	u8 request;
 
 	if (pcie_link_speed_target < pcie_link_speed_current) {
-		if (pcie_link_speed_target == 0)
+		if (pcie_link_speed_target == RADEON_PCIE_GEN1)
 			request = PCIE_PERF_REQ_PECI_GEN1;
-		else if (pcie_link_speed_target == 1)
+		else if (pcie_link_speed_target == RADEON_PCIE_GEN2)
 			request = PCIE_PERF_REQ_PECI_GEN2;
 		else
 			request = PCIE_PERF_REQ_PECI_GEN3;
@@ -377,14 +379,16 @@
 							  struct radeon_ps *radeon_new_state,
 							  struct radeon_ps *radeon_current_state)
 {
-	u32 pcie_link_speed_target =  cypress_get_maximum_link_speed(radeon_new_state);
-	u32 pcie_link_speed_current = cypress_get_maximum_link_speed(radeon_current_state);
+	enum radeon_pcie_gen pcie_link_speed_target =
+		cypress_get_maximum_link_speed(radeon_new_state);
+	enum radeon_pcie_gen pcie_link_speed_current =
+		cypress_get_maximum_link_speed(radeon_current_state);
 	u8 request;
 
 	if (pcie_link_speed_target > pcie_link_speed_current) {
-		if (pcie_link_speed_target == 0)
+		if (pcie_link_speed_target == RADEON_PCIE_GEN1)
 			request = PCIE_PERF_REQ_PECI_GEN1;
-		else if (pcie_link_speed_target == 1)
+		else if (pcie_link_speed_target == RADEON_PCIE_GEN2)
 			request = PCIE_PERF_REQ_PECI_GEN2;
 		else
 			request = PCIE_PERF_REQ_PECI_GEN3;