commit | 340a84ce1eddd6671ce0c57d890fd90f6ae27fa2 | [log] [tgz] |
---|---|---|
author | Jerome Brunet <jbrunet@baylibre.com> | Wed Jan 25 11:53:06 2017 +0100 |
committer | Stephen Boyd <sboyd@codeaurora.org> | Thu Jan 26 15:54:48 2017 -0800 |
tree | 07fdbaaf9ff8656f670e7841cfdf8676d487d51d | |
parent | 88c9b70bb2b2182fda8ef764ab49ec9e175c8ee2 [diff] |
clk: meson8b: fix clk81 register address During meson8b clock probe, clk81 register address is fixed twice. First using the meson8b_clk_gates array, then by directly changing meson8b_clk81 register. As a result meson8b_clk81.reg = HHI_MPEG_CLK_CNTL + clk_base + clk_base. Fixed by just removing the second fixup. Fixes: e31a1900c1ff ("meson: clk: Add support for clock gates") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>